This enables support for Designware PCI Express Controller emulation
It provides a controlled environment to debug the linux pci subsystem
Signed-off-by: Gaurav Sharma
---
docs/system/arm/imx8mm-evk.rst | 1 +
hw/arm/Kconfig | 3 +++
hw/arm/fsl-imx8mm.c| 30 ++
include/hw/arm/fsl-imx8mm.h| 10 ++
4 files changed, 44 insertions(+)
diff --git a/docs/system/arm/imx8mm-evk.rst b/docs/system/arm/imx8mm-evk.rst
index f379a1cc97..cabaef157e 100644
--- a/docs/system/arm/imx8mm-evk.rst
+++ b/docs/system/arm/imx8mm-evk.rst
@@ -13,6 +13,7 @@ The ``imx8mm-evk`` machine implements the following devices:
* Generic Interrupt Controller (GICv3)
* 4 UARTs
* 3 USDHC Storage Controllers
+ * 1 Designware PCI Express Controller
* Secure Non-Volatile Storage (SNVS) including an RTC
* Clock Tree
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index b5eb6553f5..6df1478c4f 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -628,11 +628,14 @@ config FSL_IMX8MP_EVK
config FSL_IMX8MM
bool
+imply PCI_DEVICES
select ARM_GIC
select FSL_IMX8MM_ANALOG
select FSL_IMX8MM_CCM
select IMX
select SDHCI
+select PCI_EXPRESS_DESIGNWARE
+select PCI_EXPRESS_FSL_IMX8M_PHY
config FSL_IMX8MM_EVK
bool
diff --git a/hw/arm/fsl-imx8mm.c b/hw/arm/fsl-imx8mm.c
index 0c42fd16f2..09e16786bc 100644
--- a/hw/arm/fsl-imx8mm.c
+++ b/hw/arm/fsl-imx8mm.c
@@ -181,6 +181,10 @@ static void fsl_imx8mm_init(Object *obj)
g_autofree char *name = g_strdup_printf("usdhc%d", i + 1);
object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC);
}
+
+object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);
+object_initialize_child(obj, "pcie_phy", &s->pcie_phy,
+TYPE_FSL_IMX8M_PCIE_PHY);
}
static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)
@@ -373,6 +377,30 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error
**errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0,
fsl_imx8mm_memmap[FSL_IMX8MM_SNVS_HP].addr);
+/* PCIe */
+if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie), errp)) {
+return;
+}
+sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0,
+fsl_imx8mm_memmap[FSL_IMX8MM_PCIE1].addr);
+
+sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0,
+ qdev_get_gpio_in(gicdev, FSL_IMX8MM_PCI_INTA_IRQ));
+sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1,
+ qdev_get_gpio_in(gicdev, FSL_IMX8MM_PCI_INTB_IRQ));
+sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2,
+ qdev_get_gpio_in(gicdev, FSL_IMX8MM_PCI_INTC_IRQ));
+sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3,
+ qdev_get_gpio_in(gicdev, FSL_IMX8MM_PCI_INTD_IRQ));
+sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 4,
+ qdev_get_gpio_in(gicdev, FSL_IMX8MM_PCI_MSI_IRQ));
+
+if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie_phy), errp)) {
+return;
+}
+sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie_phy), 0,
+fsl_imx8mm_memmap[FSL_IMX8MM_PCIE_PHY1].addr);
+
/* Unimplemented devices */
for (i = 0; i < ARRAY_SIZE(fsl_imx8mm_memmap); i++) {
switch (i) {
@@ -380,6 +408,8 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error
**errp)
case FSL_IMX8MM_CCM:
case FSL_IMX8MM_GIC_DIST:
case FSL_IMX8MM_GIC_REDIST:
+case FSL_IMX8MM_PCIE1:
+case FSL_IMX8MM_PCIE_PHY1:
case FSL_IMX8MM_RAM:
case FSL_IMX8MM_SNVS_HP:
case FSL_IMX8MM_UART1 ... FSL_IMX8MM_UART4:
diff --git a/include/hw/arm/fsl-imx8mm.h b/include/hw/arm/fsl-imx8mm.h
index 985a0a5571..74a1a1349d 100644
--- a/include/hw/arm/fsl-imx8mm.h
+++ b/include/hw/arm/fsl-imx8mm.h
@@ -15,6 +15,8 @@
#include "hw/misc/imx7_snvs.h"
#include "hw/misc/imx8mm_analog.h"
#include "hw/misc/imx8mm_ccm.h"
+#include "hw/pci-host/designware.h"
+#include "hw/pci-host/fsl_imx8m_phy.h"
#include "hw/sd/sdhci.h"
#include "qom/object.h"
#include "qemu/units.h"
@@ -42,6 +44,8 @@ struct FslImx8mmState {
IMX7SNVSState snvs;
IMXSerialState uart[FSL_IMX8MM_NUM_UARTS];
SDHCIState usdhc[FSL_IMX8MM_NUM_USDHCS];
+DesignwarePCIEHost pcie;
+FslImx8mPciePhyState pcie_phy;
};
enum FslImx8mmMemoryRegions {
@@ -164,6 +168,12 @@ enum FslImx8mmIrqs {
FSL_IMX8MM_UART2_IRQ= 27,
FSL_IMX8MM_UART3_IRQ= 28,
FSL_IMX8MM_UART4_IRQ= 29,
+
+FSL_IMX8MM_PCI_INTA_IRQ = 122,
+FSL_IMX8MM_PCI_INTB_IRQ = 123,
+FSL_IMX8MM_PCI_INTC_IRQ = 124,
+FSL_IMX8MM_PCI_INTD_IRQ = 125,
+FSL_IMX8MM_PCI_MSI_IRQ = 127,
};
#endif /* FSL_IMX8MM_H */
--
2.34.1
