Enabled GPIO controller emulation
Also updated the GPIO IRQ lines of iMX8MM
Signed-off-by: Gaurav Sharma
---
docs/system/arm/imx8mm-evk.rst | 1 +
hw/arm/fsl-imx8mm.c| 54 ++
include/hw/arm/fsl-imx8mm.h| 14 +
3 files changed, 69 insertions(+)
diff --git a/docs/system/arm/imx8mm-evk.rst b/docs/system/arm/imx8mm-evk.rst
index cabaef157e..809ff0bdb8 100644
--- a/docs/system/arm/imx8mm-evk.rst
+++ b/docs/system/arm/imx8mm-evk.rst
@@ -14,6 +14,7 @@ The ``imx8mm-evk`` machine implements the following devices:
* 4 UARTs
* 3 USDHC Storage Controllers
* 1 Designware PCI Express Controller
+ * 5 GPIO Controllers
* Secure Non-Volatile Storage (SNVS) including an RTC
* Clock Tree
diff --git a/hw/arm/fsl-imx8mm.c b/hw/arm/fsl-imx8mm.c
index 09e16786bc..bd7976a27a 100644
--- a/hw/arm/fsl-imx8mm.c
+++ b/hw/arm/fsl-imx8mm.c
@@ -177,6 +177,11 @@ static void fsl_imx8mm_init(Object *obj)
object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);
}
+for (i = 0; i < FSL_IMX8MM_NUM_GPIOS; i++) {
+g_autofree char *name = g_strdup_printf("gpio%d", i + 1);
+object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO);
+}
+
for (i = 0; i < FSL_IMX8MM_NUM_USDHCS; i++) {
g_autofree char *name = g_strdup_printf("usdhc%d", i + 1);
object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC);
@@ -350,6 +355,54 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error
**errp)
qdev_get_gpio_in(gicdev, serial_table[i].irq));
}
+/* GPIOs */
+for (i = 0; i < FSL_IMX8MM_NUM_GPIOS; i++) {
+static const struct {
+hwaddr addr;
+unsigned int irq_low;
+unsigned int irq_high;
+} gpio_table[FSL_IMX8MM_NUM_GPIOS] = {
+{
+fsl_imx8mm_memmap[FSL_IMX8MM_GPIO1].addr,
+FSL_IMX8MM_GPIO1_LOW_IRQ,
+FSL_IMX8MM_GPIO1_HIGH_IRQ
+},
+{
+fsl_imx8mm_memmap[FSL_IMX8MM_GPIO2].addr,
+FSL_IMX8MM_GPIO2_LOW_IRQ,
+FSL_IMX8MM_GPIO2_HIGH_IRQ
+},
+{
+fsl_imx8mm_memmap[FSL_IMX8MM_GPIO3].addr,
+FSL_IMX8MM_GPIO3_LOW_IRQ,
+FSL_IMX8MM_GPIO3_HIGH_IRQ
+},
+{
+fsl_imx8mm_memmap[FSL_IMX8MM_GPIO4].addr,
+FSL_IMX8MM_GPIO4_LOW_IRQ,
+FSL_IMX8MM_GPIO4_HIGH_IRQ
+},
+{
+fsl_imx8mm_memmap[FSL_IMX8MM_GPIO5].addr,
+FSL_IMX8MM_GPIO5_LOW_IRQ,
+FSL_IMX8MM_GPIO5_HIGH_IRQ
+},
+};
+object_property_set_bool(OBJECT(&s->gpio[i]), "has-edge-sel", true,
+ &error_abort);
+object_property_set_bool(OBJECT(&s->gpio[i]), "has-upper-pin-irq",
+ true, &error_abort);
+if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), errp)) {
+return;
+}
+
+sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
+sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
+ qdev_get_gpio_in(gicdev, gpio_table[i].irq_low));
+sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
+ qdev_get_gpio_in(gicdev, gpio_table[i].irq_high));
+}
+
/* USDHCs */
for (i = 0; i < FSL_IMX8MM_NUM_USDHCS; i++) {
static const struct {
@@ -408,6 +461,7 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error
**errp)
case FSL_IMX8MM_CCM:
case FSL_IMX8MM_GIC_DIST:
case FSL_IMX8MM_GIC_REDIST:
+case FSL_IMX8MM_GPIO1 ... FSL_IMX8MM_GPIO5:
case FSL_IMX8MM_PCIE1:
case FSL_IMX8MM_PCIE_PHY1:
case FSL_IMX8MM_RAM:
diff --git a/include/hw/arm/fsl-imx8mm.h b/include/hw/arm/fsl-imx8mm.h
index 74a1a1349d..d3a2d1843f 100644
--- a/include/hw/arm/fsl-imx8mm.h
+++ b/include/hw/arm/fsl-imx8mm.h
@@ -11,6 +11,7 @@
#include "cpu.h"
#include "hw/char/imx_serial.h"
+#include "hw/gpio/imx_gpio.h"
#include "hw/intc/arm_gicv3_common.h"
#include "hw/misc/imx7_snvs.h"
#include "hw/misc/imx8mm_analog.h"
@@ -29,6 +30,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(FslImx8mmState, FSL_IMX8MM)
enum FslImx8mmConfiguration {
FSL_IMX8MM_NUM_CPUS = 4,
+FSL_IMX8MM_NUM_GPIOS= 5,
FSL_IMX8MM_NUM_IRQS = 128,
FSL_IMX8MM_NUM_UARTS= 4,
FSL_IMX8MM_NUM_USDHCS = 3,
@@ -39,6 +41,7 @@ struct FslImx8mmState {
ARMCPU cpu[FSL_IMX8MM_NUM_CPUS];
GICv3State gic;
+IMXGPIOState gpio[FSL_IMX8MM_NUM_GPIOS];
IMX8MMCCMState ccm;
IMX8MMAnalogState analog;
IMX7SNVSState snvs;
@@ -169,6 +172,17 @@ enum FslImx8mmIrqs {
FSL_IMX8MM_UART3_IRQ= 28,
FSL_IMX8MM_UART4_IRQ= 29,
+FSL_IMX8MM_GPIO1_LOW_IRQ = 64,
+
