RE: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1
Hi Cedric, > From: Cédric Le Goater > Sent: Thursday, February 6, 2025 3:23 PM > To: Jamin Lin ; Andrew Jeffery > ; Peter Maydell ; > Steven Lee ; Troy Lee ; > Joel Stanley ; open list:ASPEED BMCs > ; open list:All patches CC here > > Cc: Troy Lee ; Yunlin Tang > > Subject: Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of > INTC controllers for AST2700 A1 > > > The design of the OR gates for GICINT 196 is as follows: > > It has interrupt sources ranging from 0 to 31, with its output pin > > connected to INTC_IO "T0 GICINT_196". > > The output pin is then connected to INTC_CPU "GIC_192_201" at bit 4, > > and its bit 4 output should be connected to GIC 196. > > The design of INTC_CPU GIC_192_201 have 10 output pins, mapped as > following: > > Bit 0 -> GIC 192 > > Bit 1 -> GIC 193 > > Bit 2 -> GIC 194 > > Bit 3 -> GIC 195 > > Bit 4 -> GIC 196 > > > > Jamin > > > |- > --| > > | > AST2700 A1 Design | > > | To GICINT196 > | > > | > | > > | ETH1|---| > |--||--| | > > | >|0 || > INTC_IO || orgates[0] | | > > | ETH2| 4| > orgates[0]-->|inpin[0]>outpin[0]|--->| 0| | > > | >|1 5| > orgates[1]-->|inpin[1]>outpin[1]|--->| 1| | > > | ETH3| 6| > orgates[2]-->|inpin[2]>outpin[2]|--->| 2| | > > | >|219| > orgates[3]-->|inpin[3]>outpin[3]|--->| 3 OR[0:9] |-| | > > | UART0 | > 20|-->orgates[4]-->|inpin[4]>outpin[4]|--->| 4| > | | > > | >|721| > orgates[5]-->|inpin[5]>outpin[5]|--->| 5| | | > > | UART1 | 22| > orgates[6]-->|inpin[6]>outpin[6]|--->| 6| | | > > | >|823| > orgates[7]-->|inpin[7]>outpin[7]|--->| 7| | | > > | UART2 | 24| > orgates[8]-->|inpin[8]>outpin[8]|--->| 8| | | > > | >|925| > orgates[9]-->|inpin[9]>outpin[9]|--->| 9| | | > > | UART3 | 26| > |--||--| | | > > | -|10 27| > | | > > | UART5 | 28| > | | > > | >|11 29| > | | > > | UART6 | | > | | > > | >|12 30| > |---| | > > | UART7 | 31| | > | > > | >|13 | | > | > > | UART8 | OR[0:31] | | > |--| |--| | > > | >|14 | || > INTC | | GIC | | > > | UART9 | | | > |inpin[0:0]->outpin[0] |-->|192 | | > > | >|15 | | > |inpin[0:1]->outpin[1] |-->|193 | | > > | UART10 | | | > |inpin[0:2]->outpin[2] |-->|194 | | > > | >|16 | | > |inpin[0:3]->outpin[3] |-->|195 | | > > | UART11 | | |--> > |inpin[0:4]->outpin[4] |-->|196 | | > > | >|17 | > |inpin[0:5]->outpin[5] |-->|197 | | > > | UART12 | | > |inpin[0:6]->outpin[6] |-->|198 | | > > | >|18 | > |inpin[0:7]->outpin[7] |-->|199 | | > > | |---| > |inpin[0:8]->outpin[8] |-->|200 | | > > | > |inpin[0:9]->outpin[9] |-->|201 | | > > > |- > --| > > > |--
RE: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1
Hi Cedric, > From: Cédric Le Goater > Sent: Thursday, February 6, 2025 3:17 PM > To: Jamin Lin ; Joel Stanley > Cc: Andrew Jeffery ; Peter Maydell > ; Steven Lee ; Troy > Lee ; open list:ASPEED BMCs ; > open list:All patches CC here ; Troy Lee > ; Yunlin Tang > Subject: Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of > INTC controllers for AST2700 A1 > > On 2/6/25 06:15, Jamin Lin wrote: > > Hi Joel, > > > >> From: Joel Stanley > >> Sent: Thursday, February 6, 2025 12:55 PM > >> To: Jamin Lin > >> Cc: Andrew Jeffery ; Cédric Le Goater > >> ; Peter Maydell ; Steven Lee > >> ; Troy Lee ; open > >> list:ASPEED BMCs ; open list:All patches CC here > >> ; Troy Lee ; Yunlin > >> Tang > >> Subject: Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two > >> levels of INTC controllers for AST2700 A1 > >> > >> Hi Jamin, > >> > >> On Thu, 6 Feb 2025 at 10:09, Andrew Jeffery > >> > >> wrote: > >>> Thanks, I'll consider this updated diagram as well while I put my > >>> own together from the other pieces of info you've provided. > >> > >> When you send the next version, please try to separate your code > >> cleanups and minor renames into a different patch. It makes it easier > >> to see what you're adding. > >> > >> Thanks, > >> > >> Joel > > > > Thanks for suggestion. Cedric, also made the same suggestion in patch > > 0, > > https://patchwork.kernel.org/project/qemu-devel/cover/20250121070424.2 > > [email protected]/ > > > > I think I will re-send this first. > > > > > 1. INTC rename/prereqs/cleanups > > hw/intc/aspeed: Rename INTC to INTC0 > > I thought we were keeping INTC and introducing INTC_IO ? As you wish. > Yes, I am working keeping INTC (CPU Die) and introducing INTC_IO(IO Die). I understand that INTC0 and INTC1 are very difficult to interpret or distinguish their meanings. Thanks-Jamin > If we choose to rename INTC to INTC0, I prefer that you send the series below > first. > > > > hw/intc/aspeed: Support different memory region ops > > hw/intc/aspeed: Introduce a new aspeed_2700_intc0_ops for INTC0 > > hw/intc/aspeed: Support setting different memory and register size > > hw/intc/aspeed: Introduce helper functions for enable and status > registers > > hw/intc/aspeed: Add ID to trace events for better debugging > > hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0 > > Thanks, > > C.
Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1
The design of the OR gates for GICINT 196 is as follows: It has interrupt sources ranging from 0 to 31, with its output pin connected to INTC_IO "T0 GICINT_196". The output pin is then connected to INTC_CPU "GIC_192_201" at bit 4, and its bit 4 output should be connected to GIC 196. The design of INTC_CPU GIC_192_201 have 10 output pins, mapped as following: Bit 0 -> GIC 192 Bit 1 -> GIC 193 Bit 2 -> GIC 194 Bit 3 -> GIC 195 Bit 4 -> GIC 196 Jamin |---| | AST2700 A1 Design | | To GICINT196 | | | | ETH1|---||--| |--| | | >|0 || INTC_IO | | orgates[0] | | | ETH2| 4| orgates[0]-->|inpin[0]>outpin[0]|--->| 0| | | >|1 5| orgates[1]-->|inpin[1]>outpin[1]|--->| 1| | | ETH3| 6| orgates[2]-->|inpin[2]>outpin[2]|--->| 2| | | >|219| orgates[3]-->|inpin[3]>outpin[3]|--->| 3 OR[0:9] |-| | | UART0 | 20|-->orgates[4]-->|inpin[4]>outpin[4]|--->| 4| | | | >|721| orgates[5]-->|inpin[5]>outpin[5]|--->| 5| | | | UART1 | 22| orgates[6]-->|inpin[6]>outpin[6]|--->| 6| | | | >|823| orgates[7]-->|inpin[7]>outpin[7]|--->| 7| | | | UART2 | 24| orgates[8]-->|inpin[8]>outpin[8]|--->| 8| | | | >|925| orgates[9]-->|inpin[9]>outpin[9]|--->| 9| | | | UART3 | 26||--| |--| | | | -|10 27| | | | UART5 | 28| | | | >|11 29| | | | UART6 | | | | | >|12 30| |---| | | UART7 | 31| | | | >|13 | | | | UART8 | OR[0:31] | | |--| |--| | | >|14 | ||INTC | | GIC | | | UART9 | | ||inpin[0:0]->outpin[0] |-->|192 | | | >|15 | ||inpin[0:1]->outpin[1] |-->|193 | | | UART10 | | ||inpin[0:2]->outpin[2] |-->|194 | | | >|16 | ||inpin[0:3]->outpin[3] |-->|195 | | | UART11 | | |--> |inpin[0:4]->outpin[4] |-->|196 | | | >|17 | |inpin[0:5]->outpin[5] |-->|197 | | | UART12 | | |inpin[0:6]->outpin[6] |-->|198 | | | >|18 | |inpin[0:7]->outpin[7] |-->|199 | | | |---| |inpin[0:8]->outpin[8] |-->|200 | | | |inpin[0:9]->outpin[9] |-->|201 | | |---| |---| | ETH1|---| orgates[1]--->|inpin[1]|-->outpin[10]|-->|128 | | | >|0 | orgates[2]--->|inpin[2]|-->outpin[11]|-->|129 | | | ETH2| 4| orgates[3]--->|inpin[3]|-
Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1
On 2/6/25 06:15, Jamin Lin wrote: Hi Joel, From: Joel Stanley Sent: Thursday, February 6, 2025 12:55 PM To: Jamin Lin Cc: Andrew Jeffery ; Cédric Le Goater ; Peter Maydell ; Steven Lee ; Troy Lee ; open list:ASPEED BMCs ; open list:All patches CC here ; Troy Lee ; Yunlin Tang Subject: Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1 Hi Jamin, On Thu, 6 Feb 2025 at 10:09, Andrew Jeffery wrote: Thanks, I'll consider this updated diagram as well while I put my own together from the other pieces of info you've provided. When you send the next version, please try to separate your code cleanups and minor renames into a different patch. It makes it easier to see what you're adding. Thanks, Joel Thanks for suggestion. Cedric, also made the same suggestion in patch 0, https://patchwork.kernel.org/project/qemu-devel/cover/[email protected]/ I think I will re-send this first. 1. INTC rename/prereqs/cleanups hw/intc/aspeed: Rename INTC to INTC0 I thought we were keeping INTC and introducing INTC_IO ? As you wish. If we choose to rename INTC to INTC0, I prefer that you send the series below first. hw/intc/aspeed: Support different memory region ops hw/intc/aspeed: Introduce a new aspeed_2700_intc0_ops for INTC0 hw/intc/aspeed: Support setting different memory and register size hw/intc/aspeed: Introduce helper functions for enable and status registers hw/intc/aspeed: Add ID to trace events for better debugging hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0 Thanks, C.
RE: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1
Hi Joel, > From: Joel Stanley > Sent: Thursday, February 6, 2025 12:55 PM > To: Jamin Lin > Cc: Andrew Jeffery ; Cédric Le Goater > ; Peter Maydell ; Steven Lee > ; Troy Lee ; open > list:ASPEED BMCs ; open list:All patches CC here > ; Troy Lee ; Yunlin > Tang > Subject: Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of > INTC controllers for AST2700 A1 > > Hi Jamin, > > On Thu, 6 Feb 2025 at 10:09, Andrew Jeffery > wrote: > > Thanks, I'll consider this updated diagram as well while I put my own > > together from the other pieces of info you've provided. > > When you send the next version, please try to separate your code cleanups and > minor renames into a different patch. It makes it easier to see what you're > adding. > > Thanks, > > Joel Thanks for suggestion. Cedric, also made the same suggestion in patch 0, https://patchwork.kernel.org/project/qemu-devel/cover/[email protected]/ I think I will re-send this first. 1. INTC rename/prereqs/cleanups hw/intc/aspeed: Rename INTC to INTC0 hw/intc/aspeed: Support different memory region ops hw/intc/aspeed: Introduce a new aspeed_2700_intc0_ops for INTC0 hw/intc/aspeed: Support setting different memory and register size hw/intc/aspeed: Introduce helper functions for enable and status registers hw/intc/aspeed: Add ID to trace events for better debugging hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0 Jamin
Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1
Hi Jamin, On Thu, 6 Feb 2025 at 10:09, Andrew Jeffery wrote: > Thanks, I'll consider this updated diagram as well while I put my own > together from the other pieces of info you've provided. When you send the next version, please try to separate your code cleanups and minor renames into a different patch. It makes it easier to see what you're adding. Thanks, Joel
Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1
Hi Jamin, > > > > > > The design of the OR gates for GICINT 196 is as follows: > > > > 196? You discuss 192 below. > > > Sorry typo. I update my comments. > > The design of the OR gates for GICINT 196 is as follows: > It has interrupt sources ranging from 0 to 31, with its output pin connected > to > INTC_IO "T0 GICINT_196". > The output pin is then connected to INTC_CPU "GIC_192_201" at bit 4, and > its bit 4 output should be connected to GIC 196. > The design of INTC_CPU GIC_192_201 have 10 output pins, mapped as following: > Bit 0 -> GIC 192 > Bit 1 -> GIC 193 > Bit 2 -> GIC 194 > Bit 3 -> GIC 195 > Bit 4 -> GIC 196 > > Jamin > > |---| > | AST2700 A1 Design > | > | To GICINT196 > | > | > | > | ETH1 |---| |--| > |--| | > | >|0 | | INTC_IO | > | orgates[0] | | > | ETH2 | 4| > orgates[0]-->|inpin[0]>outpin[0]|--->| 0 | | > | >|1 5| > orgates[1]-->|inpin[1]>outpin[1]|--->| 1 | | > | ETH3 | 6| > orgates[2]-->|inpin[2]>outpin[2]|--->| 2 | | > | >|2 19| > orgates[3]-->|inpin[3]>outpin[3]|--->| 3 OR[0:9] |-| | > | UART0 | > 20|-->orgates[4]-->|inpin[4]>outpin[4]|--->| 4 | > | | > | >|7 21| > orgates[5]-->|inpin[5]>outpin[5]|--->| 5 | | | > | UART1 | 22| > orgates[6]-->|inpin[6]>outpin[6]|--->| 6 | | | > | >|8 23| > orgates[7]-->|inpin[7]>outpin[7]|--->| 7 | | | > | UART2 | 24| > orgates[8]-->|inpin[8]>outpin[8]|--->| 8 | | | > | >|9 25| > orgates[9]-->|inpin[9]>outpin[9]|--->| 9 | | | > | UART3 | 26| |--| > |--| | | > | -|10 27| > | | > | UART5 | 28| > | | > | >|11 29| > | | > | UART6 | | > | | > | >|12 30| > |---| | > | UART7 | 31| | > | > | >|13 | | > | > | UART8 | OR[0:31] | | > |--| |--| | > | >|14 | | | INTC > | | GIC | | > | UART9 | | | > |inpin[0:0]->outpin[0] |-->|192 | | > | >|15 | | > |inpin[0:1]->outpin[1] |-->|193 | | > | UART10 | | | > |inpin[0:2]->outpin[2] |-->|194 | | > | >|16 | | > |inpin[0:3]->outpin[3] |-->|195 | | > | UART11 | | |--> > |inpin[0:4]->outpin[4] |-->|196 | | > | >|17 | > |inpin[0:5]->outpin[5] |-->|197 | | > | UART12 | | > |inpin[0:6]->outpin[6] |-->|198 | | > | >|18 | > |inpin[0:7]->outpin[7] |-->|199 | | > | |---| > |inpin[0:8]->outpin[8] |-->|200 | | > | > |inpin[0:9]->outpin[9] |-->|201 | | > > |---| > > |---
RE: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1
Hi Andrew, > From: Andrew Jeffery > Sent: Wednesday, February 5, 2025 11:51 AM > To: Jamin Lin ; Cédric Le Goater ; > Peter Maydell ; Steven Lee > ; Troy Lee ; Joel Stanley > ; open list:ASPEED BMCs ; open > list:All patches CC here > Cc: Troy Lee ; Yunlin Tang > > Subject: Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of > INTC controllers for AST2700 A1 > > On Tue, 2025-02-04 at 09:43 +, Jamin Lin wrote: > > Hi Andrew, > > > > > -Original Message- > > > From: Andrew Jeffery > > > Sent: Thursday, January 30, 2025 12:20 PM > > > To: Jamin Lin ; Cédric Le Goater > > > ; Peter Maydell ; Steven Lee > > > ; Troy Lee ; Joel > > > Stanley ; open list:ASPEED BMCs > > > ; open list:All patches CC here > > > > > > Cc: Troy Lee ; Yunlin Tang > > > > > > Subject: Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two > > > levels of INTC controllers for AST2700 A1 > > > > > > On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote: > > > > The design of INTC controllers has significantly changed in AST2700 A1. > > > > > > > > There are a total of 480 interrupt sources in AST2700 A1. For > > > > interrupt numbers from 0 to 127, they can route directly to PSP, > > > > SSP, and TSP. Due to the limitation of interrupt numbers of > > > > processors, the interrupts are merged every > > > > 32 sources for interrupt numbers greater than 127. > > > > > > > > There are two levels of interrupt controllers, INTC0 and INTC1. > > > > The interrupt sources of INTC0 are the interrupt numbers from > > > > INTC_0 to > > > > INTC_127 and interrupts from INTC1. The interrupt sources of INTC1 > > > > are the interrupt numbers greater than INTC_127. INTC1 controls > > > > the interrupts > > > INTC_128 to INTC_319 only. > > > > > > > > Currently, only GIC 192 to 201 are supported, and their source > > > > interrupts are from INTC1 and connected to INTC0 at input pin 0 > > > > and output pins 0 to 9 for GIC 192-201. > > > > > > > > To support both AST2700 A1 and A0, INTC0 input pins 1 to 9 and > > > > output pins > > > > 10 to 18 remain to support GIC 128-136, which source interrupts from > INTC0. > > > > These will be removed if we decide not to support AST2700 A0 in the > future. > > > > > > > > +---+ > > > > > AST2700 A1 > > > Design > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > +--+ > > > > > > > > > > > > > > > > > | INTC1 | > > > > > > > > +---+ | > > > > > > > > | | > > > | > > > > > orgates[0] | | > > > > > orgates[0]+> |inpin[0]+--->outpin[0]+--> | > > > 0 > > > > > > | > > > > > orgates[1]|> |inpin[1]|--->outpin[1]|--> | 1 > > > > > 0-31 bits +--+ | > > > > > orgates[2]|> |inpin[2]|--->outpin[2]|--> | > > > 2 > > > > > > | | > > > > > orgates[3]|> |inpin[3]|--->outpin[3]|--> | > > > 3 > > > > > > | | > > > > > orgates[4]|> |inpin[4]|--->outpin[4]|--> | > > > 4 > > > > > > | | > > > > > orgates[5]+> |inpin[5]+--->outpin[5]+--> | > > > 5 > > > > > > | | > > > > > > > > | | > > > > > > > > > ---| | | > > > > > > > > +--+ > > > > > > > > > | > > > > > > > > > > +--- > > > > > + > > > > > | | > > > > > > > > | > > > > > > > >
Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1
On Tue, 2025-02-04 at 09:43 +, Jamin Lin wrote: > Hi Andrew, > > > -Original Message- > > From: Andrew Jeffery > > Sent: Thursday, January 30, 2025 12:20 PM > > To: Jamin Lin ; Cédric Le Goater ; > > Peter Maydell ; Steven Lee > > ; Troy Lee ; Joel Stanley > > ; open list:ASPEED BMCs ; open > > list:All patches CC here > > Cc: Troy Lee ; Yunlin Tang > > > > Subject: Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of > > INTC controllers for AST2700 A1 > > > > On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote: > > > The design of INTC controllers has significantly changed in AST2700 A1. > > > > > > There are a total of 480 interrupt sources in AST2700 A1. For > > > interrupt numbers from 0 to 127, they can route directly to PSP, SSP, > > > and TSP. Due to the limitation of interrupt numbers of processors, the > > > interrupts are merged every > > > 32 sources for interrupt numbers greater than 127. > > > > > > There are two levels of interrupt controllers, INTC0 and INTC1. The > > > interrupt sources of INTC0 are the interrupt numbers from INTC_0 to > > > INTC_127 and interrupts from INTC1. The interrupt sources of INTC1 are > > > the interrupt numbers greater than INTC_127. INTC1 controls the interrupts > > INTC_128 to INTC_319 only. > > > > > > Currently, only GIC 192 to 201 are supported, and their source > > > interrupts are from INTC1 and connected to INTC0 at input pin 0 and > > > output pins 0 to 9 for GIC 192-201. > > > > > > To support both AST2700 A1 and A0, INTC0 input pins 1 to 9 and output > > > pins > > > 10 to 18 remain to support GIC 128-136, which source interrupts from > > > INTC0. > > > These will be removed if we decide not to support AST2700 A0 in the > > > future. > > > > > > +---+ > > > > AST2700 A1 > > Design > > > > > > > > > > > > > > > > > > > > > > > > +--+ > > > > > > > > > > > > > | INTC1 | > > > > > > +---+ | > > > > > > | | > > | > > > > orgates[0] | | > > > > orgates[0]+> |inpin[0]+--->outpin[0]+--> | > > 0 > > > > > | > > > > orgates[1]|> |inpin[1]|--->outpin[1]|--> | 1 0-31 > > > > bits +--+ | > > > > orgates[2]|> |inpin[2]|--->outpin[2]|--> | > > 2 > > > > > | | > > > > orgates[3]|> |inpin[3]|--->outpin[3]|--> | > > 3 > > > > > | | > > > > orgates[4]|> |inpin[4]|--->outpin[4]|--> | > > 4 > > > > > | | > > > > orgates[5]+> |inpin[5]+--->outpin[5]+--> | > > 5 > > > > > | | > > > > > > | | > > > > > > > ---| | | > > > > > > +--+ > > > > > > > | > > > > > > > > +--- > > > > | | > > > > > > | > > > > > > > > > > > > > | > > > > > > > > > > > | +--+ > > > > +-+ | > > > > > > | | INTC0 | > > | > > > > GIC | | > > > > | |inpin[0:0]->outpin[0] +-> > > > 192 > > > > > | > > > > | |inpin[0:1]|>outpin[1] |-> > > > 193 > > > > > | > > > > | |inpin[0:2]|>outpin[2] |-> > > > 194 > > > > > | > > > > | |inpin[0:3]|>outpin[3] |-> > > > 195 > > > > > | > > >
RE: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1
Hi Andrew, > -Original Message- > From: Andrew Jeffery > Sent: Thursday, January 30, 2025 12:20 PM > To: Jamin Lin ; Cédric Le Goater ; > Peter Maydell ; Steven Lee > ; Troy Lee ; Joel Stanley > ; open list:ASPEED BMCs ; open > list:All patches CC here > Cc: Troy Lee ; Yunlin Tang > > Subject: Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of > INTC controllers for AST2700 A1 > > On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote: > > The design of INTC controllers has significantly changed in AST2700 A1. > > > > There are a total of 480 interrupt sources in AST2700 A1. For > > interrupt numbers from 0 to 127, they can route directly to PSP, SSP, > > and TSP. Due to the limitation of interrupt numbers of processors, the > > interrupts are merged every > > 32 sources for interrupt numbers greater than 127. > > > > There are two levels of interrupt controllers, INTC0 and INTC1. The > > interrupt sources of INTC0 are the interrupt numbers from INTC_0 to > > INTC_127 and interrupts from INTC1. The interrupt sources of INTC1 are > > the interrupt numbers greater than INTC_127. INTC1 controls the interrupts > INTC_128 to INTC_319 only. > > > > Currently, only GIC 192 to 201 are supported, and their source > > interrupts are from INTC1 and connected to INTC0 at input pin 0 and > > output pins 0 to 9 for GIC 192-201. > > > > To support both AST2700 A1 and A0, INTC0 input pins 1 to 9 and output > > pins > > 10 to 18 remain to support GIC 128-136, which source interrupts from INTC0. > > These will be removed if we decide not to support AST2700 A0 in the future. > > > > +---+ > > > AST2700 A1 > Design > > > | > > > > > > > > | > > > > +--+ > > > > | > > > > | INTC1 | > > > > +---+ | > > > > | | > | > > > orgates[0] | | > > > orgates[0]+> |inpin[0]+--->outpin[0]+--> | > 0 > > > | | > > > orgates[1]|> |inpin[1]|--->outpin[1]|--> | 1 0-31 > > > bits +--+ | > > > orgates[2]|> |inpin[2]|--->outpin[2]|--> | > 2 > > > | | | > > > orgates[3]|> |inpin[3]|--->outpin[3]|--> | > 3 > > > | | | > > > orgates[4]|> |inpin[4]|--->outpin[4]|--> | > 4 > > > | | | > > > orgates[5]+> |inpin[5]+--->outpin[5]+--> | > 5 > > > | | | > > > > | | > > > > |---| | | > > > > +--+ > > > > | | > > > > > > +--- > > > | | > > > > | > > > > | > > > > | > > > > | > > > | +--+ > > > +-+ | > > > > | | INTC0 | > | > > > GIC | | > > > | |inpin[0:0]->outpin[0] +-> > |192 > > > | | > > > | |inpin[0:1]|>outpin[1] |-> > |193 > > > | | > > > | |inpin[0:2]|>outpin[2] |-> > |194 > > > | | > > > | |inpin[0:3]|>outpin[3] |-> > |195 > > > | | > > > >--> |inpin[0:4]|>outpin[4] |-> > |196 > > > | | > > > |inpin[0:5]|>outpin[5] |-> > |197 > > > | | > > > |inpin[0:6]|>outpin[6] |-> > |198 > > > | | > > > |inpin[0:7]|>outpin[7] |-> > |199 > > > | | > > > |inpin[0:8]|>outpin[8] |-> > |200 > > > | | > > > |inpin[0:9]|>outpin[9] |-> > |201 > > > | | > > +--
Re: [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1
On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote: > The design of INTC controllers has significantly changed in AST2700 A1. > > There are a total of 480 interrupt sources in AST2700 A1. For interrupt > numbers > from 0 to 127, they can route directly to PSP, SSP, and TSP. Due to the > limitation of interrupt numbers of processors, the interrupts are merged every > 32 sources for interrupt numbers greater than 127. > > There are two levels of interrupt controllers, INTC0 and INTC1. The interrupt > sources of INTC0 are the interrupt numbers from INTC_0 to INTC_127 and > interrupts from INTC1. The interrupt sources of INTC1 are the interrupt > numbers > greater than INTC_127. INTC1 controls the interrupts INTC_128 to INTC_319 > only. > > Currently, only GIC 192 to 201 are supported, and their source interrupts are > from INTC1 and connected to INTC0 at input pin 0 and output pins 0 to 9 for > GIC 192-201. > > To support both AST2700 A1 and A0, INTC0 input pins 1 to 9 and output pins > 10 to 18 remain to support GIC 128-136, which source interrupts from INTC0. > These will be removed if we decide not to support AST2700 A0 in the future. > > +---+ > > AST2700 A1 Design > > | > > > > | > > +--+ > > | > > | INTC1 | +---+ > > | > > | | | orgates[0] | > > | > > orgates[0]+> |inpin[0]+--->outpin[0]+--> | 0 | > > | > > orgates[1]|> |inpin[1]|--->outpin[1]|--> | 1 0-31 bits > > +--+ | > > orgates[2]|> |inpin[2]|--->outpin[2]|--> | 2 | > > | | > > orgates[3]|> |inpin[3]|--->outpin[3]|--> | 3 | > > | | > > orgates[4]|> |inpin[4]|--->outpin[4]|--> | 4 | > > | | > > orgates[5]+> |inpin[5]+--->outpin[5]+--> | 5 | > > | | > > | | |---| > > | | > > +--+ > > | | > > > > +---| > > | > > | > > | > > | > > | > > | +--+ > > +-+ | > > | | INTC0 | | GIC > > | | > > | |inpin[0:0]->outpin[0] +-> |192 > > | | > > | |inpin[0:1]|>outpin[1] |-> |193 > > | | > > | |inpin[0:2]|>outpin[2] |-> |194 > > | | > > | |inpin[0:3]|>outpin[3] |-> |195 > > | | > > >--> |inpin[0:4]|>outpin[4] |-> |196 > > | | > > |inpin[0:5]|>outpin[5] |-> |197 > > | | > > |inpin[0:6]|>outpin[6] |-> |198 > > | | > > |inpin[0:7]|>outpin[7] |-> |199 > > | | > > |inpin[0:8]|>outpin[8] |-> |200 > > | | > > |inpin[0:9]|>outpin[9] |-> |201 > > | | > +---+ > +---+ > > orgates[1]|-> |inpin[1]|-->outpin[10]|-> |128 > > | | > > orgates[2]|-> |inpin[2]|-->outpin[11]|-> |129 > > | | > > orgates[3]|-> |inpin[3]|-->outpin[12]|-> |130 > > | | > > orgates[4]|-> |inpin[4]|-->outpin[13]|-> |131 > > | | > > orgates[5]|-> |inpin[5]|-->outpin[14]|-> |132 > > | | > > orgates[6]|-> |inpin[6]|-->outpin[15]|-> |133 > > | | > > orgates[7]|-> |inpin[7]|-->outpin[16]|-> |134 > > | | > > orgates[8]|-> |inpin[8]|-->outpin[17]|-> |135 > > | | > > orgates[9]+-> |inpin[9]|-->outpin[18]+---
