Re: Re: [PATCH qemu v7 1/1] target/riscv: Add Zilsd and Zclsd extension support
On Wed, Jun 11, 2025 at 5:10 PM 刘旭 wrote: > > Thanks for your reply. > > However, regarding the issue of register restrictions, since I continued to > use the format in the basic C extension in insn16.deocode, I think the > register range has thus been compatible with `!function=ex_rvc_register`. You are right! In future please reply inline and in plain text though. This is good to go then, do you mind rebasing it on https://github.com/alistair23/qemu/tree/riscv-to-apply.next and sending a v8 Alistair > > Alistair Francis 在 2025年6月11日 周三 12:47 写道： > On Thu, May 15, 2025 at 2:07 PM ~liuxu wrote: > > > > From: lxx <[email protected]> > > > > This patch adds support for the Zilsd and Zclsd extension, > > which is documented at > > https://github.com/riscv/riscv-zilsd/releases/tag/v1.0 > > > > Co-developed-by: SUN Dongya > > Co-developed-by: LIU Xu > > Co-developed-by: ZHAO Fujin > > --- > > target/riscv/cpu.c| 4 + > > target/riscv/cpu_cfg.h| 2 + > > target/riscv/insn16.decode| 8 ++ > > target/riscv/insn32.decode| 12 ++- > > target/riscv/insn_trans/trans_zilsd.c.inc | 112 ++ > > target/riscv/tcg/tcg-cpu.c| 20 > > target/riscv/translate.c | 1 + > > 7 files changed, 157 insertions(+), 2 deletions(-) > > create mode 100644 target/riscv/insn_trans/trans_zilsd.c.inc > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index 09ded6829a..54072e284d 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -115,6 +115,7 @@ const RISCVIsaExtData isa_edata_arr[] = { > > ISA_EXT_DATA_ENTRY(zihintntl, PRIV_VERSION_1_10_0, ext_zihintntl), > > ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), > > ISA_EXT_DATA_ENTRY(zihpm, PRIV_VERSION_1_12_0, ext_zihpm), > > +ISA_EXT_DATA_ENTRY(zilsd, PRIV_VERSION_1_12_0, ext_zilsd), > > ISA_EXT_DATA_ENTRY(zimop, PRIV_VERSION_1_13_0, ext_zimop), > > ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul), > > ISA_EXT_DATA_ENTRY(za64rs, PRIV_VERSION_1_12_0, has_priv_1_12), > > @@ -138,6 +139,7 @@ const RISCVIsaExtData isa_edata_arr[] = { > > ISA_EXT_DATA_ENTRY(zcmop, PRIV_VERSION_1_13_0, ext_zcmop), > > ISA_EXT_DATA_ENTRY(zcmp, PRIV_VERSION_1_12_0, ext_zcmp), > > ISA_EXT_DATA_ENTRY(zcmt, PRIV_VERSION_1_12_0, ext_zcmt), > > +ISA_EXT_DATA_ENTRY(zclsd, PRIV_VERSION_1_12_0, ext_zclsd), > > ISA_EXT_DATA_ENTRY(zba, PRIV_VERSION_1_12_0, ext_zba), > > ISA_EXT_DATA_ENTRY(zbb, PRIV_VERSION_1_12_0, ext_zbb), > > ISA_EXT_DATA_ENTRY(zbc, PRIV_VERSION_1_12_0, ext_zbc), > > @@ -1653,6 +1655,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = > > { > > > > MULTI_EXT_CFG_BOOL("zicntr", ext_zicntr, true), > > MULTI_EXT_CFG_BOOL("zihpm", ext_zihpm, true), > > +MULTI_EXT_CFG_BOOL("zilsd", ext_zilsd, false), > > > > MULTI_EXT_CFG_BOOL("zba", ext_zba, true), > > MULTI_EXT_CFG_BOOL("zbb", ext_zbb, true), > > @@ -1692,6 +1695,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = > > { > > MULTI_EXT_CFG_BOOL("zcmp", ext_zcmp, false), > > MULTI_EXT_CFG_BOOL("zcmt", ext_zcmt, false), > > MULTI_EXT_CFG_BOOL("zicond", ext_zicond, false), > > +MULTI_EXT_CFG_BOOL("zclsd", ext_zclsd, false), > > > > /* Vector cryptography extensions */ > > MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false), > > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > > index 8a843482cc..1ca11f99f1 100644 > > --- a/target/riscv/cpu_cfg.h > > +++ b/target/riscv/cpu_cfg.h > > @@ -51,6 +51,7 @@ struct RISCVCPUConfig { > > bool ext_zcf; > > bool ext_zcmp; > > bool ext_zcmt; > > +bool ext_zclsd; > > bool ext_zk; > > bool ext_zkn; > > bool ext_zknd; > > @@ -73,6 +74,7 @@ struct RISCVCPUConfig { > > bool ext_zihintntl; > > bool ext_zihintpause; > > bool ext_zihpm; > > +bool ext_zilsd; > > bool ext_zimop; > > bool ext_zcmop; > > bool ext_ztso; > > diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode > > index bf893d1c2e..c34020e4dc 100644 > > --- a/target/riscv/insn16.decode > > +++ b/target/riscv/insn16.decode > > @@ -130,10 +130,14 @@ sw110 ... ... .. ... 00 @cs_w > > { > >ld 011 ... ... .. ... 00 @cl_d > >c_flw 011 ... ... .. ... 00 @cl_w > > + # *** Zclsd Extension *** > > + zclsd_ld011 ... ... .. ... 00 @cl_d > > } > > { > >sd 111 ... ... .. ... 00 @cs_d > >c_fsw 111 ... ... .. ... 00 @cs_w > > + # *** Zclsd Extension *** > > + zclsd_sd111 ... ... .. ... 00 @cs_d > > } > > > > # *** RV32/64C Standard Extension (Quadrant 1) *** > > @@ -212,10 +216,14 @@ sw110 . . . 10 @c_swsp > >c64_illegal 011 - 0 - 10 # c.ldsp, RES rd=0 > >ld 011 . . . 10
回复：Re: [PATCH qemu v7 1/1] target/riscv: Add Zilsd and Zclsd extension support
Thanks for your reply.
However, regarding the issue of register restrictions, since I continued to use
the format in the basic C extension in insn16.deocode, I think the
register range has thus been compatible with `!function=ex_rvc_register`.
Alistair Francishttps://github.com/riscv/riscv-zilsd/releases/tag/v1.0
>
> Co-developed-by: SUN Dongya http://www.gnu.org/licenses/>;.
> + */
> +
> +#define REQUIRE_ZILSD(ctx) do { \
> + if (!ctx->cfg_ptr->ext_zilsd) \
> + return
false;
\
> +} while (0)
> +
> +#define REQUIRE_ZCLSD(ctx) do { \
> + if (!ctx->cfg_ptr->ext_zclsd) \
> + return
false;
\
> +} while (0)
> +
> +static bool gen_load_i64(DisasContext *ctx, arg_ld *a)
> +{
> + if ((a->rd) % 2) {
> + return false;
> + }
> +
> + TCGv dest_low = dest_gpr(ctx, a->rd);
> + TCGv dest_high = dest_gpr(ctx, a->rd + 1);
> + TCGv addr = get_address(ctx, a->rs1, a->imm);
> + TCGv_i64 tmp = tcg_temp_new_i64();
> +
> + tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx,
MO_TESQ);
> +
> + if (a->rd == 0) {
> + return true;
> + }
> +
> + tcg_gen_extr_i64_tl(dest_low, dest_high, tmp);
> +
> + gen_set_gpr(ctx, a->rd, dest_low);
> + gen_set_gpr(ctx, a->rd + 1, dest_high);
> +
> + return true;
> +}
> +
> +static bool trans_zilsd_ld(DisasContext *ctx, arg_zilsd_ld *a)
> +{
> + REQUIRE_32BIT(ctx);
> + REQUIRE_ZILSD(ctx);
> + return gen_load_i64(ctx, a);
> +}
> +
> +static bool trans_zclsd_ld(DisasContext *ctx, arg_zclsd_ld *a)
> +{
> + REQUIRE_32BIT(ctx);
> + REQUIRE_ZCLSD(ctx);
Shouldn't there be a check that only x8-15 is used?
> + return gen_load_i64(ctx, a);
> +}
> +
> +static bool trans_zclsd_ldsp(DisasContext *ctx, arg_zclsd_ldsp *a)
> +{
> + REQUIRE_32BIT(ctx);
> + REQUIRE_ZCLSD(ctx);
> +
> + if (a->rd == 0) {
> + return false;
> + }
> + return gen_load_i64(ctx, a);
> +}
> +
> +static bool gen_store_i64(DisasContext *ctx, arg_sd *a)
> +{
> + if ((a->rs2) % 2) {
> + return false;
> + }
> +
> + TCGv data_low = get_gpr(ctx, a->rs2, EXT_NONE);
> + TCGv data_high = get_gpr(ctx, a->rs2 + 1, EXT_NONE);
> + TCGv addr = get_address(ctx, a->rs1, a->imm);
> + TCGv_i64 tmp = tcg_temp_new_i64();
> +
> + if (a->rs2 == 0) {
> + tmp = tcg_constant_i64(0);
> + } else {
> + tcg_gen_concat_tl_i64(tmp,
data_low, data_high);
> + }
> + tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx,
MO_TESQ);
> +
> + return true;
> +}
> +
> +static bool trans_zilsd_sd(DisasContext *ctx, arg_zilsd_sd *a)
> +{
> + REQUIRE_32BIT(ctx);
> + REQUIRE_ZILSD(ctx);
> + return gen_store_i64(ctx, a);
> +}
> +
> +static bool trans_zclsd_sd(DisasContext *ctx, arg_zclsd_sd *a)
> +{
> + REQUIRE_32BIT(ctx);
> + REQUIRE_ZCLSD(ctx);
and a x8-15 check here as well
Otherwise:
Reviewed-by: Alistair Francis
Re: [PATCH qemu v7 1/1] target/riscv: Add Zilsd and Zclsd extension support
On Thu, May 15, 2025 at 2:07 PM ~liuxu wrote: > > From: lxx <[email protected]> > > This patch adds support for the Zilsd and Zclsd extension, > which is documented at https://github.com/riscv/riscv-zilsd/releases/tag/v1.0 > > Co-developed-by: SUN Dongya > Co-developed-by: LIU Xu > Co-developed-by: ZHAO Fujin > --- > target/riscv/cpu.c| 4 + > target/riscv/cpu_cfg.h| 2 + > target/riscv/insn16.decode| 8 ++ > target/riscv/insn32.decode| 12 ++- > target/riscv/insn_trans/trans_zilsd.c.inc | 112 ++ > target/riscv/tcg/tcg-cpu.c| 20 > target/riscv/translate.c | 1 + > 7 files changed, 157 insertions(+), 2 deletions(-) > create mode 100644 target/riscv/insn_trans/trans_zilsd.c.inc > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 09ded6829a..54072e284d 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -115,6 +115,7 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(zihintntl, PRIV_VERSION_1_10_0, ext_zihintntl), > ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), > ISA_EXT_DATA_ENTRY(zihpm, PRIV_VERSION_1_12_0, ext_zihpm), > +ISA_EXT_DATA_ENTRY(zilsd, PRIV_VERSION_1_12_0, ext_zilsd), > ISA_EXT_DATA_ENTRY(zimop, PRIV_VERSION_1_13_0, ext_zimop), > ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul), > ISA_EXT_DATA_ENTRY(za64rs, PRIV_VERSION_1_12_0, has_priv_1_12), > @@ -138,6 +139,7 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(zcmop, PRIV_VERSION_1_13_0, ext_zcmop), > ISA_EXT_DATA_ENTRY(zcmp, PRIV_VERSION_1_12_0, ext_zcmp), > ISA_EXT_DATA_ENTRY(zcmt, PRIV_VERSION_1_12_0, ext_zcmt), > +ISA_EXT_DATA_ENTRY(zclsd, PRIV_VERSION_1_12_0, ext_zclsd), > ISA_EXT_DATA_ENTRY(zba, PRIV_VERSION_1_12_0, ext_zba), > ISA_EXT_DATA_ENTRY(zbb, PRIV_VERSION_1_12_0, ext_zbb), > ISA_EXT_DATA_ENTRY(zbc, PRIV_VERSION_1_12_0, ext_zbc), > @@ -1653,6 +1655,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { > > MULTI_EXT_CFG_BOOL("zicntr", ext_zicntr, true), > MULTI_EXT_CFG_BOOL("zihpm", ext_zihpm, true), > +MULTI_EXT_CFG_BOOL("zilsd", ext_zilsd, false), > > MULTI_EXT_CFG_BOOL("zba", ext_zba, true), > MULTI_EXT_CFG_BOOL("zbb", ext_zbb, true), > @@ -1692,6 +1695,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { > MULTI_EXT_CFG_BOOL("zcmp", ext_zcmp, false), > MULTI_EXT_CFG_BOOL("zcmt", ext_zcmt, false), > MULTI_EXT_CFG_BOOL("zicond", ext_zicond, false), > +MULTI_EXT_CFG_BOOL("zclsd", ext_zclsd, false), > > /* Vector cryptography extensions */ > MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false), > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > index 8a843482cc..1ca11f99f1 100644 > --- a/target/riscv/cpu_cfg.h > +++ b/target/riscv/cpu_cfg.h > @@ -51,6 +51,7 @@ struct RISCVCPUConfig { > bool ext_zcf; > bool ext_zcmp; > bool ext_zcmt; > +bool ext_zclsd; > bool ext_zk; > bool ext_zkn; > bool ext_zknd; > @@ -73,6 +74,7 @@ struct RISCVCPUConfig { > bool ext_zihintntl; > bool ext_zihintpause; > bool ext_zihpm; > +bool ext_zilsd; > bool ext_zimop; > bool ext_zcmop; > bool ext_ztso; > diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode > index bf893d1c2e..c34020e4dc 100644 > --- a/target/riscv/insn16.decode > +++ b/target/riscv/insn16.decode > @@ -130,10 +130,14 @@ sw110 ... ... .. ... 00 @cs_w > { >ld 011 ... ... .. ... 00 @cl_d >c_flw 011 ... ... .. ... 00 @cl_w > + # *** Zclsd Extension *** > + zclsd_ld011 ... ... .. ... 00 @cl_d > } > { >sd 111 ... ... .. ... 00 @cs_d >c_fsw 111 ... ... .. ... 00 @cs_w > + # *** Zclsd Extension *** > + zclsd_sd111 ... ... .. ... 00 @cs_d > } > > # *** RV32/64C Standard Extension (Quadrant 1) *** > @@ -212,10 +216,14 @@ sw110 . . . 10 @c_swsp >c64_illegal 011 - 0 - 10 # c.ldsp, RES rd=0 >ld 011 . . . 10 @c_ldsp >c_flw 011 . . . 10 @c_lwsp > + # *** Zclsd Extension *** > + zclsd_ldsp 011 . . . 10 @c_ldsp > } > { >sd 111 . . . 10 @c_sdsp >c_fsw 111 . . . 10 @c_swsp > + # *** Zclsd Extension *** > + zclsd_sd111 . . . 10 @c_sdsp > } > > # *** RV64 and RV32 Zcb Extension *** > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index 6d1a13c826..57c242c3bb 100644 > --- a/target/riscv/insn32.decode > +++ b/target/riscv/insn32.decode > @@ -182,8 +182,16 @@ csrrci . 111 . 1110011 @csr > > # *** RV64I Base Instruction Set (in addition to RV32I) *** > lwu . 110 . 011 @i > -ld
