Hi James,
On 20/5/26 06:36, James Hilliard wrote:
This series updates MIPS linux-user unaligned-access behavior and fills
in missing Octeon user-mode instruction support used by existing Octeon
binaries.
The first patches model the Linux/MIPS sysmips ABI pieces needed by
linux-user, including MIPS_FLUSH_CACHE, MIPS_ATOMIC_SET, and the
MIPS_FIXADE policy used to control unaligned scalar access fixups.
User-mode unaligned scalar accesses default to software fixups and
sysmips(MIPS_FIXADE) can toggle SIGBUS/BUS_ADRALN behavior.
Richard Henderson's v7.5 multiplier/QMAC rework is incorporated directly
as nine patches: two TCG preparatory patches and seven Octeon
multiplier/QMAC patches. The Octeon multiplier and QMAC translations now
expand inline in TCG.
The remaining Octeon patches add integer, indexed memory, atomic, COP2
crypto, CHORD, LLM, and CvmCount RDHWR support. The COP2 work is split
into state, helper plumbing, per-engine helper patches, explicit
selector decode, CHORD/LLM, and smoke-test coverage, with each
functional block isolated. The series also adds a small
mips64/mips64el TCG guest test covering representative Octeon integer,
fixed-point, multiplier, RDHWR, and COP2 selector paths. The final patch
corrects the Octeon68XX CP1 feature bits and FCR defaults.
Thanks for this series, I really appreciate your dedication and the
quality of your patches. I have been trying to queue it since v7 but
you keep respinning :) Since the first half is stable and reviewed,
I'll queue that first and send in my next MIPS pull request; less for
you to carry over.
Regards,
Phil.
---
Changes in v10:
- Split the explicit Octeon COP2 selector decode patch into register,
CRC/GFM, HSH/SHA3, stream-cipher, block-cipher, and CHORD/LLM
patches.
- Added Philippe's Reviewed-by tag and local MemOp cleanup for ZCB/ZCBT.
- Added Philippe's Tested-by tags for VMULU, VMM0, and Octeon68XX CP1.
- Restored the original constant-fold output ordering in the TCG mul[us]2
optimization patch.
- Kept Octeon COP2 crypto state architectural by dropping shared-mode and
AES, GFM, SHA3, ZUC, and SNOW3G shadow state.
- Ordered Octeon COP2 crypto CPU state and VMState fields by architectural
selector groups.
- Reworked GFM reflected helpers around the full 128-bit architectural state
and direct RESINP XOR operations.
- Preserved the 64-bit UIA2 GFM reduction path used by SNOW3G F9.
- Added Richard's Reviewed-by tag for the CRC COP2 helpers and masked
variable-length CRC writes to CRCLEN<3:0>.
- Link to v9:
https://lore.kernel.org/qemu-devel/20260519-mips-octeon-missing-insns-v2-v9-0-d7dd735ec...@gmail.com
Changes in v9:
- Used MO_ATOM_NONE for the 128-bit ZCB/ZCBT zero stores.
- Reused octeon_zero_partial_product_state() in the VMM0 translator.
- Removed the shared MIPSOcteonCop2Sel enum from CPU state headers.
- Replaced generic selector-dispatch COP2 helpers with per-operation
helper functions.
- Split COP2 helper implementation into smaller functional subcategory
patches: plumbing, CRC, GFM, SHA3, ZUC, SNOW3G, AES, SMS4, 3DES/KASUMI,
Camellia, HSH, and CHORD/LLM.
- Added COP2 helper declarations to helper.h alongside the per-engine
helper implementation commits.
- Used signed 32-bit DMFC2 direct loads for 32-bit COP2 register
readback.
- Documented the AESRESINP direct register-transfer handling in the translator.
- Combined COP2 selector readback with QMAC/CvmCount smoke coverage.
- Link to v8:
https://lore.kernel.org/qemu-devel/20260517-mips-octeon-missing-insns-v2-v8-0-206151ee7...@gmail.com
Changes in v8:
- Incorporated Richard Henderson's v7.5 9-patch multiplier/QMAC rework
directly into the stack rather than as a follow-up cleanup.
- Added the two v7.5 TCG prep patches as standalone patches:
tcg_gen_addN_i64 and mul[us]2 zero/one optimization.
- Replaced the helper-backed Octeon multiplier/QMAC sequence with the
seven v7.5-shaped patches: multiplier state, MTM, MTP, VMULU, VMM0,
V3MULU, and QMAC.
- Split Octeon COP2 crypto core support into state/migration, helper
implementation, explicit selector decode, and selector readback test
patches.
- Decoded Octeon COP2 selectors explicitly in decodetree and used direct
TCG loads/stores for simple COP2 register moves.
- Kept COP2 helper calls for operation selectors and shared-window state
that require side effects.
- Folded ZCB/ZCBT into one patch so the decodetree wildcard is
introduced in final form.
- Added new Reviewed-by tags from Richard Henderson for MTM/MTP, LA*,
CvmCount, and QMAC/CvmCount test patches.
- Link to v7:
https://lore.kernel.org/qemu-devel/20260514-mips-octeon-missing-insns-v2-v7-0-226686be4...@gmail.com
Changes in v7:
- Rebased on current qemu.git staging (edcc429e9e).
- Reordered the zero-register cleanup after the BADDU/DMUL destination fix
and moved the multiplier-state patch next to the MTM/MTP instruction
patches.
- Applied Philippe's MIPS_FIXADE TB-flag readability tweak.
- U
