Hi
there is quite a bit done in this area of FPGAs, IDELAYS etc for this
application. and also quite a bit written already on TIMENUTS I find
from archives.
From my POV, the pressure on the design is the input circuitry...My gut
is to start with a ADCMP572 and drive several FPGA pins with PECL or
CML . BUT ! I have not thought about the problem very much, nor do I
have much experience with this application (and trying to be a little
modest here considering the company I am in) . The temperature
variability of the comparator hysteresis might be some issue with the
comparator.
I think the FPGA method certainly has many limits , compared to the
analog methods (dual slope phase comparators driving 24 bit ADCs etc,
vernier methods.) But my intuition is that a design that can leverage a
hybrid of analog methods and some handy features available in modern
FPGAs can get the performance.
The idea is, to produce a general purpose high performance measurement
platform for HF region clocks, and pps, without having to resort to
buying an SR620.. analog front end, FPGA (VHDL) , drive for a standard
HD44780 LCD controller to display stuff, and output (USB most likely)
for data analysis on a platform that has plenty of storage.
IDELAYS - there is good granuality (26ps Artix -1) (3 ps Ultrascale
Kintex) , temperature stability is a bit average but that can be dealt
with. The IO delays are variable on the fly for some architectures. It
is not the whole story, but one of the bullets in the revolver in
acheiving the desired granuarity. There are several calibration options.
jitter added in the routing can be minimize with some manual placement
strategies
There is an additional handle at the place and route level on
specifying constraint delays. This is pretty rough but if a good
calibration strategy can be developed, it is worthwhile. (IE conformance
to the constraint delays may vary from build to build so there needs to
be a bit of manual placement ) .
Yes, I think trace delays are useful, although rise time of the
devices together with PCB bandwidth muddies the water , and hence
uncertainty etc etc
I'd like to use a Lattice MACH X02 for this job but I think I will use a
Xilinx due to my familiarity with them (and indeed, performance and
control of the synthesis tools) , and the speed.
(i'm actually an RF person but FPGAs and DSP is an essential these
days) .
-glen
On 27/07/2019 11:49 AM, Hal Murray wrote:
Was considering 16 LVDS receivers and IDELAYS to emulate a single fast
comparator,
I haven't done serious work with FPGAs in 10 or 15 years.
That seems like an obvious hack, but it depends on the implementation details
inside the FPGA. What's the granularity? How much does it change from chip
to chip or over voltage and temperature?
Has anybody published any data?
----------
Another possibility is to use trace delays on the PCB. You have a lumped
delay line with capacitance from the input pad. This may not be practical for
short delays where the bond wires on the chip are not short relative to the
trace lengths.
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