On Thursday, August 21, 2014 at 07:10:32 PM, Fabio Estevam wrote: > When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets > always cleared prior then the READY bit is set in the last BD, which causes > FEC transmission to fail. > > As explained by Ye Li: > > "The TDAR bit is set when the descriptors are all out from TX ring, but the > descriptor properly is in transmitting not READY.
Again, I do not understand this sentence :-( > These are two signals, > and in Ic simulation, we found the TDAR always clear prior than the READY > bit of last BD. And this is the behavior of which version of the FEC IP, the "old" one or the one present in MX6slx ? > In mx6solox, we use a latest version of FEC IP. It looks > the intrinsic behave of TDAR bit is changed in this FEC version, not any > bug in mx6sx." > > Fix this by polling the READY bit of BD after the TDAR polling, which > covers the mx6solox case and does not harm for the other SoCs. > > Signed-off-by: Fabio Estevam <fabio.este...@freescale.com> [...] Best regards, Marek Vasut _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot