Hi Bin, On 7 November 2014 07:07, Bin Meng <bmeng...@gmail.com> wrote: > Hi Simon, > > On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass <s...@chromium.org> wrote: >> Add support for CAR so that we have memory to use prior to DRAM init. >> On link there is a total of 128KB of CAR available, although some is >> used for the memory reference code. >> >> Signed-off-by: Simon Glass <s...@chromium.org> >> --- >> >> arch/x86/Kconfig | 16 ++++ >> arch/x86/cpu/ivybridge/car.S | 156 >> ++++++++++++++++++++++++++++++++++- >> arch/x86/cpu/ivybridge/cpu.c | 2 + >> arch/x86/include/asm/mtrr.h | 121 +++++++++++++++++++++++++++ >> arch/x86/include/asm/post.h | 13 ++- >> board/google/chromebook_link/Kconfig | 12 +++ >> 6 files changed, 318 insertions(+), 2 deletions(-) >> create mode 100644 arch/x86/include/asm/mtrr.h >> >> diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig >> index d9ce129..73fe8b2 100644 >> --- a/arch/x86/Kconfig >> +++ b/arch/x86/Kconfig >> @@ -34,6 +34,22 @@ config TARGET_CHROMEBOOK_LINK >> >> endchoice >> >> +config RAMBASE >> + hex >> + default 0x100000 >> + >> +config RAMTOP >> + hex >> + default 0x200000 >> + >> +config XIP_ROM_SIZE >> + hex >> + default 0x10000 >> + >> +config CPU_ADDR_BITS >> + int >> + default 36 >> + >> config ROM_SIZE >> hex >> default 0x800000 >> diff --git a/arch/x86/cpu/ivybridge/car.S b/arch/x86/cpu/ivybridge/car.S >> index 0480813..391f6df 100644 >> --- a/arch/x86/cpu/ivybridge/car.S >> +++ b/arch/x86/cpu/ivybridge/car.S >> @@ -12,9 +12,163 @@ >> */ >> >> #include <common.h> >> +#include <asm/mtrr.h> >> +#include <asm/post.h> >> +#include <asm/processor-flags.h> >> + >> +#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) >> +#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) > > Should these macros be all capital?
Yes I'll fix that. I had in mind keeping it similar to where it came from, but there are lots of changes needed so it's not worth it. > >> +#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE >> +#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE >> + >> +/* Cache 4GB - MRC_SIZE_KB for MRC */ >> +#define CACHE_MRC_BYTES ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1) >> +#define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES) >> +#define CACHE_MRC_MASK (~CACHE_MRC_BYTES) >> + >> +#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1) >> + >> +#define NoEvictMod_MSR 0x2e0 > > Ditto. > >> /* Note: ebp must not be touched in this code */ > > I think mentioning ebp holds the value of BIST would help more? OK > >> .globl car_init >> car_init: >> - /* TODO: Add cache-as-RAM init here */ >> + post_code(POST_CAR_START) >> + >> + /* Send INIT IPI to all excluding ourself */ >> + movl $0x000C4500, %eax >> + movl $0xFEE00300, %esi >> + movl %eax, (%esi) >> + >> + /* All CPUs need to be in Wait for SIPI state */ >> +wait_for_sipi: >> + movl (%esi), %eax >> + bt $12, %eax >> + jc wait_for_sipi > > Is this a must to send INIT IPI before CAR initialization? I'll test it. [snip] Regards, Simon _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
