On 03/20/2015 05:12 PM, Scott Wood wrote: > On Fri, 2015-03-20 at 17:08 -0700, York Sun wrote: >> >> On 03/20/2015 04:01 PM, Scott Wood wrote: >>> On Thu, 2015-03-19 at 09:45 -0700, York Sun wrote: >>>> #ifndef __ASSEMBLY__ >>>> unsigned long get_board_sys_clk(void); >>>> -unsigned long get_board_ddr_clk(void); >>>> #endif >>>> >>>> #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() >>>> -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() >>>> +#define CONFIG_DDR_CLK_FREQ 133333333 >>>> #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) >>> >>> Why? >> >> The timer clock source is not a fixed clock. It derives from system clock, >> dividing by 4. For this board, the system clock is fixed on board. But I >> don't >> think the timer clock should be hard-coded. > > I was referring to the DDR clock change.
DDR reference clock is fixed on RDB. > >>>> @@ -148,6 +140,7 @@ unsigned long get_board_ddr_clk(void); >>>> #define QIXIS_LBMAP_DFLTBANK 0x00 >>>> #define QIXIS_LBMAP_ALTBANK 0x04 >>>> #define QIXIS_RST_CTL_RESET 0x31 >>>> +#define QIXIS_RST_CTL_RESET_EN 0x30 >>>> #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 >>>> #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 >>>> #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 >>> >>> Is this really a difference between the two boards? >>> >> >> RDB is designed to be compatible in many ways to QDS, but it is still >> different. >> The QIXIS is compatible with most common registers, but not all of them. > > OK. I wasn't sure if it was just something that got added by someone > working on RDB, that also exists on QDS. > The RST_CTL_RESET_EN bit? It was enabled by default on QDS, but disable on RDB. We need to enable it in order to use "reset" command. York _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
