On 16/01/2017 07:16, Alison Wang wrote:
For 64-bit kernel, there is a warning about x1-x3 nonzero in violation
of boot protocol. To fix this issue, input argument 4 is added for
armv8_switch_to_el2 and armv8_switch_to_el1. The input argument 4 will
be set to the right value, such as zero.
Signed-off-by: Alison Wang <alison.w...@nxp.com>
---
Changes in v2:
- Add another input argument 4 for armv8_switch_to_el2 and armv8_switch_to_el1.
- Give up the previous way to adjust the parameters to transfer and make sure
x3 is zero.
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 28 ++++++++++++++--------------
arch/arm/cpu/armv8/sec_firmware_asm.S | 5 +++--
arch/arm/cpu/armv8/start.S | 8 ++++----
arch/arm/cpu/armv8/transition.S | 22 +++++++++++-----------
arch/arm/include/asm/system.h | 8 +++++---
arch/arm/lib/bootm.c | 10 +++++-----
arch/arm/mach-rmobile/lowlevel_init_gen3.S | 8 ++++----
cmd/bootefi.c | 2 +-
8 files changed, 47 insertions(+), 44 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 72f2c11..63215f0 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -378,29 +378,29 @@ cpu_is_le:
b.eq 1f
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
- adr x3, secondary_switch_to_el1
- ldr x4, =ES_TO_AARCH64
+ adr x4, secondary_switch_to_el1
+ ldr x5, =ES_TO_AARCH64
#else
- ldr x3, [x11]
- ldr x4, =ES_TO_AARCH32
+ ldr x4, [x11]
+ ldr x5, =ES_TO_AARCH32
#endif
bl secondary_switch_to_el2
1:
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
- adr x3, secondary_switch_to_el1
+ adr x4, secondary_switch_to_el1
#else
- ldr x3, [x11]
+ ldr x4, [x11]
#endif
- ldr x4, =ES_TO_AARCH64
+ ldr x5, =ES_TO_AARCH64
bl secondary_switch_to_el2
ENDPROC(secondary_boot_func)
ENTRY(secondary_switch_to_el2)
- switch_el x5, 1f, 0f, 0f
+ switch_el x6, 1f, 0f, 0f
0: ret
-1: armv8_switch_to_el2_m x3, x4, x5
+1: armv8_switch_to_el2_m x4, x5, x6
ENDPROC(secondary_switch_to_el2)
ENTRY(secondary_switch_to_el1)
@@ -414,22 +414,22 @@ ENTRY(secondary_switch_to_el1)
/* physical address of this cpus spin table element */
add x11, x1, x0
- ldr x3, [x11]
+ ldr x4, [x11]
ldr x5, [x11, #24]
ldr x6, =IH_ARCH_DEFAULT
cmp x6, x5
b.eq 2f
- ldr x4, =ES_TO_AARCH32
+ ldr x5, =ES_TO_AARCH32
bl switch_to_el1
-2: ldr x4, =ES_TO_AARCH64
+2: ldr x5, =ES_TO_AARCH64
switch_to_el1:
- switch_el x5, 0f, 1f, 0f
+ switch_el x6, 0f, 1f, 0f
0: ret
-1: armv8_switch_to_el1_m x3, x4, x5
+1: armv8_switch_to_el1_m x4, x5, x6
ENDPROC(secondary_switch_to_el1)
/* Ensure that the literals used by the secondary boot code are
diff --git a/arch/arm/cpu/armv8/sec_firmware_asm.S
b/arch/arm/cpu/armv8/sec_firmware_asm.S
index 903195d..747b53f 100644
--- a/arch/arm/cpu/armv8/sec_firmware_asm.S
+++ b/arch/arm/cpu/armv8/sec_firmware_asm.S
@@ -57,7 +57,8 @@ ENDPROC(_sec_firmware_support_psci_version)
* x0: argument, zero
* x1: machine nr
* x2: fdt address
- * x3: kernel entry point
+ * x3: input argument
+ * x4: kernel entry point
* @param outputs for secure firmware:
* x0: function id
* x1: kernel entry point
@@ -65,7 +66,7 @@ ENDPROC(_sec_firmware_support_psci_version)
* x3: fdt address
*/
ENTRY(armv8_el2_to_aarch32)
- mov x0, x3
+ mov x0, x4
You no longer need x0 as scratch register. Just write ...
mov x3, x2
mov x2, x1
mov x1, x0
... x4 directly into x1 here.
Otherwise looks good to me. So with the change above you can add my
Reviewed-by: Alexander Graf <ag...@suse.de>
tag in the next version.
Alex
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