Michael Schnell wrote:
With a decently constructed MMU (cache after MMU viewed from the CPU, as done with all X86 CPUS, AFAIK), only DMA and SMP issues should make cache flush necessary, I have no idea, how the 68 K MMU and cache are constructed.
It has nothing to do with m68k or "decently" constructed MMU's. If you have a harvard style cache (which is by far the most common arrangement these days). Then if you are copying or manipulating instructions in memory (eg copying them), they are passing through the data cache - as data, and then you need to flush the data cache before you try and execute in that region. (Obviously a write-thru data cache, or coherency logic between the instruction and data cache would obviate the need to flush). Regards Greg ------------------------------------------------------------------------ Greg Ungerer -- Chief Software Dude EMAIL: [EMAIL PROTECTED] SnapGear -- a Secure Computing Company PHONE: +61 7 3435 2888 825 Stanley St, FAX: +61 7 3891 3630 Woolloongabba, QLD, 4102, Australia WEB: http://www.SnapGear.com _______________________________________________ uClinux-dev mailing list uClinux-dev@uclinux.org http://mailman.uclinux.org/mailman/listinfo/uclinux-dev This message was resent by uclinux-dev@uclinux.org To unsubscribe see: http://mailman.uclinux.org/mailman/options/uclinux-dev
