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Today's Topics:
1. Re: UHD Announcement - February 25rd 2011 (Thomas Tsou)
2. Re: path for the latest images for usrp N210 (Nick Foster)
3. Re: UHD Announcement - February 25rd 2011 (Josh Blum)
4. Re: experience changing USRP2 main oscillator w/UHD? (Josh Blum)
5. USRPN210 Stopped responding during transmission (Scott Johnston)
6. Re: USRP2 frequency offset (Guanbo Zheng)
7. Multiple-carrier signal with Simulink and USRP2 (Nick Pers)
8. Re: Multiple-carrier signal with Simulink and USRP2
(Mike McLernon)
----------------------------------------------------------------------
Message: 1
Date: Mon, 28 Feb 2011 13:02:53 -0500
From: Thomas Tsou <[email protected]>
To: Josh Blum <[email protected]>
Cc: [email protected], "[email protected]"
<[email protected]>
Subject: Re: [USRP-users] UHD Announcement - February 25rd 2011
Message-ID: <[email protected]>
Content-Type: text/plain; charset=us-ascii
On Fri, Feb 25, 2011 at 8:32 PM, Josh Blum <[email protected]> wrote:
> -----------------------------------------------------------------------
> -- re-clocking support
> -----------------------------------------------------------------------
> Re-clocking support has been added to the API:
> http://www.ettus.com/uhd_docs/doxygen/html/classuhd_1_1usrp_1_1multi__usrp.html#a99254abfa5259b70a020e667eee619b9
>
> On a USRP1 board, you can specify usrp->set_master_clock_rate(52e6) so
> that the driver knows to use 52MHz in its calculations. Note that this
> does not really modify the clock rate, it just informs the driver of the
> hardware changes.
>
> In contrast, when setting the clock rate on the usrp-e100, the driver
> will dynamically reprogram the registers on the clock generator to
> obtain the desired rate. See application notes:
> http://www.ettus.com/uhd_docs/manual/html/usrp_e1xx.html#changing-the-master-clock-rate
I've been getting the following error during make since I
changed the clock rate. Did I brick the FPGA? I can't seem to
find the special pass-through image anywhere.
USRP-E100 clock control: VCO calibration timeout
Vitals:
GNU C++ version 4.5.2 20101204 (prerelease); Boost_104100;
UHD_003.20110226000831.77641c6
Linux version 2.6.35 (balister@astro) (gcc version 4.5.2 20101026
(prerelease) (GCC) ) #1 PREEMPT Fri Nov 5 08:56:09 PDT 2010
usrp_e100_fpga_compat3_feb_25.bin
Thomas
------------------------------
Message: 2
Date: Mon, 28 Feb 2011 10:13:15 -0800
From: Nick Foster <[email protected]>
To: "Chomal, Sunil" <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] path for the latest images for usrp N210
Message-ID: <1298916795.14768.1.camel@crapshoot>
Content-Type: text/plain; charset="UTF-8"
On Mon, 2011-02-28 at 23:21 +0530, Chomal, Sunil wrote:
> Hi,
> I updated my usrp n210 fpga and firmware image with the latest images.
> What is worrying me is the following warning after I request uhd_usrp_probe
> Warning:
> Could not locate USRP1 firmware.
> Please install the images package
>
> Is my firmware update gone ok ??
> Why is the USRP1 firmware being asked for usrp n210?
It just means the USRP1 firmware isn't installed where it's expecting to
find it. UHD looks for all connected devices when initialized, and this
includes looking for USRP1s connected via USB. Since you aren't using a
USRP1, you don't have to worry about it. Looks like your firmware update
went fine.
--n
> Just to note, I have not build the gnu radio for windows, instead I am using
> the pre built exe installer from http://www.ettus.com/downloads/gnuradio/
>
>
> D:\Program Files\UHD 002.20110202043814.fa35192\lib>..\bin\uhd_usrp_probe
> Win32; Microsoft Visual C++ version 10.0; Boost_104400;
> UHD_002.20110202043814.f
> a35192
>
> /////////////////////////////////////////////////////////////
> Warning:
> Could not locate USRP1 firmware.
> Please install the images package.
> Current recv sock buff size: 50000000 bytes
> mboard0 MIMO master
> _____________________________________________________
> /
> | Device: USRP2/N Series device
> | _____________________________________________________
> | /
> | | Mboard: USRP-N210 mboard
> | | rev: 2561
> | | mac-addr: a0:36:fa:25:31:60
> | | ip-addr: 192.168.10.2
> | | serial: E6R11Y0UP
> | | _____________________________________________________
> | | /
> | | | RX DSP: USRP-N210 ddc0
> | | | Codec Rate: 100.000000 Msps
> | | _____________________________________________________
> | | /
> | | | TX DSP: USRP-N210 duc0
> | | | Codec Rate: 100.000000 Msps
> | | _____________________________________________________
> | | /
> | | | RX Dboard: USRP-N210 dboard (rx unit)
> | | | _____________________________________________________
> | | | /
> | | | | RX Subdev: DBSRX2 (0x0012)
> | | | | Antennas: J3
> | | | | Freq range: 800.000 to 2400.000 Mhz
> | | | | Gain range GC1: 0.0 to 73.0 step 0.1 dB
> | | | | Gain range BBG: 0.0 to 15.0 step 1.0 dB
> | | | | Connection Type: c
> | | | | Uses LO offset: No
> | | | _____________________________________________________
> | | | /
> | | | | RX Codec: USRP-N210 adc - ads62p44
> | | | | Gain range digital: 0.0 to 6.0 step 0.5 dB
> | | | | Gain range digital-fine: 0.0 to 0.5 step 0.1 dB
> | | _____________________________________________________
> | | /
> | | | TX Dboard: USRP-N210 dboard (tx unit)
> | | | _____________________________________________________
> | | | /
> | | | | TX Subdev: Unknown - Unknown (0xffff)
> | | | | Antennas:
> | | | | Freq range: 0.000 to 0.000 Mhz
> | | | | Gain Elements: None
> | | | | Connection Type: C
> | | | | Uses LO offset: No
> | | | _____________________________________________________
> | | | /
> | | | | TX Codec: USRP-N210 dac - ad9777
> | | | | Gain Elements: None
>
> ///////////////////////////////////////////////////////
> Regards
> Sunil
>
> > -----Original Message-----
> > From: [email protected] [mailto:usrp-users-
> > [email protected]] On Behalf Of Josh Blum
> > Sent: Monday, February 28, 2011 12:25 PM
> > To: [email protected]
> > Subject: Re: [USRP-users] path for the latest images for usrp N210
> >
> > > Hi ,
> > > I want to update my USRP N210 with the latest firmware and fpga images.
> > > Is the image (usrp_n2xx_fw.bin , usrp_n210_fpga.bin) in the folder UHD-
> > images-002.20110122035832.cd5631f-
> > Linux<http://www.ettus.com/downloads/uhd_images/UHD-images-most-
> > recent/UHD-images-002.20110122035832.cd5631f-Linux.zip> at
> > http://www.ettus.com/downloads/uhd_images/UHD-images-most-recent/ the
> > correct image to use?
> > >
> >
> > That is correct.
> >
> > > Just wanted to confirm ,so that I don't brick my USRP N210 !!
> > >
> >
> > Make sure you use the most recent net burner from the uhd repository and
> > that should not be possible.
> >
> > -Josh
> >
> > _______________________________________________
> > USRP-users mailing list
> > [email protected]
> > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
------------------------------
Message: 3
Date: Mon, 28 Feb 2011 10:15:09 -0800
From: Josh Blum <[email protected]>
To: Thomas Tsou <[email protected]>
Cc: [email protected], "[email protected]"
<[email protected]>
Subject: Re: [USRP-users] UHD Announcement - February 25rd 2011
Message-ID: <[email protected]>
Content-Type: text/plain; charset=ISO-8859-1
On 02/28/2011 10:02 AM, Thomas Tsou wrote:
> On Fri, Feb 25, 2011 at 8:32 PM, Josh Blum <[email protected]> wrote:
>> -----------------------------------------------------------------------
>> -- re-clocking support
>> -----------------------------------------------------------------------
>> Re-clocking support has been added to the API:
>> http://www.ettus.com/uhd_docs/doxygen/html/classuhd_1_1usrp_1_1multi__usrp.html#a99254abfa5259b70a020e667eee619b9
>>
>> On a USRP1 board, you can specify usrp->set_master_clock_rate(52e6) so
>> that the driver knows to use 52MHz in its calculations. Note that this
>> does not really modify the clock rate, it just informs the driver of the
>> hardware changes.
>>
>> In contrast, when setting the clock rate on the usrp-e100, the driver
>> will dynamically reprogram the registers on the clock generator to
>> obtain the desired rate. See application notes:
>> http://www.ettus.com/uhd_docs/manual/html/usrp_e1xx.html#changing-the-master-clock-rate
>
> I've been getting the following error during make since I
> changed the clock rate. Did I brick the FPGA? I can't seem to
> find the special pass-through image anywhere.
>
> USRP-E100 clock control: VCO calibration timeout
>
If you can talk to it, then its still fine. Can you talk?
I think my wait for lock() is messed up since my 52Mhz is dead on and
its still printing that.
-josh
> Vitals:
>
> GNU C++ version 4.5.2 20101204 (prerelease); Boost_104100;
> UHD_003.20110226000831.77641c6
>
> Linux version 2.6.35 (balister@astro) (gcc version 4.5.2 20101026
> (prerelease) (GCC) ) #1 PREEMPT Fri Nov 5 08:56:09 PDT 2010
>
> usrp_e100_fpga_compat3_feb_25.bin
>
> Thomas
------------------------------
Message: 4
Date: Mon, 28 Feb 2011 10:28:29 -0800
From: Josh Blum <[email protected]>
To: [email protected]
Subject: Re: [USRP-users] experience changing USRP2 main oscillator
w/UHD?
Message-ID: <[email protected]>
Content-Type: text/plain; charset=ISO-8859-1
> The former has proven to be even more challenging as there appears to
> some places in the host code that make an assumption that
> get_master_clock_rate() returns the oscillator frequency and other
> places that assume it's the FPGA clock rate (i.e., input clock ==
> output clock, which is not the case when we're using the 122MHz osc).
>
The master clock rate in the uhd refers to the codec/fpga/dsp clock
rate. Where do you think this is incorrect?
-josh
------------------------------
Message: 5
Date: Mon, 28 Feb 2011 14:40:34 -0500
From: Scott Johnston <[email protected]>
To: "[email protected]" <[email protected]>
Subject: [USRP-users] USRPN210 Stopped responding during transmission
Message-ID: <[email protected]>
Content-Type: text/plain; charset="ISO-8859-1"; format=flowed
I was transmitting with my USRPN210, running a uhd modified version of
ofdm_benchmark_tx.py, and it suddenly stopped outputting to the display,
and my program hung. I opened a new terminal and tried again, but I got
the error
Runtime Error: No devices found for --->
Device Address
addr: 192.168.10.2
Then I tried uhd_find_devices and it found nothing. I also restarted the
usrp, and it went trough the right led sequence.
Any idea what caused this and what the solution is?
TIA,
Scott
--
Scott Johnston
MIT Lincoln Laboratory
244 Wood Street, Lexington, MA 02420-9108
(781) 981-8196
[email protected]
------------------------------
Message: 6
Date: Mon, 28 Feb 2011 19:37:36 -0600
From: Guanbo Zheng <[email protected]>
To: "Song, Mujun CAPT KR USAF AETC AFIT/ENG" <[email protected]>
Cc: "<[email protected]>" <[email protected]>
Subject: Re: [USRP-users] USRP2 frequency offset
Message-ID: <[email protected]>
Content-Type: text/plain; charset="gb2312"
The CFO should be stable for that USRP.
Different USRP would have different CFO, but it would locate in the range of
3ppm-10ppm(I remember)
Interp/decim do not affect CFO, because it depends on hardware only.
Best,
Guanbo
On Feb 28, 2011, at 7:36 AM, "Song, Mujun CAPT KR USAF AETC AFIT/ENG"
<[email protected]> wrote:
> Hi, all.
>
>
>
> I know there?s a frequency offset that comes from USRP2 hardware. But I have
> one more question on the frequency offset. I found that the frequency offset
> varies as the decimation factor changes. So does the frequency offset varies
> for every decimation factor or for every individual USRP2? Or do every USRP2
> have the same offset or does the offset varies every time I run the USRP2?
>
>
>
> Hope to get response from you.
>
>
>
> Thanks,
>
> Mujun
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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Message: 7
Date: Tue, 1 Mar 2011 13:32:40 +0200
From: "Nick Pers" <[email protected]>
To: <[email protected]>
Subject: [USRP-users] Multiple-carrier signal with Simulink and USRP2
Message-ID: <FE6ACAD95F9E4725ACEB36DB18465DE2@REX>
Content-Type: text/plain; charset="iso-8859-7"
Hi all,
Is it possible to transmit multiple carrier signal (OFDM) with Simulink and
USRP2?
Thanks,
NIck
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Message: 8
Date: Tue, 1 Mar 2011 14:06:16 +0000
From: Mike McLernon <[email protected]>
To: Nick Pers <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] Multiple-carrier signal with Simulink and
USRP2
Message-ID:
<e3879be9a282cb45aab7ce258a9ae48f058...@exmb-01-ah.ad.mathworks.com>
Content-Type: text/plain; charset="us-ascii"
Hi Nick,
It certainly is possible, but you will have to serialize the data first. The
USRP2 Transmitter block accepts only column vector inputs.
Hth,
Mike
From: [email protected]
[mailto:[email protected]] On Behalf Of Nick Pers
Sent: Tuesday, March 01, 2011 6:33 AM
To: [email protected]
Subject: [USRP-users] Multiple-carrier signal with Simulink and USRP2
Hi all,
Is it possible to transmit multiple carrier signal (OFDM) with Simulink and
USRP2?
Thanks,
NIck
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