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Today's Topics:
1. Re: query regarding rx_samples_to_file script (Josh Blum)
----------------------------------------------------------------------
Message: 1
Date: Thu, 03 Mar 2011 10:53:35 -0800
From: Josh Blum <[email protected]>
To: [email protected]
Subject: Re: [USRP-users] query regarding rx_samples_to_file script
Message-ID: <[email protected]>
Content-Type: text/plain; charset=ISO-8859-1
> 1) rate -> corresponds to the final decimated data (through cic and
> hbf) used to log to file ? Are there example scripts to individually
> control the decimation through this stages.
Rate is the samples per second between host and device. You cannot
control the stages individually.
decimation = dsp_rate/host_rate, such that decimation is an integer;
- no hbf will be used when decimation is odd
- one hbf will be used when decimation%2 == 0
- another hbf will be used when (decimation%2)%2 == 0
> 2) freq -> the centre freq of the band of interest ? Is the down
> conversion direct or heterodyne? If heterodyne how is the IF
> frequency and the cordic freq decided? If the down-conversion is
> direct , are there example scripts available to control PLL settings
> and the cordic register settings?
Tuning occurs in two stages, the daughterboard IF is tuned as close as
possible to the requested center frequency. The FPGA DDC handles the
error in approximation between desired center freq and dboard IF.
These elements can be set individually:
http://www.ettus.com/uhd_docs/doxygen/html/classuhd_1_1usrp_1_1multi__usrp.html#a9b61448f392466e20572fdcb042e8ec6
http://www.ettus.com/uhd_docs/doxygen/html/structuhd_1_1tune__request__t.html
> 3) gain -> this corresponds to which gain stage->I suppose there are
> two/three stages of gain boosting in the RF chain
There are multiple gain stages depending upon the hardware, they may be
individually accessed or treated as a sinlge gain element:
http://www.ettus.com/uhd_docs/doxygen/html/classuhd_1_1usrp_1_1multi__usrp.html#a4c406b7964f4cc18dc5b57cafcb345c1
> 4) How can we control the bandwidth of the filter before ADC .
>
If there is a controllable filter, it can be set through set_bandwidth:
http://www.ettus.com/uhd_docs/doxygen/html/classuhd_1_1usrp_1_1multi__usrp.html#a4e026819f286e69c48c2e1956d95c6fb
Also see dboard app notes for specific values:
http://www.ettus.com/uhd_docs/manual/html/dboards.html
-Josh
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End of USRP-users Digest, Vol 7, Issue 9
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