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Today's Topics:
1. Re: RFNoC RF loopback in X310 (Nick Foster)
2. Transmit number to FPGA (Rohit Dilip)
----------------------------------------------------------------------
Message: 1
Date: Sat, 22 Apr 2017 19:47:15 +0000
From: Nick Foster <[email protected]>
To: "Dixon, James L" <[email protected]>,
"[email protected]" <[email protected]>
Subject: Re: [USRP-users] RFNoC RF loopback in X310
Message-ID:
<ca+jmmq-weorqi2hv1zsz3py5htmqk_dh9uyaeq4w3h4ebx+...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
A belated update: here's a blog post detailing how to do hardware loopback
in RFNoC. It covers both the X310 and the E3xx (for which just a bit more
work is necessary). In general it should work for any device which supports
RFNoC.
I've disabled comments on the site because the internet is a dumpster fire
but feel free to ask questions or provide comments to the list or to me
personally.
https://corvid.io/2017/04/22/stupid-rfnoc-tricks-loopback/
Best,
Nick
On Thu, Mar 30, 2017 at 9:59 AM Nick Foster <[email protected]> wrote:
> This is probably a good time for me to start working on that RFNoC
> loopback tutorial.
>
> Give me a few days, things are pretty busy right now. But yes, it's
> possible, and the latency depends on what you do to the signal between RX
> and TX but can be as low as <10us.
>
> --n
>
> On Thu, Mar 30, 2017, 8:26 AM Dixon, James L via USRP-users <
> [email protected]> wrote:
>
>> Hi,
>>
>>
>>
>> I am new to RFNoC. I have installed the RFNoC branch of gnu-radio and I
>> have it working, where I can build a new FPGA image using Vivado and load
>> it onto the FPGA in an X310. I would like to create an RF loopback in the
>> FPGA using GRC without going through the host processor. I found several
>> discussions on this topic from about 1.5 years ago, when there seemed to be
>> issues doing what I want to do, but I don?t see any more recent posts
>> stating that this problem has been solved and giving the solution. I?ve
>> tried a number of ideas that were given in these discussions, but I can?t
>> seem to get it to work. Is there a solution or a demo out there now?
>>
>>
>>
>> One of the reasons I want to do the above is to measure the minimum RF
>> loopback latency of such a design. Has this been done and are the results
>> out there anywhere?
>>
>>
>>
>> Thanks,
>>
>>
>>
>> Jim
>> _______________________________________________
>> USRP-users mailing list
>> [email protected]
>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>
>
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Message: 2
Date: Sat, 22 Apr 2017 18:22:12 -0400
From: Rohit Dilip <[email protected]>
To: "[email protected]" <[email protected]>
Subject: [USRP-users] Transmit number to FPGA
Message-ID:
<calumccdxkakoq5ugtxrjdv1xynpz-scarccrwzrsuack4cn...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Hi,
I modified an FPGA on a USRP device to generate and output a wave using a
lookup table. Is there a way to use gnuradio to input a number to the FPGA,
so I could generate that number of waves, summed together? I'd like to be
able to input several numbers -- say f1,f2,f3... -- to the FPGA, then
output sin(f1*t) + sin(f2*t) + ... If I have the ability to input a series
of numbers I can easily modify the verilog code. It seems that there should
be a way, since I can pass the master_clock_rate in the existing blocks,
but I haven't been able to find exactly where in the Ettus github
repository those parameters are.
Best,
Rohit
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