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Today's Topics:
1. Re: x310 rfnoc fpga code (Jason Matusiak)
2. Alternatives for uhd_fft in Ubuntu (Dario Fertonani)
3. Re: B210 GPS L1 receiver in Simulink (Mike McLernon)
4. [FPGA IMAGES] Image too large to E310 (Rub?n Vogel)
5. Re: [FPGA IMAGES] Image too large to E310 (Jonathon Pendlum)
6. Re: x310 rfnoc fpga code (Anon Lister)
7. Re: x310 rfnoc fpga code (Jason Matusiak)
8. Re: x310 rfnoc fpga code (Derek Kozel)
9. Issue running UHD via sshfs on E310 (Jessica Iwamoto)
----------------------------------------------------------------------
Message: 1
Date: Thu, 27 Apr 2017 12:05:33 -0400
From: Jason Matusiak <[email protected]>
To: Derek Kozel <[email protected]>, Lihua Ren
<[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] x310 rfnoc fpga code
Message-ID:
<[email protected]>
Content-Type: text/plain; charset="utf-8"; Format="flowed"
To expand on what Derek said (because I have fallen into the same rabbit
hole in the past; Jonathon has said he will remove the option for sample
rate from the block for the X310 in the future to reduce confusion), the
X310's RFNoC radio block runs at the system clock of the X310 (default
of 200MHz; the other options are 100MHz, and 184.32MHz). You will want
to set your DDC to have an input rate of 200MHZ, and an output rate of
1.6284MHz. That said, the DDC will only select integer divisors, so
your resulting output won't be exact.
Sadly, I don't think that there is a integer divisor that will get you
the exact value based on your required end frequency (though I could be
wrong).
On 04/27/2017 10:38 AM, Derek Kozel via USRP-users wrote:
> Hello Lihua,
>
> The X310 RFNoC Radio block will always have a sample rate of either
> 200 MS/s or 100 MS/s if using the TwinRX. If you look in the log
> messages you will see a warning saying that the 16.384 MHz rate could
> not be set.
>
> Regards,
> Derek
>
> On Thu, Apr 27, 2017 at 3:28 PM, Lihua Ren via USRP-users
> <[email protected] <mailto:[email protected]>> wrote:
>
> hi,
> My design is as follows :in GNUradio, RFnoc: radio-->RFnoc: DDC
> ---> RFnoc:my block,
> in radio block, sampling rate :16.384MHz,
> in DDC block ?input rate :16.384MHz,output rate :1.6384MHz,
> I think the data rate in the FPGA code should be :1.6384MHz ?but
> the use of ChipScope to see the data rate does not match.why?
> ,I would like to know the axis interface the i_valid cycle,
> and effective time?
> Thanks.
>
>
>
> _______________________________________________
> USRP-users mailing list
> [email protected] <mailto:[email protected]>
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
> <http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com>
>
>
>
>
> _______________________________________________
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> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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Message: 2
Date: Thu, 27 Apr 2017 09:22:17 -0700
From: Dario Fertonani <[email protected]>
To: "[email protected]" <[email protected]>
Subject: [USRP-users] Alternatives for uhd_fft in Ubuntu
Message-ID:
<CAJGEdAjODq=UK54JZ4KjZ4wL37-ygqnkT=61fkzmmpbirvr...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Is anybody aware of Ubuntu alternatives for the uhd_fft app? I'm looking
for a basic spectrum analyzer.
The uhd_fft app is great, but impractical for me because the packaged
version of Gnuradio is always behind the latest UHD version (from Ettus
Research PPA), and source code compiling of UHD/Gnuradio is an overkill for
most of my uses cases.
As many Ubuntu users have experienced, the current version of Gnuradio apps
dies out on Ubuntu 16.04 LTS with the following error.
RuntimeError:
GR-UHD detected ABI compatibility mismatch with UHD library.
GR-UHD was build against ABI: 3.9.0-0,
but UHD library reports ABI: 3.10.1
Suggestion: install an ABI compatible version of UHD,
or rebuild GR-UHD component against this ABI version.
Thanks,
Dario
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Message: 3
Date: Thu, 27 Apr 2017 16:55:50 +0000
From: Mike McLernon <[email protected]>
To: Mihkel M <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] B210 GPS L1 receiver in Simulink
Message-ID:
<bn1pr05mb437878d320aa0e2103b6a31e9...@bn1pr05mb437.namprd05.prod.outlook.com>
Content-Type: text/plain; charset="us-ascii"
Hi Mihkel,
A couple of points:
1. The sample time is 1/1023000, not the sample rate.
2. You shouldn't need any additional blocks before you save the signal to
workspace.
Hth,
Mike
From: USRP-users [mailto:[email protected]] On Behalf Of
Mihkel M via USRP-users
Sent: Thursday, April 27, 2017 4:55 AM
To: [email protected]
Subject: [USRP-users] B210 GPS L1 receviver in Simulink
Hi.
My friend has project, where he has also couple of questions:
"I am trying to receive and play GPS L1 signal using Simulink and B210. For
observation I am using Ucenter 5.0. An active GPS antenna is used for
receiving. I am not sure what the receiver block parameters should be because
based on my calculations (decimation=master clock rate*sample time) I used
Fc=1.57542 Ghz, master clock rate 6.138Mhz, decimation is 6 and sample rate is
1/1023000. Should I use some additional blocks before saving the signal to
workspace and playing it back from workspace to the transmitter block? In
additon to that can someone please explain how IF is formulated using receiver
block parameters?"
Mihkel.
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Message: 4
Date: Thu, 27 Apr 2017 15:05:05 -0300
From: Rub?n Vogel <[email protected]>
To: [email protected]
Subject: [USRP-users] [FPGA IMAGES] Image too large to E310
Message-ID:
<cam7gm7bunp7o2ahvvwwynsuaoovxgit6lcdv5h8wzdq5vzl...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Hey,I am analyzing the structure of the different images in Xilinx
Vivado that are possible to generate using the Makefile:
fpga/usrp3/top/e300/Makefile
This Makefile allows to generate 3 types of images for the Ettus E310:
- make E310- make E310_RFNOC- make E3XX_IDLE
I generated the 3 types of images using the GUI = 1 option and I have
the following questions:
1 ? After generating the image E310, the resource utilization
information provided by Vivado indicates that the use of LUT's is
greater than 100% (115% to be exact). How is this possible?
2 ? The E3XX_IDLE image always loads at the end when we use the
uhd_usrp_probe command on the E310. What is the purpose of this image?
Rub?n O. VogelAdvanced Computer Engineering StudentDigital
Communications LabSchool of Exact, Physical and Natural
SciencesNational University of Cordoba ? Argentina
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Message: 5
Date: Thu, 27 Apr 2017 13:30:29 -0500
From: Jonathon Pendlum <[email protected]>
To: Rub?n Vogel <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] [FPGA IMAGES] Image too large to E310
Message-ID:
<cagdo0uqgtwrs0nr4trxjjo_cq1y6i6njguxzndwtd6mg6xc...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
>
> 1 ? After generating the image E310, the resource utilization information
> provided by Vivado indicates that the use of LUT's is greater than 100%
> (115% to be exact). How is this possible?
>
Our makefile changes build parameters, but those changes are not applied
when doing a GUI build. Try the "Area Optimization High" strategy for
Synthesis.
> 2 ? The E3XX_IDLE image always loads at the end when we use the
> uhd_usrp_probe commandn on the E310. What is the purpose of this image?
When you are not actively using the FPGA / RF frontend (e.g. when running a
UHD app or GNU Radio flowgraph), the idle image is loaded to reduce power
consumption.
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Message: 6
Date: Thu, 27 Apr 2017 14:37:05 -0400
From: Anon Lister <[email protected]>
To: Jason Matusiak <[email protected]>
Cc: Lihua Ren <[email protected]>, "[email protected]"
<[email protected]>, Derek Kozel <[email protected]>
Subject: Re: [USRP-users] x310 rfnoc fpga code
Message-ID:
<camp204s6hkbuz9qx71qxzycfqpn_qwfqseayffguymzczik...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Oh, is this integer behavior the same on the DUCs? This would explain why I
was having issues when I was messing around with using rfnoc for playing
back arbitrary rate data on the x300 in the same manner I am able to with a
b205 (utilizing the configurable master clock.)
On Apr 27, 2017 12:07 PM, "Jason Matusiak via USRP-users" <
[email protected]> wrote:
> To expand on what Derek said (because I have fallen into the same rabbit
> hole in the past; Jonathon has said he will remove the option for sample
> rate from the block for the X310 in the future to reduce confusion), the
> X310's RFNoC radio block runs at the system clock of the X310 (default of
> 200MHz; the other options are 100MHz, and 184.32MHz). You will want to set
> your DDC to have an input rate of 200MHZ, and an output rate of 1.6284MHz.
> That said, the DDC will only select integer divisors, so your resulting
> output won't be exact.
>
> Sadly, I don't think that there is a integer divisor that will get you the
> exact value based on your required end frequency (though I could be wrong).
>
>
> On 04/27/2017 10:38 AM, Derek Kozel via USRP-users wrote:
>
> Hello Lihua,
>
> The X310 RFNoC Radio block will always have a sample rate of either 200
> MS/s or 100 MS/s if using the TwinRX. If you look in the log messages you
> will see a warning saying that the 16.384 MHz rate could not be set.
>
> Regards,
> Derek
>
> On Thu, Apr 27, 2017 at 3:28 PM, Lihua Ren via USRP-users <
> [email protected]> wrote:
>
>> hi,
>>
>> My design is as follows :in GNUradio, RFnoc: radio-->RFnoc: DDC --->
>> RFnoc:my block,
>> in radio block, sampling rate :16.384MHz,
>> in DDC block ?input rate :16.384MHz,output rate :1.6384MHz,
>> I think the data rate in the FPGA code should be :1.6384MHz ?but the
>> use of ChipScope to see the data rate does not match.why?
>> ,I would like to know the axis interface the i_valid cycle,
>> and effective time?
>> Thanks.
>>
>>
>>
>>
>> _______________________________________________
>> USRP-users mailing list
>> [email protected]
>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>
>>
>
>
> _______________________________________________
> USRP-users mailing
> [email protected]http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
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Message: 7
Date: Thu, 27 Apr 2017 14:40:04 -0400
From: Jason Matusiak <[email protected]>
To: Anon Lister <[email protected]>
Cc: Lihua Ren <[email protected]>, "[email protected]"
<[email protected]>, Derek Kozel <[email protected]>
Subject: Re: [USRP-users] x310 rfnoc fpga code
Message-ID:
<[email protected]>
Content-Type: text/plain; charset="utf-8"; Format="flowed"
Yes, I believe that the DUC works the same way as the DDC. And one more
piece information, one of the Ettus folks clarified on the list in the
last couple of weeks that due to the way the DDC/DUC work, a integer
multiple of 4 will give even better results than other integers. So if
you have the ability to choose your output freq in other applications,
you might want to keep that in mind.
On 04/27/2017 02:37 PM, Anon Lister wrote:
> Oh, is this integer behavior the same on the DUCs? This would explain
> why I was having issues when I was messing around with using rfnoc for
> playing back arbitrary rate data on the x300 in the same manner I am
> able to with a b205 (utilizing the configurable master clock.)
>
>
> On Apr 27, 2017 12:07 PM, "Jason Matusiak via USRP-users"
> <[email protected] <mailto:[email protected]>> wrote:
>
> To expand on what Derek said (because I have fallen into the same
> rabbit hole in the past; Jonathon has said he will remove the
> option for sample rate from the block for the X310 in the future
> to reduce confusion), the X310's RFNoC radio block runs at the
> system clock of the X310 (default of 200MHz; the other options are
> 100MHz, and 184.32MHz). You will want to set your DDC to have an
> input rate of 200MHZ, and an output rate of 1.6284MHz. That said,
> the DDC will only select integer divisors, so your resulting
> output won't be exact.
>
> Sadly, I don't think that there is a integer divisor that will get
> you the exact value based on your required end frequency (though I
> could be wrong).
>
>
> On 04/27/2017 10:38 AM, Derek Kozel via USRP-users wrote:
>> Hello Lihua,
>>
>> The X310 RFNoC Radio block will always have a sample rate of
>> either 200 MS/s or 100 MS/s if using the TwinRX. If you look in
>> the log messages you will see a warning saying that the 16.384
>> MHz rate could not be set.
>>
>> Regards,
>> Derek
>>
>> On Thu, Apr 27, 2017 at 3:28 PM, Lihua Ren via USRP-users
>> <[email protected] <mailto:[email protected]>>
>> wrote:
>>
>> hi,
>> My design is as follows :in GNUradio, RFnoc: radio-->RFnoc:
>> DDC ---> RFnoc:my block,
>> in radio block, sampling rate :16.384MHz,
>> in DDC block ?input rate :16.384MHz,output rate :1.6384MHz,
>> I think the data rate in the FPGA code should be
>> :1.6384MHz ?but the use of ChipScope to see the data rate
>> does not match.why?
>> ,I would like to know the axis interface the i_valid
>> cycle, and effective time?
>> Thanks.
>>
>>
>>
>> _______________________________________________
>> USRP-users mailing list
>> [email protected] <mailto:[email protected]>
>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>> <http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com>
>>
>>
>>
>>
>> _______________________________________________
>> USRP-users mailing list
>> [email protected] <mailto:[email protected]>
>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>> <http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com>
> _______________________________________________ USRP-users mailing
> list [email protected]
> <mailto:[email protected]>
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
> <http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com>
>
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Message: 8
Date: Thu, 27 Apr 2017 20:05:36 +0100
From: Derek Kozel <[email protected]>
To: Jason Matusiak <[email protected]>
Cc: Anon Lister <[email protected]>, Lihua Ren
<[email protected]>, "[email protected]"
<[email protected]>
Subject: Re: [USRP-users] x310 rfnoc fpga code
Message-ID:
<CAA+K=tt9z7jb0q5KKe2KND=SOYbmVA1+LwTM=jufauwsmij...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Hi Jason,
Thanks for including the 184.32 MHz sample rate. That is an important one
to note for the LTE and cellular applications.
The Transmit side of the radio is also fixed at one of the three above
rates.
The DDC filters include a set of halfband filters which are used
preferentially to the CIC filter. Decimation rates which use these halfband
filters have lower passband loss and sharper roll off in the transition
region. Each halfband decimates by two so divisible by two, four, or eight
will provide better performance than other rates. UHD will warn about odd
decimation rates as these have some roll off in the passband.
On Thu, Apr 27, 2017 at 7:40 PM, Jason Matusiak <
[email protected]> wrote:
> Yes, I believe that the DUC works the same way as the DDC. And one more
> piece information, one of the Ettus folks clarified on the list in the last
> couple of weeks that due to the way the DDC/DUC work, a integer multiple of
> 4 will give even better results than other integers. So if you have the
> ability to choose your output freq in other applications, you might want to
> keep that in mind.
>
>
>
> On 04/27/2017 02:37 PM, Anon Lister wrote:
>
> Oh, is this integer behavior the same on the DUCs? This would explain why
> I was having issues when I was messing around with using rfnoc for playing
> back arbitrary rate data on the x300 in the same manner I am able to with a
> b205 (utilizing the configurable master clock.)
>
>
> On Apr 27, 2017 12:07 PM, "Jason Matusiak via USRP-users" <
> [email protected]> wrote:
>
>> To expand on what Derek said (because I have fallen into the same rabbit
>> hole in the past; Jonathon has said he will remove the option for sample
>> rate from the block for the X310 in the future to reduce confusion), the
>> X310's RFNoC radio block runs at the system clock of the X310 (default of
>> 200MHz; the other options are 100MHz, and 184.32MHz). You will want to set
>> your DDC to have an input rate of 200MHZ, and an output rate of 1.6284MHz.
>> That said, the DDC will only select integer divisors, so your resulting
>> output won't be exact.
>>
>> Sadly, I don't think that there is a integer divisor that will get you
>> the exact value based on your required end frequency (though I could be
>> wrong).
>>
>>
>> On 04/27/2017 10:38 AM, Derek Kozel via USRP-users wrote:
>>
>> Hello Lihua,
>>
>> The X310 RFNoC Radio block will always have a sample rate of either 200
>> MS/s or 100 MS/s if using the TwinRX. If you look in the log messages you
>> will see a warning saying that the 16.384 MHz rate could not be set.
>>
>> Regards,
>> Derek
>>
>> On Thu, Apr 27, 2017 at 3:28 PM, Lihua Ren via USRP-users <
>> [email protected]> wrote:
>>
>>> hi,
>>>
>>> My design is as follows :in GNUradio, RFnoc: radio-->RFnoc: DDC --->
>>> RFnoc:my block,
>>> in radio block, sampling rate :16.384MHz,
>>> in DDC block ?input rate :16.384MHz,output rate :1.6384MHz,
>>> I think the data rate in the FPGA code should be :1.6384MHz ?but the
>>> use of ChipScope to see the data rate does not match.why?
>>> ,I would like to know the axis interface the i_valid cycle,
>>> and effective time?
>>> Thanks.
>>>
>>>
>>>
>>>
>>> _______________________________________________
>>> USRP-users mailing list
>>> [email protected]
>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>>
>>>
>>
>>
>> _______________________________________________
>> USRP-users mailing
>> [email protected]http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>
>> _______________________________________________ USRP-users mailing list
>> [email protected] http://lists.ettus.com/mailman
>> /listinfo/usrp-users_lists.ettus.com
>
>
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Message: 9
Date: Thu, 27 Apr 2017 22:37:54 +0000
From: Jessica Iwamoto <[email protected]>
To: usrp-users <[email protected]>
Subject: [USRP-users] Issue running UHD via sshfs on E310
Message-ID:
<sn1pr09mb10085d91b0e257de971dcbca9b...@sn1pr09mb1008.namprd09.prod.outlook.com>
Content-Type: text/plain; charset="us-ascii"
Hi all,
I am following the instructions here
(https://kb.ettus.com/Software_Development_on_the_E310_and_E312) to build the
SDK and cross compiling setup for the E310, however, I am running into some
issues with UHD. After following all the steps in the link above, up to
installing UHD, I tried to run one of the UHD examples but it seems to get
stuck. I got the following output when running the benchmark_rate example:
./benchmark_rate --tx_rate 1e6
[INFO] [UHD] linux; GNU C++ version 4.9.2; Boost_105700;
UHD_3.11.0.git-162-g2790b51f
Creating the usrp device with: ...
[INFO] [E300] Loading FPGA image: /usr/share/uhd/images/usrp_e310_fpga.bit...
[INFO] [E300] FPGA image loaded
[INFO] [E300] Initializing core control...
[INFO] [E300] Performing register loopback test...
[INFO] [E300] Register loopback test passed
After this the program gets stuck and just hangs at this point. Any help would
be appreciated!
Thanks,
Jessica
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