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Today's Topics:
1. Re: x310 fpga (Lihua Ren)
2. Re: x310 fpga (Jonathon Pendlum)
3. Re: USRP-users Digest, Vol 81, Issue 14 (Jahnavendra Mattipa)
4. Some questions about USRP E100 (Lee)
5. Re: NI-USRP 15.0 driver is not working on Ubuntu 16.04
(Dennis Stroh)
6. USRP1 Support (Pol Henarejos)
7. Re: USRP1 Support (Marcus M?ller)
8. - Problem with building custom RFNoC FPGA image (Daniel Rauschen)
9. E310 read write registers (olivani)
10. Re: USRP1 Support ([email protected])
11. Does a gnu_radio convert the block codes to the HDL code?
(Ali Khanjani)
12. Re: Does a gnu_radio convert the block codes to the HDL code?
(Paolo Palana)
13. Re: Does a gnu_radio convert the block codes to the HDL code?
([email protected])
14. Re: - Problem with building custom RFNoC FPGA image
(Jonathon Pendlum)
----------------------------------------------------------------------
Message: 1
Date: Mon, 15 May 2017 08:30:56 +0800 (CST)
From: "Lihua Ren" <[email protected]>
To: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] x310 fpga
Message-ID: <[email protected]>
Content-Type: text/plain; charset="gbk"
hi,
in X310 FPGA code ?I have some problems about timing ,and hope you can help me.
e.g ,in noc_block_fft.v, clk_in?that is radio_clk:200M? ------>DCM ip
core(pll)----> clkout ?114.688M, implement ,and some problems about timing .
then I set false-path from ... to ... ,but timing still wrong.Can you help me?
Importantly?in X310 FPGA code ?all the modules' the main clock is 200MHz,
butmy block need is 114.688MHz, which can be achieved?
At 2017-05-03 09:35:35, "Jonathon Pendlum" <[email protected]> wrote:
I would suggest making two counters. One that continuously increments (lets
call it 'count') and another that only increments when m_axis_data_tvalid &
m_axis_data_tready are both asserted (lets call it 'valid_count'). Make the
counters 'count' and 'valid_count' 48 bits wide. Then use chipscope to see the
value of those counters after running your flowgraph for a few minutes.
Throughput = valid_count / count.
I would also suggest having your custom block just loopback AXI Wrapper's
output to its input (m_axis_data_tdata -> s_axis_data_tdata) so your block's
logic does not interfere with this throughput calculation.
On Tue, May 2, 2017 at 8:07 PM, Lihua Ren <[email protected]> wrote:
hi,Jonathon
My design is as follows :in GNUradio, RFnoc: radio-->RFnoc: DDC ---> RFnoc:my
block,
in radio block, sampling rate :200MHz,
in DDC block ?input rate :200MHz,output rate :200kHz,
then, in my block ,I think the data rate in the FPGA code should be :200kHz
?but the use of ChipScope to see the data rate is about 1.67MHz.
1.67MHz = The number of sampling data *(1/200MHz) ,200 Mhz is ila core 's clk.
Since RFNoC is packetized, you will see bursts of data?You're right ?but I can
calculate i_valid cycle in my block ?I need continuous data, using the RAM IP
core cache to ensure subsequent work ?Is that true?
At 2017-05-02 22:55:18, "Jonathon Pendlum" <[email protected]> wrote:
Hi,
How are you measuring the sample rate in your block? Since RFNoC is packetized,
you will see bursts of data, so you need to find the average rate over many
clock cycles.
What does the console log say? Do you see any warnings about the sample rate?
Jonathon
On May 2, 2017 7:55 AM, "Lihua Ren via USRP-users" <[email protected]>
wrote:
hi,
My design is as follows :in GNUradio, RFnoc: radio-->RFnoc: DDC ---> RFnoc:my
block,
in radio block, sampling rate :200MHz,
in DDC block ?input rate :200MHz,output rate :200kHz,
I think the data rate in the FPGA code should be :200kHz ?but the use of
ChipScope to see the data rate is about 1.67MHz.why?
Thanks.
_______________________________________________
USRP-users mailing list
[email protected]
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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Message: 2
Date: Sun, 14 May 2017 22:55:03 -0500
From: Jonathon Pendlum <[email protected]>
To: Lihua Ren <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] x310 fpga
Message-ID:
<cagdo0uqvgkaqr3ai4mk+nadrptg4jmnsw8wdwvvztryu3e9...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Hi,
Why do you need a clock rate of 114.688 MHz for your block?
Jonathon
On Sun, May 14, 2017 at 7:30 PM, Lihua Ren via USRP-users <
[email protected]> wrote:
> hi,
>
>
> in X310 FPGA code ?I have some problems about timing ,and hope you can
> help me. e.g ,in noc_block_fft.v, clk_in?that is radio_clk:200M?
> ------>DCM ip core(pll)----> clkout ?114.688M, implement ,and some
> problems about timing . then I set false-path from ... to ... ,but timing
> still
> wrong.Can you help me?
>
> Importantly?in X310 FPGA code ?all the modules' the main clock is 200MHz,
> butmy block need is 114.688MHz, which can be achieved?
>
> At 2017-05-03 09:35:35, "Jonathon Pendlum" <[email protected]>
> wrote:
>
> I would suggest making two counters. One that continuously increments
> (lets call it 'count') and another that only increments when
> m_axis_data_tvalid & m_axis_data_tready are both asserted (lets call it
> 'valid_count'). Make the counters 'count' and 'valid_count' 48 bits wide.
> Then use chipscope to see the value of those counters after running your
> flowgraph for a few minutes. Throughput = valid_count / count.
>
> I would also suggest having your custom block just loopback AXI Wrapper's
> output to its input (m_axis_data_tdata -> s_axis_data_tdata) so your
> block's logic does not interfere with this throughput calculation.
>
> On Tue, May 2, 2017 at 8:07 PM, Lihua Ren <[email protected]> wrote:
>
>>
>> hi,Jonathon
>>
>> My design is as follows :in GNUradio, RFnoc: radio-->RFnoc: DDC --->
>> RFnoc:my block,
>> in radio block, sampling rate :200MHz,
>> in DDC block ?input rate :200MHz,output rate :200kHz,
>> then, in my block ,I think the data rate in the FPGA code should be :200kHz
>> ?but
>> the use of ChipScope to see the data rate is about 1.67MHz.
>>
>> 1.67MHz = The number of sampling data *(1/200MHz) ,200 Mhz is ila core
>> 's clk.
>>
>> Since RFNoC is packetized, you will see bursts of data?You're right ?but
>> I can calculate i_valid cycle in my block ?I need continuous data, using
>> the RAM IP core cache to ensure subsequent work ?Is that true?
>>
>> At 2017-05-02 22:55:18, "Jonathon Pendlum" <[email protected]>
>> wrote:
>>
>> Hi,
>>
>> How are you measuring the sample rate in your block? Since RFNoC is
>> packetized, you will see bursts of data, so you need to find the average
>> rate over many clock cycles.
>>
>> What does the console log say? Do you see any warnings about the sample
>> rate?
>>
>>
>>
>> Jonathon
>>
>> On May 2, 2017 7:55 AM, "Lihua Ren via USRP-users" <
>> [email protected]> wrote:
>>
>>> hi,
>>> My design is as follows :in GNUradio, RFnoc: radio-->RFnoc: DDC --->
>>> RFnoc:my block,
>>> in radio block, sampling rate :200MHz,
>>> in DDC block ?input rate :200MHz,output rate :200kHz,
>>> I think the data rate in the FPGA code should be :200kHz ?but the use
>>> of ChipScope to see the data rate is about 1.67MHz.why?
>>> Thanks.
>>>
>>>
>>>
>>>
>>> _______________________________________________
>>> USRP-users mailing list
>>> [email protected]
>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>>
>>>
>>
>>
>>
>
>
>
>
>
>
>
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
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Message: 3
Date: Mon, 15 May 2017 09:47:01 +0530
From: Jahnavendra Mattipa <[email protected]>
To: [email protected]
Subject: Re: [USRP-users] USRP-users Digest, Vol 81, Issue 14
Message-ID:
<CAH5NE-ZTKrmMz_yWiQWA_rKXoViZQ_1-mO1=-=aockcfsmt...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Hello Marcus sir,
I am using 70MHz frequency for the USRP1 device and these are
processed with the GNU Radio.
On Sun, May 14, 2017 at 9:30 PM, <[email protected]> wrote:
> Send USRP-users mailing list submissions to
> [email protected]
>
> To subscribe or unsubscribe via the World Wide Web, visit
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
> or, via email, send a message with subject or body 'help' to
> [email protected]
>
> You can reach the person managing the list at
> [email protected]
>
> When replying, please edit your Subject line so it is more specific
> than "Re: Contents of USRP-users digest..."
>
>
> Today's Topics:
>
> 1. Re: Signal generator power receiving issue (Marcus D. Leech)
>
>
> ----------------------------------------------------------------------
>
> Message: 1
> Date: Sat, 13 May 2017 15:40:44 -0400
> From: "Marcus D. Leech" <[email protected]>
> To: [email protected]
> Subject: Re: [USRP-users] Signal generator power receiving issue
> Message-ID: <[email protected]>
> Content-Type: text/plain; charset="windows-1252"; Format="flowed"
>
> On 05/13/2017 10:52 AM, Jahnavendra Mattipa via USRP-users wrote:
> > Hello all,
> > I have to receive the Satellite data through the antenna and it is
> > a secondary thing. Before going to check the satellite data i have to
> > check the signal generator because they both are doing same
> > processing. So, i recently test the signal generator power using the
> > USRP. Here i am getting one issue is that when i giving -40dB gain
> > value to the USRP from the signal generator the wave is showing the
> > received data is -36dB. One more signal is -63dB and i am receiving
> > the -39dB. There is a small difference between receiving data when
> > compared to input data.
> > I have to know what is the USRP gain and how it is processing
> > the signal generator or satellite data? I am giving the some power
> > from signal generator and what happens if i change the gain in "USRP
> > Source"? I noted the data from -110dB to +110dB and the receiving
> > data is not changing from -110dB to 0dB, it is changing from 0dB to
> > 50dB. The same process is continued for -63dB also.
> > Can anyone kindly help me to solve this issue! If anyone has
> > advices and comments, they would be greatly appreciated.
> >
> > Best Regards,
> > M.Jahnavendra
> >
> YOu haven't said what frequency, no which USRP device you're using, nor
> what application you're using to measure power. This all matters.
>
>
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> ------------------------------
>
> Subject: Digest Footer
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
> ------------------------------
>
> End of USRP-users Digest, Vol 81, Issue 14
> ******************************************
>
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Message: 4
Date: Mon, 15 May 2017 10:54:25 +0800 (CST)
From: Lee <[email protected]>
To: [email protected]
Subject: [USRP-users] Some questions about USRP E100
Message-ID: <[email protected]>
Content-Type: text/plain; charset="gbk"
Hi ,
I feel great appreciate if someone can help me ~_~
Now, I have used usrp E100 for some days, download e1xx-003-make.tar.bz2 from
http://files.ettus.com/e1xx_images/current/,
Everything seemed to run correctly with "SD card creation was successful"
message at the end of the running of the "MakeEttusSDCard.sh" script. Then I
put the SD card back into the usrp E100, then powered on the device, it worked
like the picture showed bellow.
The website which showed in quoted text can't access any more.
I DON'T KNOW HOW TO DO NEXT. SOS, Can anybody help me ? Thanks very much.
+++++++++++++++++++ Quoted text +++++++++++ From USRP-users mailing list
++++++++++++++++++
[USRP-users] USRP E100 / E110 SD Card Image e1xx-001 Release
Nguyen Truongnguyentb at postech.ac.kr
Wed Nov 16 18:47:56 EST 2011
..........
On Mon, Nov 7, 2011 at 7:20 PM, Richard Clarke <richard at clarke.biz>wrote:
>>>>>> Hi Ben,
>>>>>> I've just built the latest release e1xx-001 image using Option 1 in
>>>>>> the instructions at:
>>>>>>http://ettus-apps.sourcerepo.com/redmine/ettus/projects/usrpe1xx/wiki/FAQ#How-do-I-create-re-create-E1xx-SD-Card-Images>>>>>>>>>>>>
>>>>>> I have used an 8GB microSDHC card. Everything seemed to run correctly
>>>>>>>>>>>> with "SD card creation was successful" message at the end of the
>>>>>>running of the "MakeEttusSDCard.sh" script.
Users that already have a E1xx Device can create a copy of this
>>>>>>> image using the instructions here:
>>>>>>>http://code.ettus.com/redmine/ettus/projects/usrpe1xx/wiki/FAQ#How-do-I-create-re-create-E1xx-SD-Card-Images
>>>>>>> Let us know if you have any questions, and happy hacking =)
>>>>>>> Cheers,
>>>>>>> Ben
+++++++++++++++++++ Quoted text +++++++++++ From USRP-users mailing list
++++++++++++++++++
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Message: 5
Date: Mon, 15 May 2017 09:30:36 +0000
From: Dennis Stroh <[email protected]>
To: Marcus M?ller <[email protected]>,
"[email protected]" <[email protected]>
Subject: Re: [USRP-users] NI-USRP 15.0 driver is not working on Ubuntu
16.04
Message-ID:
<[email protected]>
Content-Type: text/plain; charset="iso-8859-1"
Hello Marcus M,
my current kernel version is 4.8.0-49-generic. Ubuntu 16.04 only provides
downgrade options to kernel version 4.4. The latest NI driver V15.0 supports
only 4.2.x. So, is there no chance to get the USRP X300 runing via PCIe on
Ubuntu 16.04?
Kind regards
________________________________
Von: USRP-users [[email protected]]" im Auftrag von "Marcus
M?ller via USRP-users [[email protected]]
Gesendet: Samstag, 13. Mai 2017 14:00
An: [email protected]
Betreff: Re: [USRP-users] NI-USRP 15.0 driver is not working on Ubuntu 16.04
Hello Mr. Stroh,
I don't have a Ubuntu machine at hand to test myself, but:
what's the kernel version you're running (`uname -r`)? Might be that the NI
drivers don't support that kernel (yet).
Best regards,
Marcus M
On 11.05.2017 12:15, Dennis Stroh via USRP-users wrote:
Hi,
I want to connect a USRP X300 via PCIe to achieve high data throughput.
I installed and updated the NI-USRP 15.0 driver by following the steps of the
description in the USRP Manual.
However, the update failed and the driver is not properly working.
What should I do to make this configuration work?
Kind regards
_______________________________________________
USRP-users mailing list
[email protected]<mailto:[email protected]>
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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Message: 6
Date: Mon, 15 May 2017 15:30:07 +0200
From: Pol Henarejos <[email protected]>
To: [email protected]
Subject: [USRP-users] USRP1 Support
Message-ID: <[email protected]>
Content-Type: text/plain; charset="utf-8"; Format="flowed"
Dear all,
I am trying to get my old USRP1 running again but unfortunately I cannot
receive properly. To test it I use benchmark_rate utility.
Whilst transmission seems works properly (no underflows or complaints),
the reception is not working. A lot of "D" appear, regardless the
sampling rate.
I am using UHD 3.9 LTS (but I am able to use my self-compilation from
git source).
The command I use is
benchmark_rate --rx_rate 500e3
and the output is
-- Loading firmware image: C:\CTTC\UHD\share\uhd\images\usrp1_fw.ihx... done
*** Warning! ***
Benchmark results will be inaccurate on USRP1 due to insufficient features.
Creating the usrp device with: ...
-- Opening a USRP1 device...
-- Loading FPGA image: C:\CTTC\UHD\share\uhd\images\usrp1_fpga.rbf... done
-- Using FPGA clock rate of 64.000000MHz...
Using Device: Single USRP:
Device: USRP1 Device
Mboard 0: USRP1
RX Channel: 0
RX DSP: 0
RX Dboard: B
RX Subdev: BasicRX (AB)
TX Channel: 0
TX DSP: 0
TX Dboard: A
TX Subdev: LFTX (AB)
Setting device timestamp to 0...
Testing receive rate 0.500000 Msps on 1 channels
DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD
DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD
Benchmark rate summary:
Num received samples: 5001216
Num dropped samples: 19148
Num overflows detected: 0
Num transmitted samples: 0
Num sequence errors: 0
Num underflows detected: 0
Num late commands: 0
Num timeouts: 0
Done!
Any clue?
Thank you.
--
Pol Henarejos
Researcher, MSc
[email protected]
Centre Tecnol?gic de Telecomunicacions de Catalunya (CTTC)
Av. Carl Friedrich Gauss, 7
08860 Castelldefels, Barcelona (Spain)
Tel: +34 93 645 29 00 Ext: 2177
Fax. +34 93 645 29 01
www.cttc.es
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Message: 7
Date: Mon, 15 May 2017 15:37:38 +0200
From: Marcus M?ller <[email protected]>
To: [email protected]
Subject: Re: [USRP-users] USRP1 Support
Message-ID: <[email protected]>
Content-Type: text/plain; charset="windows-1252"
Hi Pol,
Ds on USB2 are really really rare. I don't have a USRP1 to test here,
locally, but my first suspect would be your Operating System's USB
stack. Can you try to use the device on a different OS, maybe on a
different machine?
To try, you could download and burn the GNU Radio liveSDR environment[1]
to an USB stick, and boot just any PC with it. For your downloading
pleasure, I'd recommend either using the torrent file, or the eu2 Mirror
(which happens to be my server).
Best regards, and thanks,
Marcus
[1] https://wiki.gnuradio.org/index.php/GNU_Radio_Live_SDR_Environment
On 05/15/2017 03:30 PM, Pol Henarejos via USRP-users wrote:
> Dear all,
>
> I am trying to get my old USRP1 running again but unfortunately I
> cannot receive properly. To test it I use benchmark_rate utility.
> Whilst transmission seems works properly (no underflows or
> complaints), the reception is not working. A lot of "D" appear,
> regardless the sampling rate.
>
> I am using UHD 3.9 LTS (but I am able to use my self-compilation from
> git source).
> The command I use is
>
> benchmark_rate --rx_rate 500e3
>
> and the output is
>
> -- Loading firmware image:
> C:\CTTC\UHD\share\uhd\images\usrp1_fw.ihx... done
> *** Warning! ***
> Benchmark results will be inaccurate on USRP1 due to insufficient
> features.
>
> Creating the usrp device with: ...
> -- Opening a USRP1 device...
> -- Loading FPGA image: C:\CTTC\UHD\share\uhd\images\usrp1_fpga.rbf...
> done
> -- Using FPGA clock rate of 64.000000MHz...
> Using Device: Single USRP:
> Device: USRP1 Device
> Mboard 0: USRP1
> RX Channel: 0
> RX DSP: 0
> RX Dboard: B
> RX Subdev: BasicRX (AB)
> TX Channel: 0
> TX DSP: 0
> TX Dboard: A
> TX Subdev: LFTX (AB)
>
> Setting device timestamp to 0...
> Testing receive rate 0.500000 Msps on 1 channels
> DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD
DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD
>
> Benchmark rate summary:
> Num received samples: 5001216
> Num dropped samples: 19148
> Num overflows detected: 0
> Num transmitted samples: 0
> Num sequence errors: 0
> Num underflows detected: 0
> Num late commands: 0
> Num timeouts: 0
>
>
> Done!
>
> Any clue?
>
> Thank you.
>
>
>
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
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Message: 8
Date: Mon, 15 May 2017 11:21:52 +0200
From: Daniel Rauschen <[email protected]>
To: "[email protected]" <[email protected]>
Subject: [USRP-users] - Problem with building custom RFNoC FPGA image
Message-ID: <[email protected]>
Content-Type: text/plain; charset="utf-8"; Format="flowed"
Hello usrp-users,
I have a problems building a custom RFNoC FPGA image.
I'm trying to run the following command "./uhd_image_builder.py window
fft -d x300 -t X300_RFNOC_HG -m 5 --fill-with-fifos", with a full Vivado
Design license for the 2015.4 version. The error message (see
attachment) says there are license related problems, but I don't think
this is the problem (see attachment for vlm output). Vivado is found and
the script says "Environment successfully initialized.", are there any
steps I'm missing?
Any suggestions are highly welcome.
The build system is:
Kubuntu 16.04.1 LTS
Kernel 4.4.0-57-lowlatency
UHD UHD_4.0.0.rfnoc-devel-316-g24b98579
Vivado 2015.4 Design version
USRP x300
With best regards,
Daniel
-------------- next part --------------
rauschen@n210:~/Programmieren/UHD/uhd/fpga-src/usrp3/tools/scripts$
./uhd_image_builder.py window fft -d x300 -t X300_RFNOC_HG -m 5
--fill-with-fifos
--Using the following blocks to generate image:
* window
* fft
Adding CE instantiation file for 'X300_RFNOC_HG'
changing temporarily working directory to
/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/tools/scripts/../../top/x300
Setting up a 64-bit FPGA build environment for the USRP-X3x0...
- Vivado: Found (/opt/Xilinx/Vivado/2015.4/bin)
- Vivado HLS: Found (/opt/Xilinx/Vivado_HLS/2015.4/bin)
Environment successfully initialized.
make -f Makefile.x300.inc bin NAME=X300_RFNOC_HG ARCH=kintex7
PART_ID=xc7k325t/ffg900/-2 BUILD_1G=1 BUILD_10G=1 SFP0_1GBE=1 SFP1_10GBE=1
RFNOC=1 X300=1 EXTRA_DEFS="BUILD_1G=1 BUILD_10G=1 SFP0_1GBE=1 SFP1_10GBE=1
RFNOC=1 X300=1"
make[1]: Entering directory
'/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/top/x300'
BUILDER: Checking tools...
* GNU bash, version 4.3.46(1)-release (x86_64-pc-linux-gnu)
* Python 2.7.12
* Vivado v2015.4 (64-bit)
========================================================
BUILDER: Building IP ten_gig_eth_pcs_pma
========================================================
BUILDER: Staging IP in build directory...
BUILDER: Reserving IP location:
/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma
BUILDER: Retargeting IP to part kintex7/xc7k325t/ffg900/-2...
BUILDER: Building IP...
****** Vivado v2015.4 (64-bit)
**** SW Build 1412921 on Wed Nov 18 09:44:32 MST 2015
**** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
source
/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/tools/scripts/viv_generate_ip.tcl
# set xci_file $::env(XCI_FILE) ;
# set part_name $::env(PART_NAME) ;
# set gen_example_proj $::env(GEN_EXAMPLE) ;
# set synth_ip $::env(SYNTH_IP) ;
# set ip_name [file rootname [file tail $xci_file]] ;
# file delete -force "$xci_file.out"
# create_project -part $part_name -in_memory -ip
# set_property target_simulator XSim [current_project]
# add_files -norecurse -force $xci_file
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository
'/opt/Xilinx/Vivado/2015.4/data/ip'.
WARNING: [IP_Flow 19-3664] IP 'ten_gig_eth_pcs_pma' generated file not found
'/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.dcp'.
Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'ten_gig_eth_pcs_pma' generated file not found
'/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_stub.v'.
Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'ten_gig_eth_pcs_pma' generated file not found
'/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_stub.vhdl'.
Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'ten_gig_eth_pcs_pma' generated file not found
'/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_sim_netlist.vhdl'.
Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'ten_gig_eth_pcs_pma' generated file not found
'/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_sim_netlist.v'.
Please regenerate to continue.
# reset_target all [get_files $xci_file]
# puts "BUILDER: Generating IP Target..."
BUILDER: Generating IP Target...
# generate_target all [get_files $xci_file]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP
'ten_gig_eth_pcs_pma'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP
'ten_gig_eth_pcs_pma'...
WARNING: [IP_Flow 19-650] IP license key '[email protected]'
is enabled with a Design_Linking license.
WARNING: [IP_Flow 19-650] IP license key '[email protected]'
is enabled with a Design_Linking license.
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP
'ten_gig_eth_pcs_pma'...
WARNING: [IP_Flow 19-650] IP license key '[email protected]'
is enabled with a Design_Linking license.
WARNING: [IP_Flow 19-650] IP license key '[email protected]'
is enabled with a Design_Linking license.
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP
'ten_gig_eth_pcs_pma'...
# if [string match $synth_ip "1"] {
# puts "BUILDER: Synthesizing IP Target..."
# synth_ip [get_ips $ip_name]
# }
BUILDER: Synthesizing IP Target...
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository
'/opt/Xilinx/Vivado/2015.4/data/ip'.
Command: synth_design -top ten_gig_eth_pcs_pma -part xc7k325tffg900-2 -mode
out_of_context
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t'
WARNING: [Common 17-348] Failed to get the license for feature 'Synthesis'
and/or device 'xc7k325t'
1 Infos, 1 Warnings, 0 Critical Warnings and 1 Errors encountered.
synth_design failed
ERROR: [Common 17-345] A valid license was not found for feature 'Synthesis'
and/or device 'xc7k325t'. Please run the Vivado License Manager for assistance
in determining
which features and devices are licensed for your system.
Resolution: Check the status of your licenses in the Vivado License Manager.
For debug help search Xilinx Support for "Licensing FAQ".
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Vivado 12-398] No designs are open
****** Webtalk v2015.4 (64-bit)
**** SW Build 1412921 on Wed Nov 18 09:44:32 MST 2015
**** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
source
/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k325tffg900-2/.Xil/Vivado-3215-n210/webtalk/labtool_webtalk.tcl
-notrace
INFO: [Common 17-206] Exiting Webtalk at Mon May 15 10:59:37 2017...
INFO: [Vivado 12-3441] generate_netlist_ip - operation complete
# if [string match $gen_example_proj "1"] {
# puts "BUILDER: Generating Example Design..."
# open_example_project -force -dir . [get_ips $ip_name]
# }
BUILDER: Generating Example Design...
INFO: [IP_Flow 19-1686] Generating 'Examples' target for IP
'ten_gig_eth_pcs_pma'...
****** Vivado v2015.4 (64-bit)
**** SW Build 1412921 on Wed Nov 18 09:44:32 MST 2015
**** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
source
/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_ex.tcl
# set srcIpDir
"/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma"
# create_project -name ten_gig_eth_pcs_pma_example -force
# set_property part xc7k325tffg900-2 [current_project]
# set_property target_language verilog [current_project]
# set_property simulator_language MIXED [current_project]
# set_property coreContainer.enable false [current_project]
# set returnCode 0
# import_ip -files [list [file join $srcIpDir ten_gig_eth_pcs_pma.xci]] -name
ten_gig_eth_pcs_pma
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository
'/opt/Xilinx/Vivado/2015.4/data/ip'.
WARNING: [IP_Flow 19-3664] IP 'ten_gig_eth_pcs_pma' generated file not found
'/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.dcp'.
Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'ten_gig_eth_pcs_pma' generated file not found
'/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_stub.v'.
Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'ten_gig_eth_pcs_pma' generated file not found
'/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_stub.vhdl'.
Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'ten_gig_eth_pcs_pma' generated file not found
'/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_sim_netlist.vhdl'.
Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'ten_gig_eth_pcs_pma' generated file not found
'/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_sim_netlist.v'.
Please regenerate to continue.
CRITICAL WARNING: [IP_Flow 19-4299] Failed to copy
'/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.dcp'
to
'/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma_example/ten_gig_eth_pcs_pma_example.srcs/sources_1/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.dcp'
CRITICAL WARNING: [IP_Flow 19-4299] Failed to copy
'/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_stub.v'
to
'/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma_example/ten_gig_eth_pcs_pma_example.srcs/sources_1/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_stub.v'
CRITICAL WARNING: [IP_Flow 19-4299] Failed to copy
'/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_stub.vhdl'
to
'/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma_example/ten_gig_eth_pcs_pma_example.srcs/sources_1/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_stub.vhdl'
CRITICAL WARNING: [IP_Flow 19-4299] Failed to copy
'/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_sim_netlist.vhdl'
to
'/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma_example/ten_gig_eth_pcs_pma_example.srcs/sources_1/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_sim_netlist.vhdl'
CRITICAL WARNING: [IP_Flow 19-4299] Failed to copy
'/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_sim_netlist.v'
to
'/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma_example/ten_gig_eth_pcs_pma_example.srcs/sources_1/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_sim_netlist.v'
# reset_target {open_example} [get_ips ten_gig_eth_pcs_pma]
# proc _filter_supported_targets {targets ip} {
# set res {}
# set all [get_property SUPPORTED_TARGETS $ip]
# foreach target $targets {
# lappend res {*}[lsearch -all -inline -nocase $all $target]
# }
# return $res
# }
# generate_target -quiet [_filter_supported_targets {instantiation_template
synthesis simulation implementation shared_logic} [get_ips
ten_gig_eth_pcs_pma]] [get_ips ten_gig_eth_pcs_pma]
# add_files -scan_for_includes -quiet -fileset [current_fileset] \
# [list [file join $srcIpDir
example_design/ten_gig_eth_pcs_pma_example_design.v]] \
# [list [file join $srcIpDir
example_design/support/ten_gig_eth_pcs_pma_support.v]] \
# [list [file join $srcIpDir
example_design/support/ten_gig_eth_pcs_pma_ff_synchronizer_rst2.v]] \
# [list [file join $srcIpDir
example_design/support/ten_gig_eth_pcs_pma_shared_clock_and_reset.v]] \
# [list [file join $srcIpDir
example_design/support/ten_gig_eth_pcs_pma_gt_common.v]]
# add_files -quiet -fileset [current_fileset -constrset] \
# [list [file join $srcIpDir
example_design/ten_gig_eth_pcs_pma_example_design.xdc]]
# if { [catch {current_fileset -simset} exc] } { create_fileset -simset sim_1 }
# add_files -quiet -scan_for_includes -fileset [current_fileset -simset] \
# [list [file join $srcIpDir simulation/demo_tb.v]]
# set_property USED_IN_SYNTHESIS false [get_files [list [file join $srcIpDir
simulation/demo_tb.v]]]
# import_files
INFO: [filemgmt 20-348] Importing the appropriate files for fileset: 'constrs_1'
INFO: [filemgmt 20-348] Importing the appropriate files for fileset: 'sim_1'
INFO: [filemgmt 20-348] Importing the appropriate files for fileset: 'sources_1'
# set_property TOP [lindex [find_top] 0] [current_fileset]
# update_compile_order -fileset [current_fileset]
# update_compile_order -fileset [current_fileset -simset]
# generate_target -quiet all [concat [ get_ips -quiet -filter scope=={} ]
[get_files -quiet *bd ] ]
# export_ip_user_files -force
INFO: [exportsim-Tcl-35] Exporting simulation files for "XSIM" (Xilinx Vivado
Simulator)...
INFO: [exportsim-Tcl-29] Script generated:
'/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma_example/ten_gig_eth_pcs_pma_example.ip_user_files/sim_scripts/ten_gig_eth_pcs_pma/xsim/ten_gig_eth_pcs_pma.sh'
INFO: [exportsim-Tcl-25] Exported
'/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma_example/ten_gig_eth_pcs_pma_example.ip_user_files/sim_scripts/ten_gig_eth_pcs_pma/xsim/configure_gt.tcl'
INFO: [exportsim-Tcl-35] Exporting simulation files for "MODELSIM" (Mentor
Graphics ModelSim Simulator)...
INFO: [exportsim-Tcl-29] Script generated:
'/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma_example/ten_gig_eth_pcs_pma_example.ip_user_files/sim_scripts/ten_gig_eth_pcs_pma/modelsim/ten_gig_eth_pcs_pma.sh'
INFO: [exportsim-Tcl-25] Exported
'/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma_example/ten_gig_eth_pcs_pma_example.ip_user_files/sim_scripts/ten_gig_eth_pcs_pma/modelsim/configure_gt.tcl'
INFO: [exportsim-Tcl-35] Exporting simulation files for "QUESTA" (Mentor
Graphics Questa Advanced Simulator)...
INFO: [exportsim-Tcl-29] Script generated:
'/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma_example/ten_gig_eth_pcs_pma_example.ip_user_files/sim_scripts/ten_gig_eth_pcs_pma/questa/ten_gig_eth_pcs_pma.sh'
INFO: [exportsim-Tcl-25] Exported
'/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma_example/ten_gig_eth_pcs_pma_example.ip_user_files/sim_scripts/ten_gig_eth_pcs_pma/questa/configure_gt.tcl'
INFO: [exportsim-Tcl-35] Exporting simulation files for "IES" (Cadence Incisive
Enterprise Simulator)...
INFO: [exportsim-Tcl-29] Script generated:
'/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma_example/ten_gig_eth_pcs_pma_example.ip_user_files/sim_scripts/ten_gig_eth_pcs_pma/ies/ten_gig_eth_pcs_pma.sh'
INFO: [exportsim-Tcl-25] Exported
'/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma_example/ten_gig_eth_pcs_pma_example.ip_user_files/sim_scripts/ten_gig_eth_pcs_pma/ies/configure_gt.tcl'
INFO: [exportsim-Tcl-35] Exporting simulation files for "VCS" (Synopsys Verilog
Compiler Simulator)...
INFO: [exportsim-Tcl-29] Script generated:
'/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma_example/ten_gig_eth_pcs_pma_example.ip_user_files/sim_scripts/ten_gig_eth_pcs_pma/vcs/ten_gig_eth_pcs_pma.sh'
INFO: [exportsim-Tcl-25] Exported
'/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma_example/ten_gig_eth_pcs_pma_example.ip_user_files/sim_scripts/ten_gig_eth_pcs_pma/vcs/configure_gt.tcl'
# set dfile
"/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/oepdone.txt"
# set doneFile [open $dfile w]
# puts $doneFile "Open Example Project DONE"
# close $doneFile
# if { $returnCode != 0 } {
# error "Problems were encountered while executing the example design script,
please review the log files."
# }
INFO: [Common 17-206] Exiting Vivado at Mon May 15 10:59:44 2017...
open_example_project: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory
(MB): peak = 1052.266 ; gain = 0.000 ; free physical = 27081 ; free virtual =
44888
# close_project
# if { [get_msg_config -count -severity ERROR] == 0 } {
# # Write output cookie file
# set outfile [open "$xci_file.out" w]
# puts $outfile "This file was auto-generated by viv_generate_ip.tcl and
signifies that IP generation is done."
# close $outfile
# } else {
# exit 1
# }
INFO: [Common 17-206] Exiting Vivado at Mon May 15 10:59:45 2017...
BUILDER: Releasing IP location:
/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma
/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/Makefile.inc:41:
recipe for target
'/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci.out'
failed
make[1]: ***
[/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci.out]
Error 1
make[1]: Leaving directory
'/home/rauschen/Programmieren/UHD/uhd/fpga-src/usrp3/top/x300'
Makefile:97: recipe for target 'X300_RFNOC_HG' failed
make: *** [X300_RFNOC_HG] Error 2
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Message: 9
Date: Mon, 15 May 2017 09:21:44 -0400
From: olivani <[email protected]>
To: [email protected]
Subject: [USRP-users] E310 read write registers
Message-ID:
<cabq0vixw8cdhvczzntmfb_h3+qenr1hschnr7ep3dhxl9b4...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Hi ,
I am currently in the process of creating a user register and would want to
read and write to it.
I tried to invoke the function peek32 and poke 32 with the address to read
and write .
But I when I invoked the function peek32 and poke32 (whd::wb_iface) I got
the error"not implemented". Then I created an object to invoke peek32
of e300_global regs again I get the same error.
Is there a sample of how to read and write to registers.
Thanks and Regards,
Olivani Subbukutty
571-331-2481
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Message: 10
Date: Mon, 15 May 2017 10:23:14 -0400
From: [email protected]
To: Pol Henarejos <[email protected]>
Cc: [email protected]
Subject: Re: [USRP-users] USRP1 Support
Message-ID: <[email protected]>
Content-Type: text/plain; charset="us-ascii"
Are you perhaps running this inside a VM?
On 2017-05-15 09:30, Pol Henarejos via USRP-users wrote:
> Dear all,
>
> I am trying to get my old USRP1 running again but unfortunately I cannot
> receive properly. To test it I use benchmark_rate utility.
> Whilst transmission seems works properly (no underflows or complaints), the
> reception is not working. A lot of "D" appear, regardless the sampling rate.
>
> I am using UHD 3.9 LTS (but I am able to use my self-compilation from git
> source).
> The command I use is
>
> benchmark_rate --rx_rate 500e3
>
> and the output is
>
> -- Loading firmware image: C:\CTTC\UHD\share\uhd\images\usrp1_fw.ihx... done
> *** Warning! ***
> Benchmark results will be inaccurate on USRP1 due to insufficient features.
>
> Creating the usrp device with: ...
> -- Opening a USRP1 device...
> -- Loading FPGA image: C:\CTTC\UHD\share\uhd\images\usrp1_fpga.rbf... done
> -- Using FPGA clock rate of 64.000000MHz...
> Using Device: Single USRP:
> Device: USRP1 Device
> Mboard 0: USRP1
> RX Channel: 0
> RX DSP: 0
> RX Dboard: B
> RX Subdev: BasicRX (AB)
> TX Channel: 0
> TX DSP: 0
> TX Dboard: A
> TX Subdev: LFTX (AB)
>
> Setting device timestamp to 0...
> Testing receive rate 0.500000 Msps on 1 channels
>
DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD
DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD
> Benchmark rate summary:
> Num received samples: 5001216
> Num dropped samples: 19148
> Num overflows detected: 0
> Num transmitted samples: 0
> Num sequence errors: 0
> Num underflows detected: 0
> Num late commands: 0
> Num timeouts: 0
>
> Done!
>
> Any clue?
>
> Thank you.
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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Message: 11
Date: Mon, 15 May 2017 16:31:17 +0430
From: Ali Khanjani <[email protected]>
To: [email protected]
Subject: [USRP-users] Does a gnu_radio convert the block codes to the
HDL code?
Message-ID:
<CAEj=hctdvojxe2j+pysvjxpu-d_xhx9k4oxpeozlhb4qrvd...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
hi every body, I want to know that as we make blocks in GNU radio does it
self changes the blocks languages to the HDL and write on USRP board's FPGA?
because some one told me that all the claculations are in PC and the USRP
board is just for down converting.
please answer me clearly.
thanks for your attention.
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Message: 12
Date: Mon, 15 May 2017 16:44:02 +0200
From: Paolo Palana <[email protected]>
To: [email protected]
Subject: Re: [USRP-users] Does a gnu_radio convert the block codes to
the HDL code?
Message-ID: <[email protected]>
Content-Type: text/plain; charset="windows-1252"
As far as i know the answer is absolutely no!
If you want a new block on a USRP you have to write your own VHDL, or
Verilog code.
On 05/15/2017 02:01 PM, Ali Khanjani via USRP-users wrote:
> hi every body, I want to know that as we make blocks in GNU radio does
> it self changes the blocks languages to the HDL and write on USRP
> board's FPGA?
> because some one told me that all the claculations are in PC and the
> USRP board is just for down converting.
> please answer me clearly.
> thanks for your attention.
>
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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Message: 13
Date: Mon, 15 May 2017 10:45:36 -0400
From: [email protected]
To: Ali Khanjani <[email protected]>
Cc: [email protected]
Subject: Re: [USRP-users] Does a gnu_radio convert the block codes to
the HDL code?
Message-ID: <[email protected]>
Content-Type: text/plain; charset="us-ascii"
No. Gnu Radio is a *software* framework, for Software Defined Radio.
The blocks run natively on your PC--this is what makes it Software
Defined Radio.
What you *may* be confusing is that there's an Ettus FPGA-based system
called RFNoC, for both X3xx and E3xx that allows you to write FPGA-based
blocks that can be chained together using GRC, thus relieving some of
the compute burden from your host PC. But this isn't the general case
for Gnu Radio--most blocks execute locally on your computer.
For more information on RFNoC, see:
https://kb.ettus.com/Getting_Started_with_RFNoC_Development
On 2017-05-15 08:01, Ali Khanjani via USRP-users wrote:
> hi every body, I want to know that as we make blocks in GNU radio does it
> self changes the blocks languages to the HDL and write on USRP board's FPGA?
> because some one told me that all the claculations are in PC and the USRP
> board is just for down converting.
> please answer me clearly.
> thanks for your attention.
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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Message: 14
Date: Mon, 15 May 2017 10:26:53 -0500
From: Jonathon Pendlum <[email protected]>
To: Daniel Rauschen <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] - Problem with building custom RFNoC FPGA
image
Message-ID:
<cagdo0urfubxpcgyzojnw2-mpftibkoeefcpruqjcd0np-jm...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Hi Daniel,
It is almost certainly a license issue. Are you using a license file? With
Ubuntu 16.04, the naming scheme of the network interfaces has changed
causing some minor havoc with Vivado licensing. Basically, Vivado looks for
ethX interfaces which does not match up with systemd's network interface
naming.
You can try this to fix it (
https://askubuntu.com/questions/767786/changing-network-interfaces-name-ubuntu-16-04
):
- Create '70-persistent-net.rules' in '/etc/udev/rules.d/'
- Add the following line to the file (substitute xx:xx:xx:xx:xx:xx for the
MAC address of the Ethernet adapter): SUBSYSTEM=="net", ACTION=="add",
DRIVERS=="?*", ATTR{address}=="xx:xx:xx:xx:xx:xx", ATTR{dev_id}=="0x0",
ATTR{type}=="1", NAME="eth0"
If that doesn't work, you can also try Xilinx's workaround:
https://www.xilinx.com/support/answers/60510.html
Jonathon
On Mon, May 15, 2017 at 4:21 AM, Daniel Rauschen via USRP-users <
[email protected]> wrote:
> Hello usrp-users,
>
> I have a problems building a custom RFNoC FPGA image.
>
> I'm trying to run the following command "./uhd_image_builder.py window fft
> -d x300 -t X300_RFNOC_HG -m 5 --fill-with-fifos", with a full Vivado Design
> license for the 2015.4 version. The error message (see attachment) says
> there are license related problems, but I don't think this is the problem
> (see attachment for vlm output). Vivado is found and the script says
> "Environment successfully initialized.", are there any steps I'm missing?
>
> Any suggestions are highly welcome.
>
> The build system is:
>
> Kubuntu 16.04.1 LTS
> Kernel 4.4.0-57-lowlatency
> UHD UHD_4.0.0.rfnoc-devel-316-g24b98579
> Vivado 2015.4 Design version
> USRP x300
>
>
> With best regards,
>
>
> Daniel
>
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
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Subject: Digest Footer
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------------------------------
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