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Today's Topics:
1. Re: no product ID (john liu)
2. The version of SBX (liu Jong)
3. Re: x310 FPGA code (Jonathon Pendlum)
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Message: 1
Date: Mon, 5 Jun 2017 10:59:43 +0800
From: john liu <[email protected]>
To: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] no product ID
Message-ID:
<CAF6NnTL-9u0r_Xw8t1TYNK+f_RSUVYou=wasa-_kxi87txj...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Hi,all,
Any suggestion is welcome.
thank you.
On Fri, Jun 2, 2017 at 10:12 AM, john liu <[email protected]> wrote:
> Hi,all,
> We have a usrp b210,and with command uhd_find_devices,information as below:
>
> uhd_find_devices
> linux; GNU C++ version 4.8.4; Boost_105400; UHD_003.010.001.HEAD-0-
> g945fd653
>
> --------------------------------------------------
> -- UHD Device 0
> --------------------------------------------------
> Device Address:
> type: b200
> name:
> serial:
> product: B2??
>
> Then we tried ./usrp_burn_mb_eeprom --read-all:
>
> /usr/local/lib/uhd/utils$ ./usrp_burn_mb_eeprom --read-alllinux; GNU C++
> version 4.8.4; Boost_105400; UHD_003.010.001.HEAD-0-g945fd653
>
> Creating USRP device from address:
> Error: RuntimeError: B200: Missing product ID on EEPROM.
>
> As the result showed,no product ID on EEPROM.
> How could we solved the problem?
>
> thank you.
>
> best regards
> John
>
>
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Message: 2
Date: Mon, 5 Jun 2017 11:02:56 +0800
From: liu Jong <[email protected]>
To: "[email protected]" <[email protected]>
Subject: [USRP-users] The version of SBX
Message-ID:
<CAEui2n0=juyLc+05MwQbYaAKcbdKUOBT=0hmmtxbkz2a2jw...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
The version SBX40 we purchased is 153933B-11L, but the schematic version
downloaded from the site(http://files.ettus.com/schematics/sbx/) is
153934B-01.
Is there a SBX40 schematic diagram that of the version is 153933B-11L?
thank you.
best regards
Jon
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Message: 3
Date: Mon, 5 Jun 2017 00:50:33 -0400
From: Jonathon Pendlum <[email protected]>
To: liu Jong <[email protected]>
Cc: Lihua Ren <[email protected]>, "[email protected]"
<[email protected]>
Subject: Re: [USRP-users] x310 FPGA code
Message-ID:
<cagdo0usvwzeav3f15741drhntg97xy6qbtcgkw+7ve_pzjo...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Hi John,
Try looking into resampling filter implementations.
Jonathon
On Thu, Jun 1, 2017 at 9:26 PM, liu Jong <[email protected]> wrote:
> Hi,Jonathon,
> Can we used Interpolation or decimation achieved this in FPGA
> with verilog?
>
> thank you.
> best regards
> John
>
> 2017-05-19 2:03 GMT+08:00 Jonathon Pendlum via USRP-users <
> [email protected]>:
>
>> HI Lihua,
>>
>> Generating a 114.688 MHz clock is going to be very difficult. For
>> instance, the closest you'll achieve with a MMCM using bus_clk is 115.385
>> MHz. Can you explain exactly why you need a 114.688 MHz clock and what you
>> are trying to achieve? That way, we might be able to come up with an easier
>> approach.
>>
>>
>>
>> Jonathon
>>
>> On Tue, May 16, 2017 at 9:02 PM, Lihua Ren via USRP-users <
>> [email protected]> wrote:
>>
>>> hi?all
>>> I met the clock problem, hope to get your help.for instance ?in
>>> noc_block_xx.v?"ce_clk" signal through the DCM(digital clock manager)
>>> ip core output 114.688MHz, but there are timing error.
>>>
>>> 114.688 MHz is determined by the baseband processing algorithm in my
>>> RFnoc block,and 114.688 MHz is main clock in my FPGA code.( *114.688
>>> MHz** is not a sampling rate*)
>>>
>>> Importantly?in X310 FPGA code ?all the modules' the main clock is
>>> 200MHz, but my block need is 114.688MHz, which can be achieved?
>>>
>>>
>>>
>>>
>>>
>>>
>>> _______________________________________________
>>> USRP-users mailing list
>>> [email protected]
>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>>
>>>
>>
>> _______________________________________________
>> USRP-users mailing list
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>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>
>>
>
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