Hello All, I was wondering if anybody had any tips about adding a yellow block (ADC) that has and AXI4-Lite interface to a platform design?
Is it as easy as adding something like (taken from red_pitaya_10.yaml): mmbus_architecture: AXI4-Lite mmbus_base_address: 0x40000000 # How to address each 32-bit (i.e. 4 indicates byte-addressable) mmbus_address_alignment: 4 To the platform file, and something like lines 20-57 from https://github.com/casper-astro/mlib_devel/blob/master/jasper_library/yellow_blocks/sw_reg.py to the Yellow Block's py file? -LH -- You received this message because you are subscribed to the Google Groups "casper@lists.berkeley.edu" group. To unsubscribe from this group and stop receiving emails from it, send an email to casper+unsubscr...@lists.berkeley.edu. To view this discussion on the web visit https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/7b0579d8cfd23332ece5f06401d325c5.squirrel%40webmail.gb.nrao.edu.
