Thank you, Rich!

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From: Richard Nute <ri...@bendbroadband.com>
Sent: Friday, April 26, 2024 6:54 PM
To: EMC-PSTC@LISTSERV.IEEE.ORG
Subject: Re: [PSES] Couple of loosely related safety questions


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Hi Brian:

You should attend the IEEE PSES Symposium in Chicago next week to get the 
answers to these questions from experts.  Lots of experts in clearance and 
creepage will be there and will be happy to provide you with answers!

Best regards,
Rich


From: Brian Gregory [mailto:brian_greg...@netzero.net]
Sent: Friday, April 26, 2024 4:12 PM
To: EMC-PSTC@LISTSERV.IEEE.ORG<mailto:EMC-PSTC@LISTSERV.IEEE.ORG>
Subject: [PSES] Couple of loosely related safety questions


1.  Clearances for US Safety:

I'd cite the relevant standards, but they are so alike (identical Clearance 
tables), and so alike to UL 508, I'll defer.  Here's the question:

When citing clearance spacing from "uninsulated live components"  does one 
measure from the edge of a PCB to the enclosure well, or only from the live 
components, like a pad, or the bottom pin of a thru-hole cap?
1a.  what sort of passivation or RTV could make those live components not 
"uninsulated"?

2.  Slots to increase creepage for high-voltage components

A FET that's rated for say 600V does not have to follow PCB-creepage rules for 
600V, is clearly stated places like UL 1741, §26.1.1 exception #8.  For other 
components, like say 1000V caps in 0805 packages or FET driver chips the 
requirements aren't as clear.  Is a slot needed to maintain creepage or not if 
the component is properly rated?  It does appear from a TI support page for 
dual-bridge converters, that slots are recommended in order to prevent 
contamination that may compromise the components isolation performance.

My gut says:  no, slots are not needed between component terminals on a PCB, 
but could be recommended for sensitive parts, like FET drivers.

Thoughts?

Colorado Brian

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