This series provides support for the Ventana VT1 (a 4-way superscalar rv64gc_zba_zbb_zbc_zbs_zifenci_xventanacondops core) including support for the supported instruction fusion patterns.
This includes the addition of the fusion-aware scheduling infrastructure for RISC-V and implements idiom recognition for the fusion patterns supported by VT1. Note that we don't signal support for XVentanaCondOps at this point, as the XVentanaCondOps support is in-flight separately. Changing the defaults for VT1 can happen late in the cycle, so no need to link the two different changesets. Changes in v2: - Rebased and changed over to .rst-based documentation - Updated to catch more fusion cases - Signals support for Zifencei Philipp Tomsich (2): RISC-V: Add basic support for the Ventana-VT1 core RISC-V: Add instruction fusion (for ventana-vt1) gcc/config/riscv/riscv-cores.def | 3 + gcc/config/riscv/riscv-opts.h | 2 +- gcc/config/riscv/riscv.cc | 233 ++++++++++++++++++ .../risc-v-options.rst | 5 +- 4 files changed, 240 insertions(+), 3 deletions(-) -- 2.34.1
