The Ventana-VT1 core is compatible with rv64gc, Zb[abcs], Zifenci and
XVentanaCondOps.
This introduces a placeholder -mcpu=ventana-vt1, so tooling and
scripts don't need to change once full support (pipeline, tuning,
etc.) will become public later.
gcc/ChangeLog:
* config/riscv/riscv-cores.def (RISCV_TUNE): Add ventana-vt1.
(RISCV_CORE): Ditto.
* config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): Ditto.
* config/riscv/riscv.cc: Add tune_info for ventana-vt1.
* config/riscv/riscv.md: Add ventana-vt1.
*
doc/gcc/gcc-command-options/machine-dependent-options/risc-v-options.rst:
Document -mcpu= and -mtune with ventana-vt1.
Signed-off-by: Philipp Tomsich <philipp.toms...@vrull.eu>
---
Changes in v2:
- Rebased and changed over to .rst-based documentation
- Updated to catch more fusion cases
- Signals support for Zifencei
- Rebase to master, adjusting for the new way to define cores.
- Change documentation to the new way (.rst)
- Include Zifencei in the VT1 definition.
gcc/config/riscv/riscv-cores.def | 3 +++
gcc/config/riscv/riscv-opts.h | 2 +-
gcc/config/riscv/riscv.cc | 14 ++++++++++++++
.../machine-dependent-options/risc-v-options.rst | 5 +++--
4 files changed, 21 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index 31ad34682c5..aef1e92ae24 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -38,6 +38,7 @@ RISCV_TUNE("sifive-3-series", generic, rocket_tune_info)
RISCV_TUNE("sifive-5-series", generic, rocket_tune_info)
RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info)
RISCV_TUNE("thead-c906", generic, thead_c906_tune_info)
+RISCV_TUNE("ventana-vt1", generic, ventana_vt1_tune_info)
RISCV_TUNE("size", generic, optimize_size_tune_info)
#undef RISCV_TUNE
@@ -73,4 +74,6 @@ RISCV_CORE("sifive-s76", "rv64imafdc", "sifive-7-series")
RISCV_CORE("sifive-u54", "rv64imafdc", "sifive-5-series")
RISCV_CORE("sifive-u74", "rv64imafdc", "sifive-7-series")
+RISCV_CORE("ventana-vt1", "rv64imafdc_zba_zbb_zbc_zbs_zifencei",
"ventana-vt1")
+
#undef RISCV_CORE
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 84c987626bc..7962dbe5018 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -52,7 +52,7 @@ extern enum riscv_isa_spec_class riscv_isa_spec;
/* Keep this list in sync with define_attr "tune" in riscv.md. */
enum riscv_microarchitecture_type {
generic,
- sifive_7
+ sifive_7,
};
extern enum riscv_microarchitecture_type riscv_microarchitecture;
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index c04e5db21df..31d651f8744 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -360,6 +360,20 @@ static const struct riscv_tune_param
optimize_size_tune_info = {
false, /* slow_unaligned_access */
};
+/* Costs to use when optimizing for Ventana Micro VT1. */
+static const struct riscv_tune_param ventana_vt1_tune_info = {
+ {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */
+ {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */
+ {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */
+ {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */
+ {COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */
+ 4, /* issue_rate */
+ 4, /* branch_cost */
+ 5, /* memory_cost */
+ 8, /* fmv_cost */
+ false, /* slow_unaligned_access */
+};
+
static tree riscv_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
static tree riscv_handle_type_attribute (tree *, tree, tree, int, bool *);
diff --git
a/gcc/doc/gcc/gcc-command-options/machine-dependent-options/risc-v-options.rst
b/gcc/doc/gcc/gcc-command-options/machine-dependent-options/risc-v-options.rst
index 2b5167b56b2..5a0345ae2b3 100644
---
a/gcc/doc/gcc/gcc-command-options/machine-dependent-options/risc-v-options.rst
+++
b/gcc/doc/gcc/gcc-command-options/machine-dependent-options/risc-v-options.rst
@@ -95,14 +95,15 @@ These command-line options are defined for RISC-V targets:
Permissible values for this option are: :samp:`sifive-e20`,
:samp:`sifive-e21`,
:samp:`sifive-e24`, :samp:`sifive-e31`, :samp:`sifive-e34`,
:samp:`sifive-e76`,
:samp:`sifive-s21`, :samp:`sifive-s51`, :samp:`sifive-s54`,
:samp:`sifive-s76`,
- :samp:`sifive-u54`, and :samp:`sifive-u74`.
+ :samp:`sifive-u54`, :samp:`sifive-u74`, and :samp:`ventana-vt1`.
.. option:: -mtune={processor-string}
Optimize the output for the given processor, specified by microarchitecture
or
particular CPU name. Permissible values for this option are: :samp:`rocket`,
:samp:`sifive-3-series`, :samp:`sifive-5-series`, :samp:`sifive-7-series`,
- :samp:`thead-c906`, :samp:`size`, and all valid options for :option:`-mcpu=`.
+ :samp:`thead-c906`, :samp:`ventana-vt1`, and :samp:`size`, and all valid
+ options for :option:`-mcpu=`.
When :option:`-mtune=` is not specified, use the setting from
:option:`-mcpu`,
the default is :samp:`rocket` if both are not specified.
--
2.34.1
