[PATCH v2 7/8] RISC-V: Ventana-VT1 supports XVentanaCondOps

[Philipp Tomsich]

gcc/ChangeLog:

        * config/riscv/riscv-cores.def (RISCV_CORE): Update the
        Ventana-VT1 definition to include the xventanacondops
        extension.

Signed-off-by: Philipp Tomsich <philipp.toms...@vrull.eu>
---

Changes in v2:
- New in v2.

 gcc/config/riscv/riscv-cores.def | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index aef1e92ae24..9e38e9dc72e 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -74,6 +74,6 @@ RISCV_CORE("sifive-s76",      "rv64imafdc", "sifive-7-series")
 RISCV_CORE("sifive-u54",      "rv64imafdc", "sifive-5-series")
 RISCV_CORE("sifive-u74",      "rv64imafdc", "sifive-7-series")
 
-RISCV_CORE("ventana-vt1",     "rv64imafdc_zba_zbb_zbc_zbs_zifencei",   
"ventana-vt1")
+RISCV_CORE("ventana-vt1",     
"rv64imafdc_zba_zbb_zbc_zbs_zifencei_xventanacondops",   "ventana-vt1")
 
 #undef RISCV_CORE
-- 
2.34.1