Commited, thanks juzhe.
--------------
Li Xu
>OK.
>
>
>
>juzhe.zh...@rivai.ai
>
>From: Li Xu
>Date: 2023-10-07 11:18
>To: gcc-patches
>CC: kito.cheng; palmer; juzhe.zhong; xuli
>Subject: [PATCH] RISC-V: Fix scan-assembler-times of RVV test case
>From: xuli <xu...@eswincomputing.com>
>
>gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c: Adjust assembler
>times.
> * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c: Ditto.
>---
>.../gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c | 10 +++++-----
>.../gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c | 10 +++++-----
>2 files changed, 10 insertions(+), 10 deletions(-)
>
>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c
>b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c
>index c566f8a4751..2ec9487a6c6 100644
>--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c
>+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c
>@@ -88,8 +88,8 @@ void f (void * restrict in, void * restrict out, int n, int
>cond)
> }
>}
>-/* { dg-final { scan-assembler-times
>{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 3 { target {
>no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
>"-funroll-loops" no-opts "-g" } } } } */
>-/* { dg-final { scan-assembler-times
>{vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 { target {
>no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
>"-funroll-loops" no-opts "-g" } } } } */
>-/* { dg-final { scan-assembler-times
>{vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target {
>no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
>"-funroll-loops" no-opts "-g" } } } } */
>-/* { dg-final { scan-assembler-times
>{vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 2 { target {
>no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
>"-funroll-loops" no-opts "-g" } } } } */
>-/* { dg-final { scan-assembler-times {vsetvli} 10 { target { no-opts "-O0"
>no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
>"-g" } } } } */
>+/* { dg-final { scan-assembler-times
>{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 10 { target {
>no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
>"-funroll-loops" no-opts "-g" } } } } */
>+/* { dg-final { scan-assembler-not
>{vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} { target {
>no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
>"-funroll-loops" no-opts "-g" } } } } */
>+/* { dg-final { scan-assembler-not
>{vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} { target {
>no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
>"-funroll-loops" no-opts "-g" } } } } */
>+/* { dg-final { scan-assembler-not
>{vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} { target {
>no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
>"-funroll-loops" no-opts "-g" } } } } */
>+/* { dg-final { scan-assembler-times {vsetvli} 19 { target { no-opts "-O0"
>no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
>"-g" } } } } */
>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c
>b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c
>index d0e75258188..bcafce36895 100644
>--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c
>+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c
>@@ -80,8 +80,8 @@ void f (void * restrict in, void * restrict out, int n, int
>cond)
> }
>}
>-/* { dg-final { scan-assembler-times
>{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 3 { target {
>no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
>"-funroll-loops" no-opts "-g" } } } } */
>-/* { dg-final { scan-assembler-times
>{vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 { target {
>no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
>"-funroll-loops" no-opts "-g" } } } } */
>-/* { dg-final { scan-assembler-times
>{vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 3 { target {
>no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
>"-funroll-loops" no-opts "-g" } } } } */
>-/* { dg-final { scan-assembler-times
>{vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 { target {
>no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
>"-funroll-loops" no-opts "-g" } } } } */
>-/* { dg-final { scan-assembler-times {vsetvli} 9 { target { no-opts "-O0"
>no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
>"-g" } } } } */
>+/* { dg-final { scan-assembler-times
>{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 9 { target {
>no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
>"-funroll-loops" no-opts "-g" } } } } */
>+/* { dg-final { scan-assembler-not
>{vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} { target {
>no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
>"-funroll-loops" no-opts "-g" } } } } */
>+/* { dg-final { scan-assembler-not
>{vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} { target {
>no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
>"-funroll-loops" no-opts "-g" } } } } */
>+/* { dg-final { scan-assembler-not
>{vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} { target {
>no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
>"-funroll-loops" no-opts "-g" } } } } */
>+/* { dg-final { scan-assembler-times {vsetvli} 17 { target { no-opts "-O0"
>no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
>"-g" } } } } */
>--
>2.17.1
>
>
