llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-risc-v Author: Pengcheng Wang (wangpc-pp) <details> <summary>Changes</summary> So we can only mantain one place. --- Full diff: https://github.com/llvm/llvm-project/pull/90187.diff 3 Files Affected: - (modified) llvm/lib/TargetParser/RISCVISAInfo.cpp (+2-35) - (modified) llvm/test/TableGen/riscv-target-def.td (+19) - (modified) llvm/utils/TableGen/RISCVTargetDefEmitter.cpp (+29-11) ``````````diff diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp b/llvm/lib/TargetParser/RISCVISAInfo.cpp index ea0b56b9a1339b..d786f190d9ab6c 100644 --- a/llvm/lib/TargetParser/RISCVISAInfo.cpp +++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp @@ -50,41 +50,8 @@ static const char *RISCVGImplications[] = { #define GET_SUPPORTED_EXTENSIONS #include "llvm/TargetParser/RISCVTargetParserDef.inc" -static constexpr RISCVProfile SupportedProfiles[] = { - {"rvi20u32", "rv32i"}, - {"rvi20u64", "rv64i"}, - {"rva20u64", "rv64imafdc_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_za128rs"}, - {"rva20s64", "rv64imafdc_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zifencei_" - "za128rs_ssccptr_sstvala_sstvecd_svade_svbare"}, - {"rva22u64", - "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_" - "zicntr_zihintpause_zihpm_za64rs_zfhmin_zba_zbb_zbs_zkt"}, - {"rva22s64", - "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_" - "zicntr_zifencei_zihintpause_zihpm_za64rs_zfhmin_zba_zbb_zbs_zkt_ssccptr_" - "sscounterenw_sstvala_sstvecd_svade_svbare_svinval_svpbmt"}, - {"rva23u64", - "rv64imafdcv_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_" - "zicntr_zicond_zihintntl_zihintpause_zihpm_zimop_za64rs_zawrs_zfa_zfhmin_" - "zcb_zcmop_zba_zbb_zbs_zkt_zvbb_zvfhmin_zvkt"}, - {"rva23s64", - "rv64imafdcvh_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_" - "zicntr_zicond_zifencei_zihintntl_zihintpause_zihpm_zimop_za64rs_zawrs_" - "zfa_zfhmin_zcb_zcmop_zba_zbb_zbs_zkt_zvbb_zvfhmin_zvkt_shcounterenw_" - "shgatpa_shtvala_shvsatpa_shvstvala_shvstvecd_ssccptr_sscofpmf_" - "sscounterenw_ssnpm0p8_ssstateen_sstc_sstvala_sstvecd_ssu64xl_svade_" - "svbare_svinval_svnapot_svpbmt"}, - {"rvb23u64", "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_" - "zicclsm_ziccrse_zicntr_zicond_zihintntl_zihintpause_zihpm_" - "zimop_za64rs_zawrs_zfa_zcb_zcmop_zba_zbb_zbs_zkt"}, - {"rvb23s64", - "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_" - "zicntr_zicond_zifencei_zihintntl_zihintpause_zihpm_zimop_za64rs_zawrs_" - "zfa_zcb_zcmop_zba_zbb_zbs_zkt_ssccptr_sscofpmf_sscounterenw_sstc_sstvala_" - "sstvecd_ssu64xl_svade_svbare_svinval_svnapot_svpbmt"}, - {"rvm23u32", "rv32im_zicbop_zicond_zicsr_zihintntl_zihintpause_zimop_zca_" - "zcb_zce_zcmop_zcmp_zcmt_zba_zbb_zbs"}, -}; +#define GET_SUPPORTED_PROFILES +#include "llvm/TargetParser/RISCVTargetParserDef.inc" static void verifyTables() { #ifndef NDEBUG diff --git a/llvm/test/TableGen/riscv-target-def.td b/llvm/test/TableGen/riscv-target-def.td index 175b68f9f8bad7..afc32086adf99d 100644 --- a/llvm/test/TableGen/riscv-target-def.td +++ b/llvm/test/TableGen/riscv-target-def.td @@ -51,6 +51,14 @@ def Feature64Bit def FeatureDummy : SubtargetFeature<"dummy", "Dummy", "true", "Dummy">; +class RISCVProfile<string name, list<SubtargetFeature> features> + : SubtargetFeature<name, "RISCVProfile", NAME, + "RISC-V " # name # " profile", features>; + +def RVI20U32 : RISCVProfile<"rvi20u32", [Feature32Bit, FeatureStdExtI]>; +def RVI20U64 : RISCVProfile<"rvi20u64", [Feature64Bit, FeatureStdExtI]>; +def ProfileDummy : RISCVProfile<"dummy", [Feature64Bit, FeatureStdExtI, FeatureStdExtZidummy]>; + class RISCVProcessorModel<string n, SchedMachineModel m, list<SubtargetFeature> f, @@ -123,6 +131,17 @@ def ROCKET : RISCVTuneProcessorModel<"rocket", // CHECK: #endif // GET_IMPLIED_EXTENSIONS +// CHECK: #ifdef GET_SUPPORTED_PROFILES +// CHECK-NEXT: #undef GET_SUPPORTED_PROFILES + +// CHECK: static constexpr RISCVProfile SupportedProfiles[] = { +// CHECK-NEXT: {"dummy","rv64i2p1_zidummy0p1"}, +// CHECK-NEXT: {"rvi20u32","rv32i2p1"}, +// CHECK-NEXT: {"rvi20u64","rv64i2p1"}, +// CHECK-NEXT: }; + +// CHECK: #endif // GET_SUPPORTED_PROFILES + // CHECK: #ifndef PROC // CHECK-NEXT: #define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_UNALIGNED_ACCESS) // CHECK-NEXT: #endif diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp index 4580a0ab12669c..8f9a2513184220 100644 --- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp +++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp @@ -111,14 +111,14 @@ static void emitRISCVExtensions(RecordKeeper &Records, raw_ostream &OS) { // // This is almost the same as RISCVFeatures::parseFeatureBits, except that we // get feature name from feature records instead of feature bits. -static void printMArch(raw_ostream &OS, const Record &Rec) { +static void printMArch(raw_ostream &OS, const std::vector<Record *> &Features) { std::map<std::string, RISCVISAUtils::ExtensionVersion, RISCVISAUtils::ExtensionComparator> Extensions; unsigned XLen = 0; // Convert features to FeatureVector. - for (auto *Feature : Rec.getValueAsListOfDefs("Features")) { + for (auto *Feature : Features) { StringRef FeatureName = getExtensionName(Feature); if (Feature->isSubClassOf("RISCVExtension")) { unsigned Major = Feature->getValueAsInt("MajorVersion"); @@ -142,6 +142,23 @@ static void printMArch(raw_ostream &OS, const Record &Rec) { OS << LS << Ext.first << Ext.second.Major << 'p' << Ext.second.Minor; } +static void emitRISCVProfiles(RecordKeeper &Records, raw_ostream &OS) { + OS << "#ifdef GET_SUPPORTED_PROFILES\n"; + OS << "#undef GET_SUPPORTED_PROFILES\n\n"; + + OS << "static constexpr RISCVProfile SupportedProfiles[] = {\n"; + + for (const Record *Rec : Records.getAllDerivedDefinitions("RISCVProfile")) { + OS.indent(4) << "{\"" << Rec->getValueAsString("Name") << "\",\""; + printMArch(OS, Rec->getValueAsListOfDefs("Implies")); + OS << "\"},\n"; + } + + OS << "};\n\n"; + + OS << "#endif // GET_SUPPORTED_PROFILES\n\n"; +} + static void emitRISCVProcs(RecordKeeper &RK, raw_ostream &OS) { OS << "#ifndef PROC\n" << "#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_UNALIGNED_ACCESS)\n" @@ -149,15 +166,15 @@ static void emitRISCVProcs(RecordKeeper &RK, raw_ostream &OS) { // Iterate on all definition records. for (const Record *Rec : RK.getAllDerivedDefinitions("RISCVProcessorModel")) { - bool FastScalarUnalignedAccess = - any_of(Rec->getValueAsListOfDefs("Features"), [&](auto &Feature) { - return Feature->getValueAsString("Name") == "unaligned-scalar-mem"; - }); + const std::vector<Record *> &Features = + Rec->getValueAsListOfDefs("Features"); + bool FastScalarUnalignedAccess = any_of(Features, [&](auto &Feature) { + return Feature->getValueAsString("Name") == "unaligned-scalar-mem"; + }); - bool FastVectorUnalignedAccess = - any_of(Rec->getValueAsListOfDefs("Features"), [&](auto &Feature) { - return Feature->getValueAsString("Name") == "unaligned-vector-mem"; - }); + bool FastVectorUnalignedAccess = any_of(Features, [&](auto &Feature) { + return Feature->getValueAsString("Name") == "unaligned-vector-mem"; + }); bool FastUnalignedAccess = FastScalarUnalignedAccess && FastVectorUnalignedAccess; @@ -169,7 +186,7 @@ static void emitRISCVProcs(RecordKeeper &RK, raw_ostream &OS) { // Compute MArch from features if we don't specify it. if (MArch.empty()) - printMArch(OS, *Rec); + printMArch(OS, Features); else OS << MArch; OS << "\"}, " << FastUnalignedAccess << ")\n"; @@ -191,6 +208,7 @@ static void emitRISCVProcs(RecordKeeper &RK, raw_ostream &OS) { static void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS) { emitRISCVExtensions(RK, OS); + emitRISCVProfiles(RK, OS); emitRISCVProcs(RK, OS); } `````````` </details> https://github.com/llvm/llvm-project/pull/90187 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits