[PATCH] drm/amd/display: Drop pixel_clock_mhz
The pixel_clock_mhz property is populated in amdgpu_dm when Freesync is setup,
but it is not used anywhere in amdgpu_dm. Remove the dead code.
Cc: chiahsuan.ch...@amd.com
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 -
2 files changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index f80213b7e9f7..3054bf79fc99 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -11274,7 +11274,6 @@ void amdgpu_dm_update_freesync_caps(struct
drm_connector *connector,
amdgpu_dm_connector->min_vfreq = 0;
amdgpu_dm_connector->max_vfreq = 0;
- amdgpu_dm_connector->pixel_clock_mhz = 0;
connector->display_info.monitor_range.min_vfreq = 0;
connector->display_info.monitor_range.max_vfreq = 0;
freesync_capable = false;
@@ -11338,8 +11337,6 @@ void amdgpu_dm_update_freesync_caps(struct
drm_connector *connector,
connector->display_info.monitor_range.min_vfreq;
amdgpu_dm_connector->max_vfreq =
connector->display_info.monitor_range.max_vfreq;
- amdgpu_dm_connector->pixel_clock_mhz =
- range->pixel_clock_mhz * 10;
break;
}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 09519b7abf67..67647bb5999b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -678,7 +678,6 @@ struct amdgpu_dm_connector {
* value is set to zero when there is no FreeSync support.
*/
int max_vfreq ;
- int pixel_clock_mhz;
/* Audio instance - protected by audio_lock. */
int audio_inst;
--
2.43.0
[PATCH] drm/amdgpu: enable unmapped doorbell handling basic mode on mes 12
This reverts commit 9606c08e178f953d22e50b05c64b4b1a48051f3e.
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c| 14 ++
drivers/gpu/drm/amd/include/mes_v12_api_def.h | 3 ++-
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
index 76db85157bf9..4f123d88aa3a 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
@@ -525,7 +525,14 @@ static int mes_v12_0_set_hw_resources(struct amdgpu_mes
*mes)
mes_set_hw_res_pkt.disable_mes_log = 1;
mes_set_hw_res_pkt.use_different_vmid_compute = 1;
mes_set_hw_res_pkt.enable_reg_active_poll = 1;
+
+ /*
+* Keep oversubscribe timer for sdma . When we have unmapped doorbell
+* handling support, other queue will not use the oversubscribe timer.
+* handling mode - 0: disabled; 1: basic version; 2: basic+ version
+*/
mes_set_hw_res_pkt.oversubscription_timer = 50;
+ mes_set_hw_res_pkt.unmapped_doorbell_handling = 1;
mes_set_hw_res_pkt.enable_mes_event_int_logging = 0;
mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr =
mes->event_log_gpu_addr;
@@ -972,6 +979,13 @@ static int mes_v12_0_mqd_init(struct amdgpu_ring *ring)
mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT;
mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT;
+ /*
+* Set CP_HQD_GFX_CONTROL.DB_UPDATED_MSG_EN[15] to enable unmapped
+* doorbell handling. This is a reserved CP internal register can
+* not be accesss by others
+*/
+ mqd->reserved_184 = BIT(15);
+
return 0;
}
diff --git a/drivers/gpu/drm/amd/include/mes_v12_api_def.h
b/drivers/gpu/drm/amd/include/mes_v12_api_def.h
index e3211daa9c2e..ffd67c6ed9b3 100644
--- a/drivers/gpu/drm/amd/include/mes_v12_api_def.h
+++ b/drivers/gpu/drm/amd/include/mes_v12_api_def.h
@@ -239,7 +239,8 @@ union MESAPI_SET_HW_RESOURCES {
uint32_t send_write_data : 1;
uint32_t os_tdr_timeout_override : 1;
uint32_t use_rs64mem_for_proc_gang_ctx : 1;
- uint32_t reserved : 17;
+ uint32_t unmapped_doorbell_handling: 2;
+ uint32_t reserved : 15;
};
uint32_t uint32_all;
};
--
2.34.1
[pull] amdgpu, amdkfd drm-fixes-6.9
Hi Dave, Sima, Fixes for 6.9. The following changes since commit dd5a440a31fae6e459c0d627162825505361: Linux 6.9-rc7 (2024-05-05 14:06:01 -0700) are available in the Git repository at: https://gitlab.freedesktop.org/agd5f/linux.git tags/amd-drm-fixes-6.9-2024-05-08 for you to fetch changes up to 3d09248a06d285397e7b873415505d299202e1c6: drm/amdgpu: Fix comparison in amdgpu_res_cpu_visible (2024-05-08 18:47:52 -0400) amd-drm-fixes-6.9-2024-05-08: amdgpu: - DCN 3.5 fix - MST DSC fixes - S0i3 fix - S4 fix - Warning fix - HDP MMIO mapping fix - Fix a regression in visible vram handling amdkfd: - Spatial partition fix Agustin Gutierrez (2): drm/amd/display: Fix DSC-re-computing drm/amd/display: MST DSC check for older devices Alex Deucher (1): drm/amdkfd: don't allow mapping the MMIO HDP page with large pages Lijo Lazar (2): Revert "drm/amdkfd: Add partition id field to location_id" drm/amd/amdxcp: Fix warnings Mario Limonciello (1): dm/amd/pm: Fix problems with reboot/shutdown for some SMU 13.0.4/13.0.11 users Michel Dänzer (1): drm/amdgpu: Fix comparison in amdgpu_res_cpu_visible Nicholas Kazlauskas (1): drm/amd/display: Fix idle optimization checks for multi-display and dual eDP Nicholas Susanto (1): drm/amd/display: Enable urgent latency adjustments for DCN35 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c| 2 +- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 7 +++-- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 5 ++-- drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c| 2 +- .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c| 16 +-- .../gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c | 4 +-- .../drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c| 33 ++ .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c | 2 +- 8 files changed, 52 insertions(+), 19 deletions(-)
[PATCH v2] drm/amd/display: Enable colorspace property for MST connectors
MST colorspace property support was disabled due to a series of warnings
that came up when the device was plugged in since the properties weren't
made at device creation. Create the properties in advance instead.
Suggested-by: Ville Syrjälä
Fixes: 69a959610229 ("drm/amd/display: Temporary Disable MST DP Colorspace
Property").
Reported-and-tested-by: Tyler Schneider
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3353
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 941e96f100f4..12b036d511d0 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -613,6 +613,9 @@ dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
>base,
dev->mode_config.tile_property,
0);
+ connector->colorspace_property = master->base.colorspace_property;
+ if (connector->colorspace_property)
+ drm_connector_attach_colorspace_property(connector);
drm_connector_set_path_property(connector, pathprop);
--
2.43.0
Re: [PATCH v2 01/12] drm/amdgpu, drm/radeon: Make I2C terminology more inclusive
On Wed, May 8, 2024 at 4:12 PM Easwar Hariharan wrote: > > On 5/8/2024 7:53 AM, Alex Deucher wrote: > > On Tue, May 7, 2024 at 2:32 PM Easwar Hariharan > > wrote: > >> > >> On 5/3/2024 11:13 AM, Easwar Hariharan wrote: > >>> I2C v7, SMBus 3.2, and I3C 1.1.1 specifications have replaced > >>> "master/slave" > >>> with more appropriate terms. Inspired by and following on to Wolfram's > >>> series to fix drivers/i2c/[1], fix the terminology for users of > >>> I2C_ALGOBIT bitbanging interface, now that the approved verbiage exists > >>> in the specification. > >>> > >>> Compile tested, no functionality changes intended > >>> > >>> [1]: > >>> https://lore.kernel.org/all/20240322132619.6389-1-wsa+rene...@sang-engineering.com/ > >>> > >>> Signed-off-by: Easwar Hariharan > >>> --- > >>> .../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 8 +++--- > >>> drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c | 10 +++ > >>> drivers/gpu/drm/amd/amdgpu/atombios_i2c.c | 8 +++--- > >>> drivers/gpu/drm/amd/amdgpu/atombios_i2c.h | 2 +- > >>> drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c| 20 ++--- > >>> .../gpu/drm/amd/display/dc/bios/bios_parser.c | 2 +- > >>> .../drm/amd/display/dc/bios/bios_parser2.c| 2 +- > >>> .../drm/amd/display/dc/core/dc_link_exports.c | 4 +-- > >>> drivers/gpu/drm/amd/display/dc/dc.h | 2 +- > >>> drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c | 4 +-- > >>> .../display/include/grph_object_ctrl_defs.h | 2 +- > >>> drivers/gpu/drm/amd/include/atombios.h| 2 +- > >>> drivers/gpu/drm/amd/include/atomfirmware.h| 26 - > >>> .../powerplay/hwmgr/vega20_processpptables.c | 4 +-- > >>> .../amd/pm/powerplay/inc/smu11_driver_if.h| 2 +- > >>> .../inc/pmfw_if/smu11_driver_if_arcturus.h| 2 +- > >>> .../inc/pmfw_if/smu11_driver_if_navi10.h | 2 +- > >>> .../pmfw_if/smu11_driver_if_sienna_cichlid.h | 2 +- > >>> .../inc/pmfw_if/smu13_driver_if_aldebaran.h | 2 +- > >>> .../inc/pmfw_if/smu13_driver_if_v13_0_0.h | 2 +- > >>> .../inc/pmfw_if/smu13_driver_if_v13_0_7.h | 2 +- > >>> .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 4 +-- > >>> .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 8 +++--- > >>> drivers/gpu/drm/radeon/atombios.h | 16 +-- > >>> drivers/gpu/drm/radeon/atombios_i2c.c | 4 +-- > >>> drivers/gpu/drm/radeon/radeon_combios.c | 28 +-- > >>> drivers/gpu/drm/radeon/radeon_i2c.c | 10 +++ > >>> drivers/gpu/drm/radeon/radeon_mode.h | 6 ++-- > >>> 28 files changed, 93 insertions(+), 93 deletions(-) > >>> > >> > >> > >> > >> Hello Christian, Daniel, David, others, > >> > >> Could you re-review v2 since the feedback provided in v0 [1] has now been > >> addressed? I can send v3 with > >> all other feedback and signoffs from the other maintainers incorporated > >> when I have something for amdgpu > >> and radeon. > > > > This seems like a lot of churn. Additionally, a bunch of these > > headers are shared with other OSes, so it's possible some of the > > changes may end up getting reverted accidently when we sync up or we > > may add new headers in new code with the old nomenclature and then > > we'd need to make sure to adjust it to make sure everything was > > aligned again. I would just as soon leave things as is, but I'm open > > to acking them if there is a strong desire to update things. > > > > Alex > > The way I see it, this is a small downpayment on the debt we have built up so > far. Internship > programs like LF Outreachy to get more underrepresented groups involved in > open source are trying to > change the open source community culture to be more inclusive, but > simultaneously rely on the culture > being welcoming enough as well. > > I do see the challenge involved in preserving the changes and ensuring no new > code is added with > outdated nomenclature (but see [1]), but culture changes one person at a > time, and I'd encourage the community > to do the work needed so we can move past our (mostly) inadvertent role in > perpetuating it. > > That's my 2c (or your sub-unit currency of choice). Fair enough. Acked-by: Aex Deucher > > Easwar > > [1] > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=49decddd39e5f6132ccd7d9fdc3d7c470b0061bb
[PATCH 1/4] drm/amdgpu: add gfx eviction fence helpers
This patch adds basic eviction fence framework for the gfx buffers.
The idea is to:
- One eviction fence is created per gfx process, at kms_open.
- This same fence is attached to all the gem buffers created
by this process.
This framework will be further used for usermode queues.
V2: Addressed review comments from Christian
- keep fence_ctx and fence_seq directly in fpriv
- evcition_fence should be dynamically allocated
- do not save eviction fence instance in BO, there could be many
such fences attached to one BO
- use dma_resv_replace_fence() in detach
Cc: Christian Koenig
Cc: Alex Deucher
Signed-off-by: Shashank Sharma
---
drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 20
.../drm/amd/amdgpu/amdgpu_eviction_fence.c| 106 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 10 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 8 +-
5 files changed, 143 insertions(+), 3 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index b0103f404957..9743bf06d6aa 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -82,7 +82,7 @@ amdgpu-y += amdgpu_device.o amdgpu_doorbell_mgr.o
amdgpu_kms.o \
amdgpu_fw_attestation.o amdgpu_securedisplay.o \
amdgpu_eeprom.o amdgpu_mca.o amdgpu_psp_ta.o amdgpu_lsdma.o \
amdgpu_ring_mux.o amdgpu_xcp.o amdgpu_seq64.o amdgpu_aca.o \
- amdgpu_userq_fence.o
+ amdgpu_userq_fence.o amdgpu_eviction_fence.o
amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 2d5ef2e74c71..a37193fc9ddc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -465,6 +465,11 @@ struct amdgpu_flip_work {
boolasync;
};
+struct amdgpu_eviction_fence {
+ struct dma_fence base;
+ spinlock_t lock;
+ char timeline_name[TASK_COMM_LEN];
+};
/*
* file private structure
@@ -479,6 +484,12 @@ struct amdgpu_fpriv {
struct idr bo_list_handles;
struct amdgpu_ctx_mgr ctx_mgr;
struct amdgpu_userq_mgr userq_mgr;
+
+ /* Eviction fence infra */
+ u64 ev_fence_ctx;
+ atomic_tev_fence_seq;
+ struct amdgpu_eviction_fence *ev_fence;
+
/** GPU partition selection */
uint32_txcp_id;
};
@@ -1480,6 +1491,15 @@ void amdgpu_disable_vblank_kms(struct drm_crtc *crtc);
int amdgpu_info_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp);
+/* Eviction fence */
+struct amdgpu_eviction_fence *amdgpu_eviction_fence_create(struct amdgpu_fpriv
*fpriv);
+void amdgpu_eviction_fence_destroy(struct amdgpu_fpriv *fpriv);
+int amdgpu_eviction_fence_attach(struct amdgpu_eviction_fence *ev_fence,
+struct amdgpu_bo *bo);
+void amdgpu_eviction_fence_detach(struct amdgpu_fpriv *fpriv,
+ struct amdgpu_eviction_fence *ev_fence,
+ struct amdgpu_bo *bo);
+
/*
* functions used by amdgpu_encoder.c
*/
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c
new file mode 100644
index ..1a03f040ccc8
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2024 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include
+#include "amdgpu.h"
+
+static const char *
+amdgpu_ev_fence_get_driver_name(struct dma_fence *fence)
+{
+ return "amdgpu";
+}
+
+static const char
[PATCH 4/4] drm/amdgpu: add userqueue resume
This patch adds support for userqueue resume. What it typically does is
this:
- adds a new delayed work for resuming all the queues.
- schedules this delayed work from the suspend work.
- validates the BOs and replaces the eviction fence before resuming all
the queues running under this instance of userq manager.
Cc: Alex Deucher
Cc: Christian Koenig
Signed-off-by: Shashank Sharma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 166 ++
.../gpu/drm/amd/include/amdgpu_userqueue.h| 1 +
2 files changed, 167 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
index fdbd542e7f53..02ddd713d068 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
@@ -398,6 +398,167 @@ int amdgpu_userq_ioctl(struct drm_device *dev, void *data,
return r;
}
+static int
+amdgpu_userqueue_resume_all(struct amdgpu_userq_mgr *uq_mgr)
+{
+ struct amdgpu_device *adev = uq_mgr->adev;
+ const struct amdgpu_userq_funcs *userq_funcs;
+ struct amdgpu_usermode_queue *queue;
+ int queue_id, ret;
+
+ userq_funcs = adev->userq_funcs[AMDGPU_HW_IP_GFX];
+
+ /* Resume all the queues for this process */
+ idr_for_each_entry(_mgr->userq_idr, queue, queue_id) {
+ ret = userq_funcs->resume(uq_mgr, queue);
+ if (ret)
+ DRM_ERROR("Failed to resume queue %d\n", queue_id);
+ }
+
+ return ret;
+}
+
+static int
+amdgpu_userqueue_replace_ev_fence(struct amdgpu_userq_mgr *uq_mgr,
+ struct drm_exec *exec)
+{
+ int ret;
+ struct amdgpu_fpriv *fpriv = uq_mgr_to_fpriv(uq_mgr);
+ struct amdgpu_vm *vm = >vm;
+ struct amdgpu_eviction_fence *old_ef, *new_ef;
+ struct amdgpu_bo_va *bo_va, *tmp;
+
+ old_ef = fpriv->ev_fence;
+ new_ef = amdgpu_eviction_fence_create(fpriv);
+ if (!new_ef) {
+ DRM_ERROR("Failed to create new eviction fence\n");
+ return ret;
+ }
+
+ list_for_each_entry_safe(bo_va, tmp, >done, base.vm_status) {
+ struct amdgpu_bo *bo = bo_va->base.bo;
+
+ /* Skip pinned BOs */
+ if (bo->tbo.pin_count)
+ continue;
+
+ ret = drm_exec_lock_obj(exec, >tbo.base);
+ if (unlikely(ret)) {
+ DRM_ERROR("Failed to lock BO for eviction fence
replacement\n");
+ goto free_err;
+ }
+
+ /* replace the old eviction fence with new one */
+ amdgpu_eviction_fence_detach(fpriv, old_ef, bo);
+ ret = amdgpu_eviction_fence_attach(new_ef, bo);
+ if (ret) {
+ DRM_ERROR("Failed to attch new eviction fence\n");
+ goto free_err;
+ }
+ }
+
+ /* Update the new eviction fence */
+ fpriv->ev_fence = new_ef;
+ kfree(old_ef);
+ return 0;
+
+free_err:
+ kfree(new_ef);
+ return ret;
+}
+
+/* Expects drm_exec_until_all_locked called on this exec */
+static int
+amdgpu_userqueue_validate_bos(struct amdgpu_userq_mgr *uq_mgr,
+ struct drm_exec *exec)
+{
+ int ret;
+ struct amdgpu_bo *bo;
+ struct amdgpu_bo_va *bo_va, *tmp;
+ struct amdgpu_fpriv *fpriv = uq_mgr_to_fpriv(uq_mgr);
+ struct amdgpu_vm *vm = >vm;
+
+ list_for_each_entry_safe(bo_va, tmp, >done, base.vm_status) {
+ bo = bo_va->base.bo;
+ ret = drm_exec_lock_obj(exec, >tbo.base);
+ if (unlikely(ret)) {
+ DRM_ERROR("Failed to exec lock for validation\n");
+ goto unlock_all;
+ }
+ }
+
+ list_for_each_entry_safe(bo_va, tmp, >invalidated, base.vm_status) {
+ bo = bo_va->base.bo;
+ ret = drm_exec_lock_obj(exec, >tbo.base);
+ if (unlikely(ret)) {
+ DRM_ERROR("Failed to lock BO for validation\n");
+ goto unlock_all;
+ }
+
+ ret = amdgpu_bo_reserve(bo, false);
+ if (unlikely(ret)) {
+ DRM_ERROR("Failed to reserve BO for validation\n");
+ goto unlock_all;
+ }
+
+ ret = amdgpu_userqueue_validate_bo(bo);
+ amdgpu_bo_unreserve(bo);
+ if (ret) {
+ DRM_ERROR("Failed to validate BO\n");
+ goto unlock_all;
+ }
+ }
+
+ ret = amdgpu_vm_handle_moved(uq_mgr->adev, vm, NULL);
+ if (ret)
+ DRM_ERROR("Failed to handle moved BOs\n");
+
+unlock_all:
+ return ret;
+}
+
+static void amdgpu_userqueue_resume_worker(struct work_struct *work)
+{
+ int ret;
+ struct
[PATCH 3/4] drm/amdgpu: suspend gfx userqueues
This patch adds suspend support for gfx userqueues. It typically does
the following:
- adds an enable_signaling function for the eviction fence, so that it
can trigger the userqueue suspend,
- adds a delayed function for suspending the userqueues, to suspend all
the queues under this userq manager and signals the eviction fence,
- adds reference of userq manager in the eviction fence container so
that it can be used in the suspend function.
Cc: Alex Deucher
Cc: Christian Koenig
Signed-off-by: Shashank Sharma
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
.../drm/amd/amdgpu/amdgpu_eviction_fence.c| 6 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 77 +++
.../gpu/drm/amd/include/amdgpu_userqueue.h| 6 ++
5 files changed, 91 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index a37193fc9ddc..1856fe11dd05 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -469,6 +469,7 @@ struct amdgpu_eviction_fence {
struct dma_fence base;
spinlock_t lock;
char timeline_name[TASK_COMM_LEN];
+ struct amdgpu_userq_mgr *uq_mgr;
};
/*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c
index 1a03f040ccc8..3f806e44f614 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c
@@ -39,10 +39,16 @@ amdgpu_ev_fence_get_timeline_name(struct dma_fence *f)
return ef->timeline_name;
}
+static bool amdgpu_ev_fence_enable_signaling(struct dma_fence *f)
+{
+ return !amdgpu_userqueue_enable_signaling(f);
+}
+
static const struct dma_fence_ops amdgpu_eviction_fence_ops = {
.use_64bit_seqno = true,
.get_driver_name = amdgpu_ev_fence_get_driver_name,
.get_timeline_name = amdgpu_ev_fence_get_timeline_name,
+ .enable_signaling = amdgpu_ev_fence_enable_signaling,
};
struct amdgpu_eviction_fence *
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index fa03d9e4874c..8c13de7f2a19 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -111,6 +111,7 @@ struct amdgpu_bo {
#endif
struct kgd_mem *kfd_bo;
+
/*
* For GPUs with spatial partitioning, xcp partition number, -1 means
* any partition. For other ASICs without spatial partition, always 0
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
index 7a89f378c97f..fdbd542e7f53 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
@@ -23,11 +23,16 @@
*/
#include
#include
+#include
#include "amdgpu.h"
#include "amdgpu_vm.h"
#include "amdgpu_userqueue.h"
#include "amdgpu_userq_fence.h"
+#define work_to_uq_mgr(w, name) container_of(w, struct amdgpu_userq_mgr, name)
+#define uq_mgr_to_fpriv(u) container_of(u, struct amdgpu_fpriv, userq_mgr)
+#define to_ev_fence(f) container_of(f, struct amdgpu_eviction_fence, base)
+
static void amdgpu_userq_walk_and_drop_fence_drv(struct xarray *xa)
{
struct amdgpu_userq_fence_driver *fence_drv;
@@ -226,6 +231,7 @@ int amdgpu_userqueue_update_bo_mapping(struct drm_file
*filp, struct amdgpu_bo *
}
drm_syncobj_add_point(syncobj, chain, bo_va->last_pt_update,
(uint64_t)point);
+
return 0;
}
@@ -392,12 +398,83 @@ int amdgpu_userq_ioctl(struct drm_device *dev, void *data,
return r;
}
+static int
+amdgpu_userqueue_suspend_all(struct amdgpu_userq_mgr *uq_mgr)
+{
+ struct amdgpu_device *adev = uq_mgr->adev;
+ const struct amdgpu_userq_funcs *userq_funcs;
+ struct amdgpu_usermode_queue *queue;
+ int queue_id, ret;
+
+ userq_funcs = adev->userq_funcs[AMDGPU_HW_IP_GFX];
+
+ /* Suspend all the queues for this process */
+ idr_for_each_entry(_mgr->userq_idr, queue, queue_id) {
+ ret = userq_funcs->suspend(uq_mgr, queue);
+ if (ret)
+ DRM_ERROR("Failed to suspend queue\n");
+ }
+
+ return ret;
+}
+
+static void
+amdgpu_userqueue_suspend_worker(struct work_struct *work)
+{
+ int ret;
+ struct dma_fence *fence;
+ struct amdgpu_userq_mgr *uq_mgr = work_to_uq_mgr(work,
suspend_work.work);
+ struct amdgpu_fpriv *fpriv = uq_mgr_to_fpriv(uq_mgr);
+
+ mutex_lock(_mgr->userq_mutex);
+ ret = amdgpu_userqueue_suspend_all(uq_mgr);
+ if (ret) {
+ DRM_ERROR("Failed to evict userqueue\n");
+ goto unlock;
+ }
+
+ /* Signal current eviction fence */
+ fence = dma_fence_get(>ev_fence->base);
+ ret = dma_fence_signal(fence);
+
[PATCH 2/4] drm/amdgpu: add core userqueue suspend/resume functions
This patch adds userqueue suspend/resume functions at
core MES V11 IP level.
Cc: Alex Deucher
Cc: Christian Koenig
Signed-off-by: Shashank Sharma
---
.../gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c | 31 +++
.../gpu/drm/amd/include/amdgpu_userqueue.h| 5 +++
2 files changed, 36 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c
b/drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c
index 412970376b49..4e05da3c8f53 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c
@@ -321,7 +321,38 @@ mes_v11_0_userq_mqd_destroy(struct amdgpu_userq_mgr
*uq_mgr,
amdgpu_userqueue_destroy_object(uq_mgr, >mqd);
}
+static int mes_v11_0_userq_suspend(struct amdgpu_userq_mgr *uq_mgr,
+ struct amdgpu_usermode_queue *queue)
+{
+ if (queue->queue_active) {
+ mes_v11_0_userq_unmap(uq_mgr, queue);
+ queue->queue_active = 0;
+ }
+
+ return 0;
+}
+
+static int mes_v11_0_userq_resume(struct amdgpu_userq_mgr *uq_mgr,
+ struct amdgpu_usermode_queue *queue)
+{
+ int ret;
+
+ if (queue->queue_active)
+ return 0;
+
+ ret = mes_v11_0_userq_map(uq_mgr, queue, queue->userq_prop);
+ if (ret) {
+ DRM_ERROR("Failed to resume queue\n");
+ return ret;
+ }
+
+ queue->queue_active = 1;
+ return 0;
+}
+
const struct amdgpu_userq_funcs userq_mes_v11_0_funcs = {
.mqd_create = mes_v11_0_userq_mqd_create,
.mqd_destroy = mes_v11_0_userq_mqd_destroy,
+ .suspend = mes_v11_0_userq_suspend,
+ .resume = mes_v11_0_userq_resume,
};
diff --git a/drivers/gpu/drm/amd/include/amdgpu_userqueue.h
b/drivers/gpu/drm/amd/include/amdgpu_userqueue.h
index 5416de0bdf25..afaf93faa824 100644
--- a/drivers/gpu/drm/amd/include/amdgpu_userqueue.h
+++ b/drivers/gpu/drm/amd/include/amdgpu_userqueue.h
@@ -37,6 +37,7 @@ struct amdgpu_userq_obj {
struct amdgpu_usermode_queue {
int queue_type;
+ uint8_t queue_active;
uint64_tdoorbell_handle;
uint64_tdoorbell_index;
uint64_tflags;
@@ -57,6 +58,10 @@ struct amdgpu_userq_funcs {
struct amdgpu_usermode_queue *queue);
void (*mqd_destroy)(struct amdgpu_userq_mgr *uq_mgr,
struct amdgpu_usermode_queue *uq);
+ int (*suspend)(struct amdgpu_userq_mgr *uq_mgr,
+ struct amdgpu_usermode_queue *queue);
+ int (*resume)(struct amdgpu_userq_mgr *uq_mgr,
+ struct amdgpu_usermode_queue *queue);
};
/* Usermode queues for gfx */
--
2.43.2
[PATCH 0/4] AMDGPU userqueue suspend/resume
This patch series adds support for suspending and resuming the gfx usermode queues. It also adds eviction fences which are primarily used by usermode queues. This patch series is dependent on basic AMDGPU usermode queue series which is being reviewed here: https://patchwork.freedesktop.org/series/113675/ Shashank Sharma (4): drm/amdgpu: add gfx eviction fence helpers drm/amdgpu: add core userqueue suspend/resume functions drm/amdgpu: suspend gfx userqueues drm/amdgpu: add userqueue resume drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 21 ++ .../drm/amd/amdgpu/amdgpu_eviction_fence.c| 112 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 10 +- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 8 +- drivers/gpu/drm/amd/amdgpu/amdgpu_object.h| 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 243 ++ .../gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c | 31 +++ .../gpu/drm/amd/include/amdgpu_userqueue.h| 12 + 9 files changed, 437 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c -- 2.43.2
Re: [PATCH 1/2] drm: Allow mode object properties to be added after a device is registered
On Wed, May 08, 2024 at 02:43:07PM -0500, Mario Limonciello wrote:
> When the colorspace property is registered on MST devices there is
> no `obj_free_cb` callback for it in drm_mode_object_add().
>
> Don't show a warning trace for __drm_mode_object_add() calls for
> DRM_MODE_OBJECT_PROPERTY.
You need to create the property ahead of time. See eg.
commit 1b9bd09630d4 ("drm/i915: Do not create a new max_bpc prop for MST
connectors")
>
> Reported-and-tested-by: Tyler Schneider
> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3353
> Signed-off-by: Mario Limonciello
> ---
> drivers/gpu/drm/drm_mode_object.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/drm_mode_object.c
> b/drivers/gpu/drm/drm_mode_object.c
> index 0e8355063eee..b077547a2db4 100644
> --- a/drivers/gpu/drm/drm_mode_object.c
> +++ b/drivers/gpu/drm/drm_mode_object.c
> @@ -42,7 +42,7 @@ int __drm_mode_object_add(struct drm_device *dev, struct
> drm_mode_object *obj,
> {
> int ret;
>
> - WARN_ON(!dev->driver->load && dev->registered && !obj_free_cb);
> + WARN_ON(!dev->driver->load && dev->registered && !obj_free_cb &&
> obj_type != DRM_MODE_OBJECT_PROPERTY);
>
> mutex_lock(>mode_config.idr_mutex);
> ret = idr_alloc(>mode_config.object_idr, register_obj ? obj : NULL,
> --
> 2.43.0
--
Ville Syrjälä
Intel
[PATCH 2/2] Revert "drm/amd/display: Temporary Disable MST DP Colorspace Property"
MST colorspace property support was disabled due to a series of warnings
that came up when the device was plugged in. As those warnings are fixed,
revert commit 69a959610229 ("drm/amd/display: Temporary Disable MST DP
Colorspace Property").
Reported-and-tested-by: Tyler Schneider
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3353
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 3054bf79fc99..93e2030f4c17 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -7695,7 +7695,7 @@ void amdgpu_dm_connector_init_helper(struct
amdgpu_display_manager *dm,
if (connector_type == DRM_MODE_CONNECTOR_HDMIA) {
if
(!drm_mode_create_hdmi_colorspace_property(>base,
supported_colorspaces))
drm_connector_attach_colorspace_property(>base);
- } else if ((connector_type == DRM_MODE_CONNECTOR_DisplayPort &&
!aconnector->mst_root) ||
+ } else if (connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
connector_type == DRM_MODE_CONNECTOR_eDP) {
if (!drm_mode_create_dp_colorspace_property(>base,
supported_colorspaces))
drm_connector_attach_colorspace_property(>base);
--
2.43.0
[PATCH 1/2] drm: Allow mode object properties to be added after a device is registered
When the colorspace property is registered on MST devices there is
no `obj_free_cb` callback for it in drm_mode_object_add().
Don't show a warning trace for __drm_mode_object_add() calls for
DRM_MODE_OBJECT_PROPERTY.
Reported-and-tested-by: Tyler Schneider
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3353
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/drm_mode_object.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_mode_object.c
b/drivers/gpu/drm/drm_mode_object.c
index 0e8355063eee..b077547a2db4 100644
--- a/drivers/gpu/drm/drm_mode_object.c
+++ b/drivers/gpu/drm/drm_mode_object.c
@@ -42,7 +42,7 @@ int __drm_mode_object_add(struct drm_device *dev, struct
drm_mode_object *obj,
{
int ret;
- WARN_ON(!dev->driver->load && dev->registered && !obj_free_cb);
+ WARN_ON(!dev->driver->load && dev->registered && !obj_free_cb &&
obj_type != DRM_MODE_OBJECT_PROPERTY);
mutex_lock(>mode_config.idr_mutex);
ret = idr_alloc(>mode_config.object_idr, register_obj ? obj : NULL,
--
2.43.0
[PATCH] drm/amdgpu/soc24: use common nbio callback to set remap offset
This fixes HDP flushes on systems with non-4K pages.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc24.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.c
b/drivers/gpu/drm/amd/amdgpu/soc24.c
index 12900488dd618..66c7138fc6aa4 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc24.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc24.c
@@ -372,11 +372,9 @@ static const struct amdgpu_asic_funcs soc24_asic_funcs = {
static int soc24_common_early_init(void *handle)
{
-#define MMIO_REG_HOLE_OFFSET (0x8 - PAGE_SIZE)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
- adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
+ adev->nbio.funcs->set_reg_remap(adev);
adev->smc_rreg = NULL;
adev->smc_wreg = NULL;
adev->pcie_rreg = _device_indirect_rreg;
--
2.45.0
Re: [RFC 1/5] drm/amdgpu: Fix migration rate limiting accounting
On 08.05.24 20:09, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
The logic assumed any migration attempt worked and therefore would over-
account the amount of data migrated during buffer re-validation. As a
consequence client can be unfairly penalised by incorrectly considering
its migration budget spent.
If the migration failed but data was still moved (which I think could be
the case when we try evicting everything but it still doesn't work?),
shouldn't the eviction movements count towards the ratelimit too?
Fix it by looking at the before and after buffer object backing store and
only account if there was a change.
FIXME:
I think this needs a better solution to account for migrations between
VRAM visible and non-visible portions.
FWIW, I have some WIP patches (not posted on any MLs yet though) that
attempt to solve this issue (+actually enforcing ratelimits) by moving
the ratelimit accounting/enforcement to TTM entirely.
By moving the accounting to TTM we can count moved bytes when we move
them, and don't have to rely on comparing resources to determine whether
moving actually happened. This should address your FIXME as well.
Regards,
Friedrich
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Friedrich Vock
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 26 +-
1 file changed, 21 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index ec888fc6ead8..22708954ae68 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -784,12 +784,15 @@ static int amdgpu_cs_bo_validate(void *param, struct
amdgpu_bo *bo)
.no_wait_gpu = false,
.resv = bo->tbo.base.resv
};
+ struct ttm_resource *old_res;
uint32_t domain;
int r;
if (bo->tbo.pin_count)
return 0;
+ old_res = bo->tbo.resource;
+
/* Don't move this buffer if we have depleted our allowance
* to move it. Don't move anything if the threshold is zero.
*/
@@ -817,16 +820,29 @@ static int amdgpu_cs_bo_validate(void *param, struct
amdgpu_bo *bo)
amdgpu_bo_placement_from_domain(bo, domain);
r = ttm_bo_validate(>tbo, >placement, );
- p->bytes_moved += ctx.bytes_moved;
- if (!amdgpu_gmc_vram_full_visible(>gmc) &&
- amdgpu_res_cpu_visible(adev, bo->tbo.resource))
- p->bytes_moved_vis += ctx.bytes_moved;
-
if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
domain = bo->allowed_domains;
goto retry;
}
+ if (!r) {
+ struct ttm_resource *new_res = bo->tbo.resource;
+ bool moved = true;
+
+ if (old_res == new_res)
+ moved = false;
+ else if (old_res && new_res &&
+old_res->mem_type == new_res->mem_type)
+ moved = false;
+
+ if (moved) {
+ p->bytes_moved += ctx.bytes_moved;
+ if (!amdgpu_gmc_vram_full_visible(>gmc) &&
+ amdgpu_res_cpu_visible(adev, bo->tbo.resource))
+ p->bytes_moved_vis += ctx.bytes_moved;
+ }
+ }
+
return r;
}
Re: [PATCH 2/5] drm/amdgpu: Use drm_crtc_vblank_crtc()
On Wed, May 08, 2024 at 09:47:50AM -0400, Alex Deucher wrote: > On Mon, Apr 8, 2024 at 3:06 PM Ville Syrjala > wrote: > > > > From: Ville Syrjälä > > > > Replace the open coded drm_crtc_vblank_crtc() with the real > > thing. > > > > Cc: Alex Deucher > > Cc: "Christian König" > > Cc: "Pan, Xinhui" > > Cc: amd-gfx@lists.freedesktop.org > > Signed-off-by: Ville Syrjälä > > Reviewed-by: Alex Deucher Thanks. Pushed to drm-misc-next. -- Ville Syrjälä Intel
[RFC 3/5] drm/ttm: Add preferred placement flag
From: Tvrtko Ursulin
Currently the fallback placement flag can achieve a hint that buffer
should be migrated back to the non-fallback placement, however that only
works while there is no memory pressure. As soon as we reach full VRAM
utilisation, or worse overcommit, the logic is happy to leave buffers in
the fallback placement. Consequence of this is that once buffers are
evicted they never get considered to be migrated back until the memory
pressure subsides, leaving a potentially active client not able to bring
its buffers back in.
Add a "preferred" placement flag which drivers can set when they want some
extra effort to be attempted for bringing a buffer back in.
QQQ:
Is the current "desired" flag unfortunately named perhaps? I ended up
understanding it as more like "would be nice if possible but absolutely
don't bother under memory pressure".
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Friedrich Vock
---
drivers/gpu/drm/ttm/ttm_resource.c | 13 +
include/drm/ttm/ttm_placement.h| 3 +++
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_resource.c
b/drivers/gpu/drm/ttm/ttm_resource.c
index 4a66b851b67d..59f3d1bcc11f 100644
--- a/drivers/gpu/drm/ttm/ttm_resource.c
+++ b/drivers/gpu/drm/ttm/ttm_resource.c
@@ -305,6 +305,8 @@ bool ttm_resource_compatible(struct ttm_resource *res,
struct ttm_placement *placement,
bool evicting)
{
+ const u32 incompatible_flag = evicting ? TTM_PL_FLAG_DESIRED :
+TTM_PL_FLAG_FALLBACK;
struct ttm_buffer_object *bo = res->bo;
struct ttm_device *bdev = bo->bdev;
unsigned i;
@@ -316,11 +318,14 @@ bool ttm_resource_compatible(struct ttm_resource *res,
const struct ttm_place *place = >placement[i];
struct ttm_resource_manager *man;
- if (res->mem_type != place->mem_type)
- continue;
+ if (res->mem_type != place->mem_type) {
+ if (place->flags & TTM_PL_FLAG_PREFERRED)
+ return false;
+ else
+ continue;
+ }
- if (place->flags & (evicting ? TTM_PL_FLAG_DESIRED :
- TTM_PL_FLAG_FALLBACK))
+ if (place->flags & incompatible_flag)
continue;
if (place->flags & TTM_PL_FLAG_CONTIGUOUS &&
diff --git a/include/drm/ttm/ttm_placement.h b/include/drm/ttm/ttm_placement.h
index b510a4812609..8ea0865e9cc8 100644
--- a/include/drm/ttm/ttm_placement.h
+++ b/include/drm/ttm/ttm_placement.h
@@ -70,6 +70,9 @@
/* Placement is only used during eviction */
#define TTM_PL_FLAG_FALLBACK (1 << 4)
+/* Placement is only used during eviction */
+#define TTM_PL_FLAG_PREFERRED (1 << 5)
+
/**
* struct ttm_place
*
--
2.44.0
[RFC 0/5] Discussion around eviction improvements
From: Tvrtko Ursulin Last few days I was looking at the situation with VRAM over subscription, what happens versus what perhaps should happen. Browsing through the driver and running some simple experiments. I ended up with this patch series which, as a disclaimer, may be completely wrong but as I found some suspicious things, to me at least, I thought it was a good point to stop and request some comments. To perhaps summarise what are the main issues I think I found: * Migration rate limiting does not bother knowing if actual migration happened and so can over-account and unfairly penalise. * Migration rate limiting does not even work, at least not for the common case where userspace configures VRAM+GTT. It thinks it can stop migration attempts by playing with bo->allowed_domains vs bo->preferred domains but, both from the code, and from empirical experiments, I see that not working at all. Both masks are identical so fiddling with them achieves nothing. * Idea of the fallback placement only works when VRAM has free space. As soon as it does not, ttm_resource_compatible is happy to leave the buffers in the secondary placement forever. * Driver thinks it will be re-validating evicted buffers on the next submission but it does not for the very common case of VRAM+GTT because it only checks if current placement is *none* of the preferred placements. All those problems are addressed in individual patches. End result of this series appears to be driver which will try harder to move buffers back into VRAM, but will be (more) correctly throttled in doing so by the existing rate limiting logic. I have run a quick benchmark of Cyberpunk 2077 and cannot say that I saw a change but that could be a good thing too. At least I did not break anything, perhaps.. On one occassion I did see the rate limiting logic get confused while for a period of few minutes it went to a mode where it was constantly giving a high migration budget. But that recovered itself when I switched clients and did not come back so I don't know. If there is something wrong there I don't think it would be caused by any patches in this series. Series is probably rough but should be good enough for dicsussion. I am curious to hear if I identified at least something correctly as a real problem. It would also be good to hear what are the suggested games to check and see whether there is any improvement. Cc: Christian König Cc: Friedrich Vock Tvrtko Ursulin (5): drm/amdgpu: Fix migration rate limiting accounting drm/amdgpu: Actually respect buffer migration budget drm/ttm: Add preferred placement flag drm/amdgpu: Use preferred placement for VRAM+GTT drm/amdgpu: Re-validate evicted buffers drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 38 +- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 8 +++-- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 21 ++-- drivers/gpu/drm/ttm/ttm_resource.c | 13 +--- include/drm/ttm/ttm_placement.h| 3 ++ 5 files changed, 65 insertions(+), 18 deletions(-) -- 2.44.0
[RFC 1/5] drm/amdgpu: Fix migration rate limiting accounting
From: Tvrtko Ursulin
The logic assumed any migration attempt worked and therefore would over-
account the amount of data migrated during buffer re-validation. As a
consequence client can be unfairly penalised by incorrectly considering
its migration budget spent.
Fix it by looking at the before and after buffer object backing store and
only account if there was a change.
FIXME:
I think this needs a better solution to account for migrations between
VRAM visible and non-visible portions.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Friedrich Vock
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 26 +-
1 file changed, 21 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index ec888fc6ead8..22708954ae68 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -784,12 +784,15 @@ static int amdgpu_cs_bo_validate(void *param, struct
amdgpu_bo *bo)
.no_wait_gpu = false,
.resv = bo->tbo.base.resv
};
+ struct ttm_resource *old_res;
uint32_t domain;
int r;
if (bo->tbo.pin_count)
return 0;
+ old_res = bo->tbo.resource;
+
/* Don't move this buffer if we have depleted our allowance
* to move it. Don't move anything if the threshold is zero.
*/
@@ -817,16 +820,29 @@ static int amdgpu_cs_bo_validate(void *param, struct
amdgpu_bo *bo)
amdgpu_bo_placement_from_domain(bo, domain);
r = ttm_bo_validate(>tbo, >placement, );
- p->bytes_moved += ctx.bytes_moved;
- if (!amdgpu_gmc_vram_full_visible(>gmc) &&
- amdgpu_res_cpu_visible(adev, bo->tbo.resource))
- p->bytes_moved_vis += ctx.bytes_moved;
-
if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
domain = bo->allowed_domains;
goto retry;
}
+ if (!r) {
+ struct ttm_resource *new_res = bo->tbo.resource;
+ bool moved = true;
+
+ if (old_res == new_res)
+ moved = false;
+ else if (old_res && new_res &&
+old_res->mem_type == new_res->mem_type)
+ moved = false;
+
+ if (moved) {
+ p->bytes_moved += ctx.bytes_moved;
+ if (!amdgpu_gmc_vram_full_visible(>gmc) &&
+ amdgpu_res_cpu_visible(adev, bo->tbo.resource))
+ p->bytes_moved_vis += ctx.bytes_moved;
+ }
+ }
+
return r;
}
--
2.44.0
[RFC 5/5] drm/amdgpu: Re-validate evicted buffers
From: Tvrtko Ursulin
Currently the driver appears to be thinking that it will be attempting to
re-validate the evicted buffers on the next submission if they are not in
their preferred placement.
That however appears not to be true for the very common case of buffers
with allowed placements of VRAM+GTT. Simply because the check can only
detect if the current placement is *none* of the preferred ones, happily
leaving VRAM+GTT buffers in the GTT placement "forever".
Fix it by extending the VRAM+GTT special case to the re-validation logic.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Friedrich Vock
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 21 ++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 6bddd43604bc..e53ff914b62e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1248,10 +1248,25 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
struct amdgpu_bo_va *bo_va,
* next command submission.
*/
if (amdgpu_vm_is_bo_always_valid(vm, bo)) {
- uint32_t mem_type = bo->tbo.resource->mem_type;
+ unsigned current_domain =
+ amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type);
+ bool move_to_evict = false;
- if (!(bo->preferred_domains &
- amdgpu_mem_type_to_domain(mem_type)))
+ if (!(bo->preferred_domains & current_domain)) {
+ move_to_evict = true;
+ } else if ((bo->preferred_domains & AMDGPU_GEM_DOMAIN_MASK) ==
+ (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT) &&
+ current_domain != AMDGPU_GEM_DOMAIN_VRAM) {
+ /*
+* If userspace has provided a list of possible
+* placements equal to VRAM+GTT, we assume VRAM is *the*
+* preferred placement and so try to move it back there
+* on the next submission.
+*/
+ move_to_evict = true;
+ }
+
+ if (move_to_evict)
amdgpu_vm_bo_evicted(_va->base);
else
amdgpu_vm_bo_idle(_va->base);
--
2.44.0
[RFC 2/5] drm/amdgpu: Actually respect buffer migration budget
From: Tvrtko Ursulin
Current code appears to live in a misconception that playing with buffer
allowed and preferred placements can control the decision on whether
backing store migration will be attempted or not.
Both from code inspection and from empirical experiments I see that not
being true, and that both allowed and preferred placement are typically
set to the same bitmask.
As such, when the code decides to throttle the migration for a client, it
is in fact not achieving anything. Buffers can still be either migrated or
not migrated based on the external (to this function and facility) logic.
Fix it by not changing the buffer object placements if the migration
budget has been spent.
FIXME:
Is it still required to call validate is the question..
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Friedrich Vock
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 22708954ae68..d07a1dd7c880 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -784,6 +784,7 @@ static int amdgpu_cs_bo_validate(void *param, struct
amdgpu_bo *bo)
.no_wait_gpu = false,
.resv = bo->tbo.base.resv
};
+ bool migration_allowed = true;
struct ttm_resource *old_res;
uint32_t domain;
int r;
@@ -805,19 +806,24 @@ static int amdgpu_cs_bo_validate(void *param, struct
amdgpu_bo *bo)
* visible VRAM if we've depleted our allowance to do
* that.
*/
- if (p->bytes_moved_vis < p->bytes_moved_vis_threshold)
+ if (p->bytes_moved_vis < p->bytes_moved_vis_threshold) {
domain = bo->preferred_domains;
- else
+ } else {
domain = bo->allowed_domains;
+ migration_allowed = false;
+ }
} else {
domain = bo->preferred_domains;
}
} else {
domain = bo->allowed_domains;
+ migration_allowed = false;
}
retry:
- amdgpu_bo_placement_from_domain(bo, domain);
+ if (migration_allowed)
+ amdgpu_bo_placement_from_domain(bo, domain);
+
r = ttm_bo_validate(>tbo, >placement, );
if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
--
2.44.0
[RFC 4/5] drm/amdgpu: Use preferred placement for VRAM+GTT
From: Tvrtko Ursulin
Now that TTM has the preferred placement flag, extend the current
workaround which assumes the GTT placement as fallback in the presence of
the additional VRAM placement.
By marking the VRAM placement as preferred we will make the buffer re-
validation phase actually attempt to migrate them back to VRAM.
Without it, TTM core logic is happy to leave them in GTT placement
"forever".
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Friedrich Vock
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 50b7e7c0ce50..9be767357e86 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -128,8 +128,8 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo,
u32 domain)
struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
struct ttm_placement *placement = >placement;
struct ttm_place *places = abo->placements;
+ int c = 0, vram_index = -1;
u64 flags = abo->flags;
- u32 c = 0;
if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
unsigned int visible_pfn = adev->gmc.visible_vram_size >>
PAGE_SHIFT;
@@ -158,7 +158,7 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo,
u32 domain)
flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
places[c].flags |= TTM_PL_FLAG_CONTIGUOUS;
- c++;
+ vram_index = c++;
}
if (domain & AMDGPU_GEM_DOMAIN_DOORBELL) {
@@ -180,8 +180,10 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo
*abo, u32 domain)
* When GTT is just an alternative to VRAM make sure that we
* only use it as fallback and still try to fill up VRAM first.
*/
- if (domain & abo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM)
+ if (vram_index >= 0) {
places[c].flags |= TTM_PL_FLAG_FALLBACK;
+ places[vram_index].flags |= TTM_PL_FLAG_PREFERRED;
+ }
c++;
}
--
2.44.0
Re: [PATCH] drm/amdgpu: Fix comparison in amdgpu_res_cpu_visible
Am 08.05.24 um 15:45 schrieb Alex Deucher:
On Wed, May 8, 2024 at 9:25 AM Michel Dänzer wrote:
From: Michel Dänzer
It incorrectly claimed a resource isn't CPU visible if it's located at
the very end of CPU visible VRAM.
Fixes: a6ff969fe9 ("drm/amdgpu: fix visible VRAM handling during faults")
Reported-and-Tested-by: Jeremy Day
Signed-off-by: Michel Dänzer
Reviewed-by: Alex Deucher
Reviewed-by: Christian König
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3343
CC: sta...@vger.kernel.org
Christian.
and applied. Thanks!
Alex
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 109fe557a02b..29c197c00018 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -427,7 +427,7 @@ bool amdgpu_res_cpu_visible(struct amdgpu_device *adev,
amdgpu_res_first(res, 0, res->size, );
while (cursor.remaining) {
- if ((cursor.start + cursor.size) >= adev->gmc.visible_vram_size)
+ if ((cursor.start + cursor.size) > adev->gmc.visible_vram_size)
return false;
amdgpu_res_next(, cursor.size);
}
--
2.43.0
[PATCH 20/20] drm/amd/display: 3.2.285
From: Aric Cyr This version brings along following fixes: - Read default boot options - Find max flickerless instant vtotal delta - Refactor dcn401_update_clocks - Reduce I2C speed to 95kHz in DCN401 - Allow higher DSC slice support for small timings on dcn401 - Don't offload flip if not only address update - Check UHBR13.5 cap when determining max link cap - Enable SYMCLK gating in DCCG - Expand to higher link rates - Add left edge pixel for YCbCr422/420 + ODM pipe split - Add resource interfaces for get ODM slice rect - Add COEF filter types for DCN401 - Refactor DCN401 DCCG into component directory - Fix 3dlut size for Fastloading on DCN401 - Fix write to non-existent reg on DCN401 - Remove USBC check for DCN32 - Remove unused code for some dc files - Disable AC/DC codepath when unnecessary - Create dcn401_clk_mgr struct Acked-by: Alex Hung Signed-off-by: Aric Cyr --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index d550b6f97039..a7ba80c84128 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -55,7 +55,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.284" +#define DC_VER "3.2.285" #define MAX_SURFACES 3 #define MAX_PLANES 6 -- 2.34.1
[PATCH 19/20] drm/amd/display: Read default boot options
From: Duncan Ma
[WHY]
DPIA boot option is set by VBIOS. It gets
overwritten when driver loads DMU.
[HOW]
Read PreOS boot options and determine if
dpia is enabled.
Reviewed-by: Ovidiu Bunea
Acked-by: Alex Hung
Signed-off-by: Duncan Ma
---
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
index 70e63aeb8f89..7f53074f4e48 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
@@ -410,10 +410,13 @@ union dmub_fw_boot_options
dmub_dcn35_get_fw_boot_option(struct dmub_srv *dmub)
void dmub_dcn35_enable_dmub_boot_options(struct dmub_srv *dmub, const struct
dmub_srv_hw_params *params)
{
union dmub_fw_boot_options boot_options = {0};
+ union dmub_fw_boot_options cur_boot_options = {0};
+
+ cur_boot_options = dmub_dcn35_get_fw_boot_option(dmub);
boot_options.bits.z10_disable = params->disable_z10;
boot_options.bits.dpia_supported = params->dpia_supported;
- boot_options.bits.enable_dpia = params->disable_dpia == true ? 0:1;
+ boot_options.bits.enable_dpia = cur_boot_options.bits.enable_dpia &&
!params->disable_dpia;
boot_options.bits.usb4_cm_version = params->usb4_cm_version;
boot_options.bits.dpia_hpd_int_enable_supported =
params->dpia_hpd_int_enable_supported;
boot_options.bits.power_optimization = params->power_optimization;
--
2.34.1
[PATCH 18/20] drm/amd/display: Find max flickerless instant vtotal delta
From: Ethan Bitnun
[WHAT & HOW]
- Populate dml 2 callback with get_max_flickerless_instant_vtotal_increase
- Use long long when necessary to prevent overflow
- Add asic specific default values, currently disabled by
default for every asic
- Use the pre-existing debug option to protect the call to
get_max_flickerless_instant_vtotal_increase
Reviewed-by: Alvin Lee
Acked-by: Alex Hung
Signed-off-by: Ethan Bitnun
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 3 +
.../gpu/drm/amd/display/dc/core/dc_stream.c | 64 +--
.../gpu/drm/amd/display/dc/dc_stream_priv.h | 14
.../display/dc/dcn32/dcn32_resource_helpers.c | 2 +-
.../drm/amd/display/dc/dml2/dml2_wrapper.h| 3 +
5 files changed, 79 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 8a5cc8b80217..70c39eef99e5 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -43,6 +43,8 @@
#include "link.h"
#include "clk_mgr.h"
#include "dc_state_priv.h"
+#include "dc_stream_priv.h"
+
#include "virtual/virtual_link_hwss.h"
#include "link/hwss/link_hwss_dio.h"
#include "link/hwss/link_hwss_dpia.h"
@@ -5195,6 +5197,7 @@ void resource_init_common_dml2_callbacks(struct dc *dc,
struct dml2_configuratio
dml2_options->callbacks.get_dpp_pipes_for_plane =
_get_dpp_pipes_for_plane;
dml2_options->callbacks.get_stream_status = _state_get_stream_status;
dml2_options->callbacks.get_stream_from_id =
_state_get_stream_from_id;
+ dml2_options->callbacks.get_max_flickerless_instant_vtotal_increase =
_stream_get_max_flickerless_instant_vtotal_increase;
dml2_options->svp_pstate.callbacks.dc = dc;
dml2_options->svp_pstate.callbacks.add_phantom_plane =
_state_add_phantom_plane;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index b5a89b587d86..de48084eac25 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -833,7 +833,7 @@ static int
dc_stream_get_brightness_millinits_linear_interpolation (struct dc_st
int index2,
int
refresh_hz)
{
- int slope = 0;
+ long long slope = 0;
if (stream->lumin_data.refresh_rate_hz[index2] !=
stream->lumin_data.refresh_rate_hz[index1]) {
slope = (stream->lumin_data.luminance_millinits[index2] -
stream->lumin_data.luminance_millinits[index1]) /
(stream->lumin_data.refresh_rate_hz[index2] -
stream->lumin_data.refresh_rate_hz[index1]);
@@ -852,7 +852,7 @@ static int dc_stream_get_refresh_hz_linear_interpolation
(struct dc_stream_state
int index2,
int
brightness_millinits)
{
- int slope = 1;
+ long long slope = 1;
if (stream->lumin_data.refresh_rate_hz[index2] !=
stream->lumin_data.refresh_rate_hz[index1]) {
slope = (stream->lumin_data.luminance_millinits[index2] -
stream->lumin_data.luminance_millinits[index1]) /
(stream->lumin_data.refresh_rate_hz[index2] -
stream->lumin_data.refresh_rate_hz[index1]);
@@ -860,7 +860,7 @@ static int dc_stream_get_refresh_hz_linear_interpolation
(struct dc_stream_state
int y_intercept = stream->lumin_data.luminance_millinits[index2] -
slope * stream->lumin_data.refresh_rate_hz[index2];
- return ((brightness_millinits - y_intercept) / slope);
+ return ((int)div64_s64((brightness_millinits - y_intercept), slope));
}
/*
@@ -884,8 +884,9 @@ static int dc_stream_get_brightness_millinits_from_refresh
(struct dc_stream_sta
}
/*
- * Finds the lowest refresh rate that can be achieved
- * from starting_refresh_hz while staying within flicker criteria
+ * Finds the lowest/highest refresh rate (depending on search_for_max_increase)
+ * that can be achieved from starting_refresh_hz while staying
+ * within flicker criteria
*/
static int dc_stream_calculate_flickerless_refresh_rate(struct dc_stream_state
*stream,
int current_brightness,
@@ -942,7 +943,7 @@ static int
dc_stream_calculate_flickerless_refresh_rate(struct dc_stream_state *
}
if (search_for_max_increase)
- return
stream->lumin_data.refresh_rate_hz[LUMINANCE_DATA_TABLE_SIZE - 1];
+ return (int)div64_s64((long
long)stream->timing.pix_clk_100hz*100,
stream->timing.v_total*stream->timing.h_total);
else
return stream->lumin_data.refresh_rate_hz[0];
}
@@ -982,6 +983,31 @@ static int
[PATCH 17/20] drm/amd/display: Refactor dcn401_update_clocks
From: Dillon Varone
[WHY & HOW]
Refactor complex code into manageable functions. This also cleans up
some updating logics.
Reviewed-by: Alvin Lee
Acked-by: Alex Hung
Signed-off-by: Dillon Varone
---
.../amd/display/dc/clk_mgr/dcn401/dalsmc.h| 8 +-
.../dc/clk_mgr/dcn401/dcn401_clk_mgr.c| 523 +-
.../dc/clk_mgr/dcn401/dcn401_clk_mgr.h| 94
.../clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c | 80 ++-
.../clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h | 10 +
.../gpu/drm/amd/display/dc/core/dc_resource.c | 3 +-
drivers/gpu/drm/amd/display/dc/dc.h | 3 +
.../gpu/drm/amd/display/include/dal_asic_id.h | 3 +
8 files changed, 718 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dalsmc.h
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dalsmc.h
index 0d2584437934..5653c7991c62 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dalsmc.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dalsmc.h
@@ -36,7 +36,13 @@
#define DALSMC_MSG_SetFclkSwitchAllow 0x11
#define DALSMC_MSG_SetCabForUclkPstate0x12
#define DALSMC_MSG_SetWorstCaseUclkLatency0x13
-#define DALSMC_Message_Count 0x14
+#define DALSMC_MSG_DcnExitReset 0x14
+#define DALSMC_MSG_ReturnHardMinStatus0x15
+#define DALSMC_MSG_SetAlwaysWaitDmcubResp 0x16
+#define DALSMC_MSG_IndicateDrrStatus 0x17 // PMFW 15811
+#define DALSMC_MSG_ActiveUclkFclk 0x18
+#define DALSMC_MSG_IdleUclkFclk 0x19
+#define DALSMC_Message_Count 0x1A
typedef enum {
FCLK_SWITCH_DISALLOW,
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
index bd74ff47fb37..d2abc00a60c5 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
@@ -67,6 +67,9 @@ static const struct clk_mgr_mask clk_mgr_mask_dcn401 = {
CLK_COMMON_MASK_SH_LIST_DCN401(_MASK)
};
+#define TO_DCN401_CLK_MGR(clk_mgr)\
+ container_of(clk_mgr, struct dcn401_clk_mgr, base)
+
static bool dcn401_is_ppclk_dpm_enabled(struct clk_mgr_internal *clk_mgr,
PPCLK_e clk)
{
bool ppclk_dpm_enabled = false;
@@ -112,6 +115,30 @@ static bool dcn401_is_ppclk_dpm_enabled(struct
clk_mgr_internal *clk_mgr, PPCLK_
return ppclk_dpm_enabled;
}
+static bool dcn401_is_ppclk_idle_dpm_enabled(struct clk_mgr_internal *clk_mgr,
PPCLK_e clk)
+{
+ bool ppclk_idle_dpm_enabled = false;
+
+ switch (clk) {
+ case PPCLK_UCLK:
+ case PPCLK_FCLK:
+ if
(ASICREV_IS_GC_12_0_0_A0(clk_mgr->base.ctx->asic_id.hw_internal_rev) &&
+ clk_mgr->smu_ver >= 0x681800) {
+ ppclk_idle_dpm_enabled = true;
+ } else if
(ASICREV_IS_GC_12_0_1_A0(clk_mgr->base.ctx->asic_id.hw_internal_rev) &&
+ clk_mgr->smu_ver >= 0x661300) {
+ ppclk_idle_dpm_enabled = true;
+ }
+ break;
+ default:
+ ppclk_idle_dpm_enabled = false;
+ }
+
+ ppclk_idle_dpm_enabled &= clk_mgr->smu_present;
+
+ return ppclk_idle_dpm_enabled;
+}
+
/* Query SMU for all clock states for a particular clock */
static void dcn401_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e
clk, unsigned int *entry_0,
unsigned int *num_levels)
@@ -470,7 +497,7 @@ static void dcn401_update_clocks_update_dentist(
}
-static void dcn401_update_clocks(struct clk_mgr *clk_mgr_base,
+static void dcn401_update_clocks_legacy(struct clk_mgr *clk_mgr_base,
struct dc_state *context,
bool safe_to_lower)
{
@@ -512,7 +539,7 @@ static void dcn401_update_clocks(struct clk_mgr
*clk_mgr_base,
if (clk_mgr->smu_present) {
if (enter_display_off == safe_to_lower)
- dcn30_smu_set_num_of_displays(clk_mgr, display_count);
+ dcn401_smu_set_num_of_displays(clk_mgr, display_count);
clk_mgr_base->clks.fclk_prev_p_state_change_support =
clk_mgr_base->clks.fclk_p_state_change_support;
@@ -542,7 +569,7 @@ static void dcn401_update_clocks(struct clk_mgr
*clk_mgr_base,
if (should_set_clock(safe_to_lower,
new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
clk_mgr_base->clks.dcfclk_deep_sleep_khz =
new_clocks->dcfclk_deep_sleep_khz;
if (dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_DCFCLK))
- dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr,
khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz));
+ dcn401_smu_set_min_deep_sleep_dcef_clk(clk_mgr,
[PATCH 16/20] drm/amd/display: Reduce I2C speed to 95kHz in DCN401
From: Chris Park [WHY] HW for DCN401 is presented with a small I2C speed fluctuation that exceeds the hard cap limitation of 100kHz occasionally. This violates compliance requirement and will result in failure in compliance. [HOW] After various measurements and traceback to previous generation HW, DCN IP, SI and SW driver agrees that we can reduce I2C speed to 95kHz to address the I2C spped fluctuation in DCN401. Reviewed-by: Dillon Varone Acked-by: Alex Hung Signed-off-by: Chris Park --- .../gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c index 75e2c62ae792..a55421363772 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c @@ -1772,8 +1772,8 @@ static bool dcn401_resource_construct( pool->base.pipe_count = num_pipes; pool->base.mpcc_count = num_pipes; dc->caps.max_downscale_ratio = 600; - dc->caps.i2c_speed_in_khz = 100; - dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/ + dc->caps.i2c_speed_in_khz = 95; + dc->caps.i2c_speed_in_khz_hdcp = 95; /*1.4 w/a applied by default*/ /* TODO: Bring max cursor size back to 256 after subvp cursor corruption is fixed*/ dc->caps.max_cursor_size = 64; dc->caps.cursor_not_scaled = true; -- 2.34.1
[PATCH 15/20] drm/amd/display: Allow higher DSC slice support for small timings on dcn401
From: Wenjing Liu
[WHY]
DML2.1 has added the support to determine ODM combine based on DSC slice
count limitation. This support would allow us to support DSC slice higher
than 4 on small timings. The change will allow higher DSC slice support
independent from pixel clock in use.
[HOW]
Add a DCN401 get_enc_caps function to allow the support for DSC slice count
higher than 4.
Reviewed-by: Dillon Varone
Acked-by: Alex Hung
Signed-off-by: Wenjing Liu
---
.../amd/display/dc/dsc/dcn401/dcn401_dsc.c| 412 ++
1 file changed, 39 insertions(+), 373 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
index 845686d57919..52f23bb554af 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
@@ -9,6 +9,9 @@
#include "dsc/dscc_types.h"
#include "dsc/rc_calc.h"
+#define MAX_THROUGHPUT_PER_DSC_100HZ 2000
+#define MAX_DSC_UNIT_COMBINE 4
+
static void dsc_write_to_registers(struct display_stream_compressor *dsc,
const struct dsc_reg_values *reg_vals);
/* Object I/F functions */
@@ -22,9 +25,10 @@ static void dsc401_enable(struct display_stream_compressor
*dsc, int opp_pipe);
static void dsc401_disable(struct display_stream_compressor *dsc);
static void dsc401_disconnect(struct display_stream_compressor *dsc);
static void dsc401_wait_disconnect_pending_clear(struct
display_stream_compressor *dsc);
+static void dsc401_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int
pixel_clock_100Hz);
const struct dsc_funcs dcn401_dsc_funcs = {
- .dsc_get_enc_caps = dsc2_get_enc_caps,
+ .dsc_get_enc_caps = dsc401_get_enc_caps,
.dsc_read_state = dsc401_read_state,
.dsc_validate_stream = dsc401_validate_stream,
.dsc_set_config = dsc401_set_config,
@@ -48,9 +52,6 @@ const struct dsc_funcs dcn401_dsc_funcs = {
#define DC_LOGGER \
dsc->ctx->logger
-#define DCN401_MAX_PIXEL_CLOCK_Mhz 1188
-#define DCN401_MAX_DISPLAY_CLOCK_Mhz1200
-
enum dsc_bits_per_comp {
DSC_BPC_8 = 8,
DSC_BPC_10 = 10,
@@ -78,50 +79,40 @@ void dsc401_construct(struct dcn401_dsc *dsc,
dsc->max_image_width = 5184;
}
-/* This returns the capabilities for a single DSC encoder engine. Number of
slices and total throughput
- * can be doubled, tripled etc. by using additional DSC engines.
- */
-//static void dsc401_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int
pixel_clock_100Hz)
-//{
-// dsc_enc_caps->dsc_version = 0x21; /* v1.2 - DP spec defined it in
reverse order and we kept it */
-//
-// /*dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 1;
-// dsc_enc_caps->slice_caps.bits.NUM_SLICES_2 = 1;
-// dsc_enc_caps->slice_caps.bits.NUM_SLICES_3 = 1;
-// dsc_enc_caps->slice_caps.bits.NUM_SLICES_4 = 1;
-//
-// dsc_enc_caps->lb_bit_depth = 13;
-// dsc_enc_caps->is_block_pred_supported = true;
-//
-// dsc_enc_caps->color_formats.bits.RGB = 1;
-// dsc_enc_caps->color_formats.bits.YCBCR_444 = 1;
-// dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1;
-// dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0;
-// dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1;
-//
-// dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1;
-// dsc_enc_caps->color_depth.bits.COLOR_DEPTH_10_BPC = 1;
-// dsc_enc_caps->color_depth.bits.COLOR_DEPTH_12_BPC = 1;
-//
-// /* Maximum total throughput with all the slices combined. This is
different from how DP spec specifies it.
-// * Our decoder's total throughput in Pix/s is equal to DISPCLK. This is
then shared between slices.
-// * The value below is the absolute maximum value. The actual throughput
may be lower, but it'll always
-// * be sufficient to process the input pixel rate fed into a single DSC
engine.
-// */
-// /*dsc_enc_caps->max_total_throughput_mps = DCN401_MAX_DISPLAY_CLOCK_Mhz;
-//
-// /* For pixel clock bigger than a single-pipe limit we'll need two
engines, which then doubles our
-// * throughput and number of slices, but also introduces a lower limit
of 2 slices
-// */
-// /*if (pixel_clock_100Hz >= DCN401_MAX_PIXEL_CLOCK_Mhz*1) {
-// dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 0;
-// dsc_enc_caps->slice_caps.bits.NUM_SLICES_8 = 1;
-// dsc_enc_caps->max_total_throughput_mps =
DCN401_MAX_DISPLAY_CLOCK_Mhz * 2;
-// }
-//
-// dsc_enc_caps->max_slice_width = 5184; /* (including 64 overlap pixels
for eDP MSO mode) */
-// /*dsc_enc_caps->bpp_increment_div = 16; /* 1/16th of a bit */
-//}
+static void dsc401_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int
pixel_clock_100Hz)
+{
+ int min_dsc_unit_required = (pixel_clock_100Hz +
MAX_THROUGHPUT_PER_DSC_100HZ - 1) / MAX_THROUGHPUT_PER_DSC_100HZ;
+
+ dsc_enc_caps->dsc_version = 0x21; /* v1.2 - DP spec defined it in
reverse
[PATCH 14/20] drm/amd/display: Don't offload flip if not only address update
From: Alvin Lee
[WHAT & HOW]
Fast updates can consist of some stream updates as well (i.e., out_csc).
In these cases we should not offload the flip to FW as we can only
offload address only updates to FW.
Reviewed-by: Chris Park
Acked-by: Alex Hung
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 0f20a3d96d93..0208b28517ac 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3664,6 +3664,10 @@ static void commit_planes_for_stream_fast(struct dc *dc,
break;
}
}
+ if (stream_update) {
+ /* more than address update, need to acquire FAMS2 lock
*/
+ should_offload_fams2_flip = false;
+ }
}
dc_exit_ips_for_hw_access(dc);
--
2.34.1
[PATCH 13/20] drm/amd/display: Check UHBR13.5 cap when determining max link cap
From: George Shen
[WHY]
UHBR13.5 support is optional, even if UHBR20 is supported by the device.
If source supports max UHBR13.5 while sink, cable and LTTPR support
UHBR20 but not UHBR13.5, UHBR10 should be used as the max link cap.
Reviewed-by: Wenjing Liu
Acked-by: Alex Hung
Signed-off-by: George Shen
---
.../dc/link/protocols/link_dp_capability.c| 22 +++
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
index 8f57b344f09e..766116ec627d 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
@@ -2062,7 +2062,7 @@ struct dc_link_settings dp_get_max_link_cap(struct
dc_link *link)
enum dc_link_rate lttpr_max_link_rate;
enum dc_link_rate cable_max_link_rate;
struct link_encoder *link_enc = NULL;
-
+ bool is_uhbr13_5_supported = true;
link_enc = link_enc_cfg_get_link_enc(link);
ASSERT(link_enc);
@@ -2083,6 +2083,9 @@ struct dc_link_settings dp_get_max_link_cap(struct
dc_link *link)
max_link_cap.link_spread =
link->reported_link_cap.link_spread;
+ if (!link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5)
+ is_uhbr13_5_supported = false;
+
/* Lower link settings based on cable attributes
* Cable ID is a DP2 feature to identify max certified link rate that
* a cable can carry. The cable identification method requires both
@@ -2101,9 +2104,13 @@ struct dc_link_settings dp_get_max_link_cap(struct
dc_link *link)
cable_max_link_rate = get_cable_max_link_rate(link);
if (!link->dc->debug.ignore_cable_id &&
- cable_max_link_rate != LINK_RATE_UNKNOWN &&
- cable_max_link_rate < max_link_cap.link_rate)
- max_link_cap.link_rate = cable_max_link_rate;
+ cable_max_link_rate != LINK_RATE_UNKNOWN) {
+ if (cable_max_link_rate < max_link_cap.link_rate)
+ max_link_cap.link_rate = cable_max_link_rate;
+
+ if (!link->dpcd_caps.cable_id.bits.UHBR13_5_CAPABILITY)
+ is_uhbr13_5_supported = false;
+ }
/* account for lttpr repeaters cap
* notes: repeaters do not snoop in the DPRX Capabilities addresses
(3.6.3).
@@ -2116,12 +2123,19 @@ struct dc_link_settings dp_get_max_link_cap(struct
dc_link *link)
if (lttpr_max_link_rate < max_link_cap.link_rate)
max_link_cap.link_rate = lttpr_max_link_rate;
+ if
(!link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR13_5)
+ is_uhbr13_5_supported = false;
+
DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR, max_lane
count %d max_link rate %d \n",
__func__,
max_link_cap.lane_count,
max_link_cap.link_rate);
}
+ if (max_link_cap.link_rate == LINK_RATE_UHBR13_5 &&
+ !is_uhbr13_5_supported)
+ max_link_cap.link_rate = LINK_RATE_UHBR10;
+
if (link_dp_get_encoding_format(_link_cap) == DP_128b_132b_ENCODING
&&
link->dc->debug.disable_uhbr)
max_link_cap.link_rate = LINK_RATE_HIGH3;
--
2.34.1
[PATCH 12/20] drm/amd/display: Enable SYMCLK gating in DCCG
From: Daniel Miess
[WHY & HOW]
Enable root clock optimization for SYMCLK and only
disable it when it's actively used.
Reviewed-by: Charlene Liu
Acked-by: Alex Hung
Signed-off-by: Daniel Miess
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
.../amd/display/dc/dccg/dcn35/dcn35_dccg.c| 102 ++
.../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 45 +++-
.../amd/display/dc/hwss/dcn35/dcn35_hwseq.h | 2 +
.../amd/display/dc/hwss/dcn35/dcn35_init.c| 1 +
.../amd/display/dc/hwss/dcn351/dcn351_init.c | 1 +
.../display/dc/hwss/hw_sequencer_private.h| 4 +
drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 7 ++
8 files changed, 115 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 2fce8c0303fa..eef2f357fe14 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -726,6 +726,7 @@ enum pg_hw_pipe_resources {
PG_DPSTREAM,
PG_HDMISTREAM,
PG_PHYSYMCLK,
+ PG_SYMCLK,
PG_HW_PIPE_RESOURCES_NUM_ELEMENT
};
diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
index 1fc3aa2b507b..d3b27920e294 100644
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
@@ -655,9 +655,61 @@ static void dccg35_disable_symclk32_se(
}
}
+static void dccg35_set_symclk_root_clock_gating(struct dccg *dccg, uint32_t
stream_enc_inst,
+ uint32_t link_enc_inst, bool enable)
+{
+ struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+ switch (stream_enc_inst) {
+ case 0:
+ if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe)
+ REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,
SYMCLKA_FE_ROOT_GATE_DISABLE, enable ? 1 : 0);
+ break;
+ case 1:
+ if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe)
+ REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,
SYMCLKB_FE_ROOT_GATE_DISABLE, enable ? 1 : 0);
+ break;
+ case 2:
+ if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe)
+ REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,
SYMCLKC_FE_ROOT_GATE_DISABLE, enable ? 1 : 0);
+ break;
+ case 3:
+ if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe)
+ REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,
SYMCLKD_FE_ROOT_GATE_DISABLE, enable ? 1 : 0);
+ break;
+ case 4:
+ if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe)
+ REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,
SYMCLKE_FE_ROOT_GATE_DISABLE, enable ? 1 : 0);
+ break;
+ }
+
+ switch (link_enc_inst) {
+ case 0:
+ if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe)
+ REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,
SYMCLKA_ROOT_GATE_DISABLE, enable ? 1 : 0);
+ break;
+ case 1:
+ if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe)
+ REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,
SYMCLKB_ROOT_GATE_DISABLE, enable ? 1 : 0);
+ break;
+ case 2:
+ if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe)
+ REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,
SYMCLKC_ROOT_GATE_DISABLE, enable ? 1 : 0);
+ break;
+ case 3:
+ if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe)
+ REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,
SYMCLKD_ROOT_GATE_DISABLE, enable ? 1 : 0);
+ break;
+ case 4:
+ if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe)
+ REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,
SYMCLKE_ROOT_GATE_DISABLE, enable ? 1 : 0);
+ break;
+ }
+}
+
void dccg35_init(struct dccg *dccg)
{
- int otg_inst;
+ int otg_inst, phy_inst;
/* Set HPO stream encoder to use refclk to avoid case where PHY is
* disabled and SYMCLK32 for HPO SE is sourced from PHYD32CLK which
* will cause DCN to hang.
@@ -671,10 +723,9 @@ void dccg35_init(struct dccg *dccg)
dccg31_set_symclk32_le_root_clock_gating(dccg,
otg_inst, false);
}
-// if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
-// for (otg_inst = 0; otg_inst < 4; otg_inst++)
-// dccg35_disable_symclk_se(dccg, otg_inst, otg_inst);
-
+ if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe)
+ for (phy_inst = 0; phy_inst < 5; phy_inst++)
+ dccg35_set_symclk_root_clock_gating(dccg, phy_inst,
phy_inst, false);
if
[PATCH 11/20] drm/amd/display: Expand to higher link rates
From: Sung Joon Kim [WHY & HOW] To support higher link rates that sink allows, we need to make sure driver is ready and perform correct link-training sequence. Reviewed-by: Wenjing Liu Acked-by: Alex Hung Signed-off-by: Sung Joon Kim --- .../gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c index 107b2cec572d..8f57b344f09e 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c @@ -209,6 +209,9 @@ static enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in case 810: link_rate = LINK_RATE_HIGH3;// Rate_9 (HBR3)- 8.10 Gbps/Lane break; + case 1000: + link_rate = LINK_RATE_UHBR10; // UHBR10 - 10.0 Gbps/Lane + break; default: link_rate = LINK_RATE_UNKNOWN; break; -- 2.34.1
[PATCH 10/20] drm/amd/display: Add left edge pixel for YCbCr422/420 + ODM pipe split
From: Wenjing Liu
[WHY]
Currently 3-tap chroma subsampling is used for YCbCr422/420. When ODM
pipesplit is used, pixels on the left edge of ODM slices need one extra
pixel from the right edge of the previous slice to calculate the correct
chroma value.
Without this change, the chroma value is slightly different than
expected. This is usually imperceptible visually, but it impacts test
pattern CRCs for compliance test automation.
[HOW]
Update logic to use the register for adding extra left edge pixel for
YCbCr422/420 ODM cases.
Reviewed-by: George Shen
Acked-by: Alex Hung
Signed-off-by: Wenjing Liu
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 9 ++-
.../gpu/drm/amd/display/dc/dcn20/dcn20_opp.c | 25 +--
.../gpu/drm/amd/display/dc/dcn20/dcn20_opp.h | 4 +-
.../drm/amd/display/dc/dcn201/dcn201_opp.c| 1 +
.../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 67 +--
.../amd/display/dc/hwss/dcn314/dcn314_hwseq.c | 4 +-
.../amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 8 ++-
.../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 4 +-
.../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 48 -
drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 7 +-
.../amd/display/dc/inc/hw/timing_generator.h | 2 +-
.../amd/display/dc/optc/dcn20/dcn20_optc.c| 6 +-
.../amd/display/dc/optc/dcn20/dcn20_optc.h| 2 +-
.../amd/display/dc/optc/dcn30/dcn30_optc.c| 6 +-
.../amd/display/dc/optc/dcn30/dcn30_optc.h| 2 +-
.../amd/display/dc/optc/dcn31/dcn31_optc.c| 8 +--
.../amd/display/dc/optc/dcn314/dcn314_optc.c | 7 +-
.../amd/display/dc/optc/dcn32/dcn32_optc.c| 7 +-
.../amd/display/dc/optc/dcn35/dcn35_optc.c| 7 +-
.../amd/display/dc/optc/dcn401/dcn401_optc.c | 22 ++
20 files changed, 140 insertions(+), 106 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index fd03d7129ffa..fd624b1fee25 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -2110,12 +2110,19 @@ struct rect resource_get_odm_slice_src_rect(struct
pipe_ctx *pipe_ctx)
struct rect odm_slice_dst;
struct rect odm_slice_src;
struct pipe_ctx *opp_head = resource_get_opp_head(pipe_ctx);
+ struct output_pixel_processor *opp = opp_head->stream_res.opp;
uint32_t left_edge_extra_pixel_count;
odm_slice_dst = resource_get_odm_slice_dst_rect(opp_head);
odm_slice_src = odm_slice_dst;
- left_edge_extra_pixel_count = 0;
+ if (opp->funcs->opp_get_left_edge_extra_pixel_count)
+ left_edge_extra_pixel_count =
+ opp->funcs->opp_get_left_edge_extra_pixel_count(
+ opp,
pipe_ctx->stream->timing.pixel_encoding,
+ resource_is_pipe_type(opp_head,
OTG_MASTER));
+ else
+ left_edge_extra_pixel_count = 0;
odm_slice_src.x -= left_edge_extra_pixel_count;
odm_slice_src.width += left_edge_extra_pixel_count;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c
index fbf1b6370eb2..f5fe0cac7cb0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c
@@ -23,6 +23,7 @@
*
*/
+#include "core_types.h"
#include "dm_services.h"
#include "dcn20_opp.h"
#include "reg_helper.h"
@@ -350,19 +351,32 @@ bool opp2_dpg_is_pending(struct output_pixel_processor
*opp)
return (dpg_en == 1 && double_buffer_pending == 1);
}
-void opp2_program_left_edge_extra_pixel (
+void opp2_program_left_edge_extra_pixel(
struct output_pixel_processor *opp,
- bool count)
+ enum dc_pixel_encoding pixel_encoding,
+ bool is_primary)
{
struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp);
+ uint32_t count = opp2_get_left_edge_extra_pixel_count(opp,
pixel_encoding, is_primary);
- /* Specifies the number of extra left edge pixels that are supplied to
+ /*
+* Specifies the number of extra left edge pixels that are supplied to
* the 422 horizontal chroma sub-sample filter.
-* Note that when left edge pixel is not "0", fmt pixel encoding can be
in either 420 or 422 mode
-* */
+*/
REG_UPDATE(FMT_422_CONTROL, FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT, count);
}
+uint32_t opp2_get_left_edge_extra_pixel_count(struct output_pixel_processor
*opp,
+ enum dc_pixel_encoding pixel_encoding, bool is_primary)
+{
+ if ((pixel_encoding == PIXEL_ENCODING_YCBCR422 || pixel_encoding ==
PIXEL_ENCODING_YCBCR420) &&
+ !opp->ctx->dc->debug.force_chroma_subsampling_1tap &&
+ !is_primary)
+ return 1;
+ else
+ return 0;
+}
+
[PATCH 09/20] drm/amd/display: Add resource interfaces for get ODM slice rect
From: Wenjing Liu
[WHY]
We need an unified location to perform ODM slice rect calculation.
[HOW]
Add three interfaces for ODM slice rect/width calucaltion in resource.h
Reviewed-by: George Shen
Acked-by: Alex Hung
Signed-off-by: Wenjing Liu
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 137 ++
drivers/gpu/drm/amd/display/dc/inc/resource.h | 10 ++
2 files changed, 83 insertions(+), 64 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 532882ee7b2b..fd03d7129ffa 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -816,37 +816,6 @@ static struct rect shift_rec(const struct rect *rec_in,
int x, int y)
return rec_out;
}
-static struct rect calculate_odm_slice_in_timing_active(struct pipe_ctx
*pipe_ctx)
-{
- const struct dc_stream_state *stream = pipe_ctx->stream;
- int odm_slice_count = resource_get_odm_slice_count(pipe_ctx);
- int odm_slice_idx = resource_get_odm_slice_index(pipe_ctx);
- bool is_last_odm_slice = (odm_slice_idx + 1) == odm_slice_count;
- int h_active = stream->timing.h_addressable +
- stream->timing.h_border_left +
- stream->timing.h_border_right;
- int odm_slice_width = h_active / odm_slice_count;
- struct rect odm_rec;
- bool is_two_pixels_per_container =
-
pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(>timing);
-
- if ((odm_slice_width % 2) && is_two_pixels_per_container)
- odm_slice_width++;
-
- odm_rec.x = odm_slice_width * odm_slice_idx;
- odm_rec.width = is_last_odm_slice ?
- /* last slice width is the reminder of h_active */
- h_active - odm_slice_width * (odm_slice_count - 1) :
- /* odm slice width is the floor of h_active / count */
- odm_slice_width;
- odm_rec.y = 0;
- odm_rec.height = stream->timing.v_addressable +
- stream->timing.v_border_bottom +
- stream->timing.v_border_top;
-
- return odm_rec;
-}
-
static struct rect calculate_plane_rec_in_timing_active(
struct pipe_ctx *pipe_ctx,
const struct rect *rec_in)
@@ -1134,7 +1103,7 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx)
*/
struct rect plane_clip;
struct rect mpc_slice_of_plane_clip;
- struct rect odm_slice;
+ struct rect odm_slice_src;
struct rect overlapping_area;
plane_clip = calculate_plane_rec_in_timing_active(pipe_ctx,
@@ -1144,16 +1113,16 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx)
_ctx->stream->dst);
mpc_slice_of_plane_clip = calculate_mpc_slice_in_timing_active(
pipe_ctx, _clip);
- odm_slice = calculate_odm_slice_in_timing_active(pipe_ctx);
- overlapping_area = intersect_rec(_slice_of_plane_clip, _slice);
+ odm_slice_src = resource_get_odm_slice_src_rect(pipe_ctx);
+ overlapping_area = intersect_rec(_slice_of_plane_clip,
_slice_src);
if (overlapping_area.height > 0 &&
overlapping_area.width > 0) {
/* shift the overlapping area so it is with respect to current
-* ODM slice's position
+* ODM slice source's position
*/
pipe_ctx->plane_res.scl_data.recout = shift_rec(
_area,
- -odm_slice.x, -odm_slice.y);
+ -odm_slice_src.x, -odm_slice_src.y);
adjust_recout_for_visual_confirm(
_ctx->plane_res.scl_data.recout,
pipe_ctx);
@@ -1290,13 +1259,13 @@ static void calculate_inits_and_viewports(struct
pipe_ctx *pipe_ctx)
struct rect recout_clip_in_active_timing;
struct rect recout_clip_in_recout_dst;
struct rect overlap_in_active_timing;
- struct rect odm_slice = calculate_odm_slice_in_timing_active(pipe_ctx);
+ struct rect odm_slice_src = resource_get_odm_slice_src_rect(pipe_ctx);
int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
|| data->format == PIXEL_FORMAT_420BPP10) ? 2 :
1;
bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir;
recout_clip_in_active_timing = shift_rec(
- >recout, odm_slice.x, odm_slice.y);
+ >recout, odm_slice_src.x, odm_slice_src.y);
recout_dst_in_active_timing = calculate_plane_rec_in_timing_active(
pipe_ctx, _state->dst_rect);
overlap_in_active_timing = intersect_rec(_clip_in_active_timing,
@@ -1465,20 +1434,13 @@ static enum
[PATCH 08/20] drm/amd/display: Add COEF filter types for DCN401
From: Samson Tam
Add VERTICAL_BLUR_SCALE & HORIZONTAL_BLUR_SCALE types.
Reviewed-by: Jun Lei
Acked-by: Alex Hung
Signed-off-by: Samson Tam
---
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
index 696ccf96b847..d9a08cd160b3 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
@@ -56,7 +56,9 @@ enum dcn401_coef_filter_type_sel {
SCL_COEF_CHROMA_VERT_FILTER = 2,
SCL_COEF_CHROMA_HORZ_FILTER = 3,
SCL_COEF_ALPHA_VERT_FILTER = 4,
- SCL_COEF_ALPHA_HORZ_FILTER = 5
+ SCL_COEF_ALPHA_HORZ_FILTER = 5,
+ SCL_COEF_VERTICAL_BLUR_SCALE = SCL_COEF_ALPHA_VERT_FILTER,
+ SCL_COEF_HORIZONTAL_BLUR_SCALE = SCL_COEF_ALPHA_HORZ_FILTER
};
enum dscl_autocal_mode {
--
2.34.1
[PATCH 07/20] drm/amd/display: Refactor DCN401 DCCG into component directory
From: Revalla Hari Krishna
[WHY]
Clean up the code that requires dccg to be in its own component.
[HOW]
Move all files under newly created dccg dir and fix the makefiles.
Acked-by: Alex Hung
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Revalla Hari Krishna
---
drivers/gpu/drm/amd/display/dc/dccg/Makefile | 7 ++-
.../gpu/drm/amd/display/dc/{ => dccg}/dcn401/dcn401_dccg.c | 0
.../gpu/drm/amd/display/dc/{ => dccg}/dcn401/dcn401_dccg.h | 0
drivers/gpu/drm/amd/display/dc/dcn401/Makefile | 1 -
4 files changed, 6 insertions(+), 2 deletions(-)
rename drivers/gpu/drm/amd/display/dc/{ => dccg}/dcn401/dcn401_dccg.c (100%)
rename drivers/gpu/drm/amd/display/dc/{ => dccg}/dcn401/dcn401_dccg.h (100%)
diff --git a/drivers/gpu/drm/amd/display/dc/dccg/Makefile
b/drivers/gpu/drm/amd/display/dc/dccg/Makefile
index bfdce98768f1..1d5cf0f8e79d 100644
--- a/drivers/gpu/drm/amd/display/dc/dccg/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dccg/Makefile
@@ -95,4 +95,9 @@ AMD_DAL_DCCG_DCN35 = $(addprefix
$(AMDDALPATH)/dc/dccg/dcn35/,$(DCCG_DCN35))
AMD_DISPLAY_FILES += $(AMD_DAL_DCCG_DCN35)
###
-endif
\ No newline at end of file
+DCCG_DCN401 = dcn401_dccg.o
+
+AMD_DAL_DCCG_DCN401 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn401/,$(DCCG_DCN401))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_DCCG_DCN401)
+endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn401/dcn401_dccg.c
b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dcn401/dcn401_dccg.c
rename to drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
diff --git a/drivers/gpu/drm/amd/display/dc/dcn401/dcn401_dccg.h
b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
similarity index 100%
rename from drivers/gpu/drm/amd/display/dc/dcn401/dcn401_dccg.h
rename to drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h
diff --git a/drivers/gpu/drm/amd/display/dc/dcn401/Makefile
b/drivers/gpu/drm/amd/display/dc/dcn401/Makefile
index 2e15e639194d..73544559f41f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn401/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn401/Makefile
@@ -6,7 +6,6 @@ DCN401 += dcn401_dio_link_encoder.o
DCN401 += dcn401_dio_stream_encoder.o
DCN401 += dcn401_hubp.o
DCN401 += dcn401_mpc.o
-DCN401 += dcn401_dccg.o
DCN401 += dcn401_hubbub.o
AMD_DAL_DCN401 = $(addprefix $(AMDDALPATH)/dc/dcn401/,$(DCN401))
--
2.34.1
[PATCH 06/20] drm/amd/display: Fix 3dlut size for Fastloading on DCN401
From: Adam Nelson
[WHY]
After a non-3dlut test the MPCC_MCM_3DLUT_MODE::MPCC_MCM_3DLUT_SIZE is
incorrect.
[HOW]
Add register write to make valid.
Acked-by: Alex Hung
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Adam Nelson
---
drivers/gpu/drm/amd/display/dc/dcn401/dcn401_mpc.c| 8
drivers/gpu/drm/amd/display/dc/dcn401/dcn401_mpc.h| 5 +
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 3 +++
drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 1 +
4 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn401/dcn401_mpc.c
b/drivers/gpu/drm/amd/display/dc/dcn401/dcn401_mpc.c
index d6c99c6c2b35..37ab5a4eefc7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn401/dcn401_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn401/dcn401_mpc.c
@@ -297,6 +297,13 @@ void mpc401_program_lut_read_write_control(struct mpc
*mpc, const enum MCM_LUT_I
}
}
+void mpc401_program_3dlut_size(struct mpc *mpc, bool is_17x17x17, int mpcc_id)
+{
+ struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc);
+
+ REG_UPDATE(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_SIZE,
is_17x17x17 ? 0 : 1);
+}
+
static void program_gamut_remap(
struct mpc *mpc,
unsigned int mpcc_id,
@@ -615,6 +622,7 @@ static const struct mpc_funcs dcn401_mpc_funcs = {
.populate_lut = mpc401_populate_lut,
.program_lut_read_write_control = mpc401_program_lut_read_write_control,
.program_lut_mode = mpc401_program_lut_mode,
+ .program_3dlut_size = mpc401_program_3dlut_size,
};
diff --git a/drivers/gpu/drm/amd/display/dc/dcn401/dcn401_mpc.h
b/drivers/gpu/drm/amd/display/dc/dcn401/dcn401_mpc.h
index a8ef67695757..af44054c2477 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn401/dcn401_mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn401/dcn401_mpc.h
@@ -221,6 +221,11 @@ void mpc401_program_lut_read_write_control(
bool lut_bank_a,
int mpcc_id);
+void mpc401_program_3dlut_size(
+ struct mpc *mpc,
+ bool is_17x17x17,
+ int mpcc_id);
+
void mpc401_set_gamut_remap(
struct mpc *mpc,
int mpcc_id,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index 3b74c4a9c2a8..5b87186598e6 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -478,6 +478,7 @@ void dcn401_populate_mcm_luts(struct dc *dc,
enum MCM_LUT_XABLE shaper_xable = MCM_LUT_DISABLE;
enum MCM_LUT_XABLE lut3d_xable = MCM_LUT_DISABLE;
enum MCM_LUT_XABLE lut1d_xable = MCM_LUT_DISABLE;
+ bool is_17x17x17 = true;
dcn401_get_mcm_lut_xable_from_pipe_ctx(dc, pipe_ctx, _xable,
_xable, _xable);
@@ -543,6 +544,8 @@ void dcn401_populate_mcm_luts(struct dc *dc,
mpc->funcs->program_lut_read_write_control(mpc,
MCM_LUT_3DLUT, lut_bank_a, mpcc_id);
if (mpc->funcs->program_lut_mode)
mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT,
lut3d_xable, lut_bank_a, mpcc_id);
+ if (mpc->funcs->program_3dlut_size)
+ mpc->funcs->program_3dlut_size(mpc, is_17x17x17,
mpcc_id);
if (hubp->funcs->hubp_program_3dlut_fl_addr)
hubp->funcs->hubp_program_3dlut_fl_addr(hubp,
mcm_luts.lut3d_data.gpu_mem_params.addr);
switch (mcm_luts.lut3d_data.gpu_mem_params.layout) {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
index dd786600668f..34cf8efc5cb9 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
@@ -576,6 +576,7 @@ struct mpc_funcs {
void (*program_lut_read_write_control)(struct mpc *mpc, const enum
MCM_LUT_ID id, bool lut_bank_a, int mpcc_id);
void (*program_lut_mode)(struct mpc *mpc, const enum MCM_LUT_ID id,
const enum MCM_LUT_XABLE xable,
bool lut_bank_a, int mpcc_id);
+ void (*program_3dlut_size)(struct mpc *mpc, bool is_17x17x17, int
mpcc_id);
};
#endif
--
2.34.1
[PATCH 05/20] drm/amd/display: Fix write to non-existent reg on DCN401
From: Ilya Bakoulin
DP_DSC_CNTL no longer exists on DCN401.
Acked-by: Alex Hung
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Ilya Bakoulin
---
.../dc/dcn401/dcn401_dio_stream_encoder.c | 20 +++
1 file changed, 3 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn401/dcn401_dio_stream_encoder.c
b/drivers/gpu/drm/amd/display/dc/dcn401/dcn401_dio_stream_encoder.c
index 1c55ccede09b..090288305609 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn401/dcn401_dio_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn401/dcn401_dio_stream_encoder.c
@@ -372,21 +372,6 @@ static void enc401_stream_encoder_dp_unblank(
link->dc->link_srv->dp_trace_source_sequence(link,
DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM);
}
-/* Set DSC-related configuration.
- * dsc_mode: 0 disables DSC, other values enable DSC in specified format
- * sc_bytes_per_pixel: DP_DSC_BYTES_PER_PIXEL removed in DCN3x
- * dsc_slice_width: DP_DSC_SLICE_WIDTH removed in DCN3x
- */
-static void enc401_dp_set_dsc_config(struct stream_encoder *enc,
- enum optc_dsc_mode dsc_mode,
- uint32_t dsc_bytes_per_pixel,
- uint32_t dsc_slice_width)
-{
- struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
-
- REG_UPDATE(DP_DSC_CNTL, DP_DSC_MODE, dsc_mode == OPTC_DSC_DISABLED ? 0
: 1);
-}
-
/* this function read dsc related register fields to be logged later in
dcn10_log_hw_state
* into a dcn_dsc_state struct.
*/
@@ -395,7 +380,8 @@ static void enc401_read_state(struct stream_encoder *enc,
struct enc_state *s)
struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
//if dsc is enabled, continue to read
- REG_GET(DP_DSC_CNTL, DP_DSC_MODE, >dsc_mode);
+ REG_GET(DP_PIXEL_FORMAT, PIXEL_ENCODING_TYPE, >dsc_mode);
+
if (s->dsc_mode) {
REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_LINE_NUM,
>sec_gsp_pps_line_num);
@@ -770,7 +756,7 @@ static const struct stream_encoder_funcs
dcn401_str_enc_funcs = {
.dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format,
.enc_read_state = enc401_read_state,
- .dp_set_dsc_config = enc401_dp_set_dsc_config,
+ .dp_set_dsc_config = NULL,
.dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet,
.set_dynamic_metadata = enc401_set_dynamic_metadata,
.hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,
--
2.34.1
[PATCH 04/20] drm/amd/display: Remove USBC check for DCN32
From: Rodrigo Siqueira The CONNECTOR_ID_USBC check was removed to fix a regression, but it was re-introduced by accident. This commit drops the USBC that causes the regressions. Acked-by: Alex Hung Signed-off-by: Rodrigo Siqueira --- drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c index d9ff95cd2dbd..06907e8a4eda 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_link_encoder.c @@ -252,9 +252,6 @@ void dcn32_link_encoder_construct( enc10->base.features = *enc_features; - if (enc10->base.connector.id == CONNECTOR_ID_USBC) - enc10->base.features.flags.bits.DP_IS_USB_C = 1; - enc10->base.transmitter = init_data->transmitter; /* set the flag to indicate whether driver poll the I2C data pin -- 2.34.1
[PATCH 03/20] drm/amd/display: Remove unused code for some dc files
From: Rodrigo Siqueira
Cleanup unused code in DC.
Acked-by: Alex Hung
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 9 -
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 3 ---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h | 4
3 files changed, 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index d19c67205de6..0f20a3d96d93 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3614,9 +3614,6 @@ static void
commit_plane_for_stream_offload_fams2_flip(struct dc *dc,
for (i = 0; i < surface_count; i++) {
struct dc_plane_state *plane_state = srf_updates[i].surface;
- /* set offload flag so driver does not program address */
- plane_state->address.offload_flip = true;
-
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx =
>res_ctx.pipe_ctx[j];
@@ -3638,12 +3635,6 @@ static void
commit_plane_for_stream_offload_fams2_flip(struct dc *dc,
stream,
srf_updates,
surface_count);
-
- /* reset offload flip flag */
- for (i = 0; i < surface_count; i++) {
- struct dc_plane_state *plane_state = srf_updates[i].surface;
- plane_state->address.offload_flip = false;
- }
}
static void commit_planes_for_stream_fast(struct dc *dc,
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index 226285037b2b..959ae0df1e56 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -125,9 +125,6 @@ struct dc_plane_address {
union large_integer page_table_base;
uint8_t vmid;
- /* dc should use hw flip queue rather than directly programming the
surface address.
-* Value is determined on each flip. */
- bool offload_flip;
};
struct dc_size {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h
index 54f889cfd911..ce93003dae01 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h
@@ -1091,10 +1091,6 @@ void mpc3_power_on_ogam_lut(
void mpc3_init_mpcc(struct mpcc *mpcc, int mpcc_inst);
-void mpc3_mpc_init_single_inst(
- struct mpc *mpc,
- unsigned int mpcc_id);
-
enum dc_lut_mode mpc3_get_ogam_current(
struct mpc *mpc,
int mpcc_id);
--
2.34.1
[PATCH 02/20] drm/amd/display: Disable AC/DC codepath when unnecessary
From: Joshua Aberback
[WHY]
If there are no DC clock limits present, or if the DC limits are the same
as the AC limits, we can disable the AC/DC codepath as there won't be any
validation differences between the two modes.
[HOW]
When all DC power mode clock limits are the same as the max clock
values, there won't be any difference between AC mode and DC mode. Zero
out DC limits that equal max and provide a new cap to indicate the
presence of any non-zero DC mode limit. In summary:
- zero out DC limits that are the same as max clock value
- new dc cap to indicate the presence of DC mode limits
- set limits present if any clock has distinct AC and DC values from SMU
Acked-by: Alex Hung
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Joshua Aberback
---
.../dc/clk_mgr/dcn401/dcn401_clk_mgr.c| 28 ++-
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
.../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 12 +++-
3 files changed, 33 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
index 1cf750cfed66..bd74ff47fb37 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
@@ -180,7 +180,6 @@ static void dcn401_build_wm_range_table(struct clk_mgr
*clk_mgr)
void dcn401_init_clocks(struct clk_mgr *clk_mgr_base)
{
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
- unsigned int num_levels;
struct clk_limit_num_entries *num_entries_per_clk =
_mgr_base->bw_params->clk_table.num_entries_per_clk;
unsigned int i;
@@ -208,34 +207,43 @@ void dcn401_init_clocks(struct clk_mgr *clk_mgr_base)
_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz,
_entries_per_clk->num_dcfclk_levels);
clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz =
dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DCFCLK);
+ if (num_entries_per_clk->num_dcfclk_levels &&
clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz ==
+
clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_dcfclk_levels
- 1].dcfclk_mhz)
+ clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = 0;
/* SOCCLK */
dcn401_init_single_clock(clk_mgr, PPCLK_SOCCLK,
_mgr_base->bw_params->clk_table.entries[0].socclk_mhz,
_entries_per_clk->num_socclk_levels);
clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz =
dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_SOCCLK);
+ if (num_entries_per_clk->num_socclk_levels &&
clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz ==
+
clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_socclk_levels
- 1].socclk_mhz)
+ clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz = 0;
/* DTBCLK */
if (!clk_mgr->base.ctx->dc->debug.disable_dtb_ref_clk_switch) {
dcn401_init_single_clock(clk_mgr, PPCLK_DTBCLK,
_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz,
_entries_per_clk->num_dtbclk_levels);
- clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz =
- dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr,
PPCLK_DTBCLK);
+ clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz =
dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DTBCLK);
+ if (num_entries_per_clk->num_dtbclk_levels &&
clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz ==
+
clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_dtbclk_levels
- 1].dtbclk_mhz)
+ clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz = 0;
}
/* DISPCLK */
dcn401_init_single_clock(clk_mgr, PPCLK_DISPCLK,
_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz,
_entries_per_clk->num_dispclk_levels);
- num_levels = num_entries_per_clk->num_dispclk_levels;
clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz =
dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DISPCLK);
+ if (num_entries_per_clk->num_dispclk_levels &&
clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz ==
+
clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_dispclk_levels
- 1].dispclk_mhz)
+ clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = 0;
/* DPPCLK */
dcn401_init_single_clock(clk_mgr, PPCLK_DPPCLK,
_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz,
_entries_per_clk->num_dppclk_levels);
- num_levels = num_entries_per_clk->num_dppclk_levels;
if
[PATCH 01/20] drm/amd/display: Create dcn401_clk_mgr struct
From: Dillon Varone
Create dcn401 specific structure to encapsulate version specific
variables.
Acked-by: Alex Hung
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Dillon Varone
---
.../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 3 +--
.../dc/clk_mgr/dcn401/dcn401_clk_mgr.c| 23 ---
.../dc/clk_mgr/dcn401/dcn401_clk_mgr.h| 10
3 files changed, 26 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
index 5f67d159e1e2..f770828df149 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
@@ -367,14 +367,13 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx,
struct pp_smu_funcs *p
break;
case AMDGPU_FAMILY_GC_12_0_0: {
- struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr),
GFP_KERNEL);
+ struct clk_mgr_internal *clk_mgr =
dcn401_clk_mgr_construct(ctx, dccg);
if (clk_mgr == NULL) {
BREAK_TO_DEBUGGER();
return NULL;
}
- dcn401_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
return _mgr->base;
}
break;
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
index 7db7446ad91f..1cf750cfed66 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
@@ -935,14 +935,18 @@ static struct clk_mgr_funcs dcn401_funcs = {
.is_smu_present = dcn401_is_smu_present,
};
-void dcn401_clk_mgr_construct(
+struct clk_mgr_internal *dcn401_clk_mgr_construct(
struct dc_context *ctx,
- struct clk_mgr_internal *clk_mgr,
- struct pp_smu_funcs *pp_smu,
struct dccg *dccg)
{
struct clk_log_info log_info = {0};
+ struct dcn401_clk_mgr *clk_mgr401 = kzalloc(sizeof(struct
dcn401_clk_mgr), GFP_KERNEL);
+ struct clk_mgr_internal *clk_mgr;
+
+ if (!clk_mgr401)
+ return NULL;
+ clk_mgr = _mgr401->base;
clk_mgr->base.ctx = ctx;
clk_mgr->base.funcs = _funcs;
clk_mgr->regs = _mgr_regs_dcn401;
@@ -987,11 +991,24 @@ void dcn401_clk_mgr_construct(
clk_mgr->smu_present = false;
clk_mgr->base.bw_params = kzalloc(sizeof(*clk_mgr->base.bw_params),
GFP_KERNEL);
+ if (!clk_mgr->base.bw_params) {
+ BREAK_TO_DEBUGGER();
+ kfree(clk_mgr);
+ return NULL;
+ }
/* need physical address of table to give to PMFW */
clk_mgr->wm_range_table = dm_helpers_allocate_gpu_mem(clk_mgr->base.ctx,
DC_MEM_ALLOC_TYPE_GART, sizeof(WatermarksExternal_t),
_mgr->wm_range_table_addr);
+ if (!clk_mgr->wm_range_table) {
+ BREAK_TO_DEBUGGER();
+ kfree(clk_mgr->base.bw_params);
+ return NULL;
+ }
+
+ return _mgr401->base;
+
}
void dcn401_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h
index 496540ec1950..dad203de0dd4 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h
@@ -5,11 +5,13 @@
#ifndef __DCN401_CLK_MGR_H_
#define __DCN401_CLK_MGR_H_
+struct dcn401_clk_mgr {
+ struct clk_mgr_internal base;
+};
+
void dcn401_init_clocks(struct clk_mgr *clk_mgr_base);
-void dcn401_clk_mgr_construct(struct dc_context *ctx,
- struct clk_mgr_internal *clk_mgr,
- struct pp_smu_funcs *pp_smu,
+struct clk_mgr_internal *dcn401_clk_mgr_construct(struct dc_context *ctx,
struct dccg *dccg);
void dcn401_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
@@ -17,6 +19,4 @@ void dcn401_update_clocks_update_dpp_dto(struct
clk_mgr_internal *clk_mgr,
void dcn401_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr);
-
-
#endif /* __DCN401_CLK_MGR_H_ */
--
2.34.1
[PATCH 00/20] DC Patches May 08, 2024
This DC patchset brings improvements in multiple areas. In summary, we have:
* Fixes on DCN401, 3dlut and I2C
* Improvements on AC/DC, link rates, DSC and ODM slice rect and pipe
* Refactoring on code styles and unused code
Cc: Daniel Wheeler
Adam Nelson (1):
drm/amd/display: Fix 3dlut size for Fastloading on DCN401
Alvin Lee (1):
drm/amd/display: Don't offload flip if not only address update
Aric Cyr (1):
drm/amd/display: 3.2.285
Chris Park (1):
drm/amd/display: Reduce I2C speed to 95kHz in DCN401
Daniel Miess (1):
drm/amd/display: Enable SYMCLK gating in DCCG
Dillon Varone (2):
drm/amd/display: Create dcn401_clk_mgr struct
drm/amd/display: Refactor dcn401_update_clocks
Duncan Ma (1):
drm/amd/display: Read default boot options
Ethan Bitnun (1):
drm/amd/display: Find max flickerless instant vtotal delta
George Shen (1):
drm/amd/display: Check UHBR13.5 cap when determining max link cap
Ilya Bakoulin (1):
drm/amd/display: Fix write to non-existent reg on DCN401
Joshua Aberback (1):
drm/amd/display: Disable AC/DC codepath when unnecessary
Revalla Hari Krishna (1):
drm/amd/display: Refactor DCN401 DCCG into component directory
Rodrigo Siqueira (2):
drm/amd/display: Remove unused code for some dc files
drm/amd/display: Remove USBC check for DCN32
Samson Tam (1):
drm/amd/display: Add COEF filter types for DCN401
Sung Joon Kim (1):
drm/amd/display: Expand to higher link rates
Wenjing Liu (3):
drm/amd/display: Add resource interfaces for get ODM slice rect
drm/amd/display: Add left edge pixel for YCbCr422/420 + ODM pipe split
drm/amd/display: Allow higher DSC slice support for small timings on
dcn401
.../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 3 +-
.../amd/display/dc/clk_mgr/dcn401/dalsmc.h| 8 +-
.../dc/clk_mgr/dcn401/dcn401_clk_mgr.c| 574 +-
.../dc/clk_mgr/dcn401/dcn401_clk_mgr.h| 104 +++-
.../clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c | 80 ++-
.../clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h | 10 +
drivers/gpu/drm/amd/display/dc/core/dc.c | 13 +-
.../gpu/drm/amd/display/dc/core/dc_resource.c | 150 +++--
.../gpu/drm/amd/display/dc/core/dc_stream.c | 64 +-
drivers/gpu/drm/amd/display/dc/dc.h | 7 +-
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 3 -
.../gpu/drm/amd/display/dc/dc_stream_priv.h | 14 +
drivers/gpu/drm/amd/display/dc/dccg/Makefile | 7 +-
.../amd/display/dc/dccg/dcn35/dcn35_dccg.c| 102 ++--
.../dc/{ => dccg}/dcn401/dcn401_dccg.c| 0
.../dc/{ => dccg}/dcn401/dcn401_dccg.h| 0
.../gpu/drm/amd/display/dc/dcn20/dcn20_opp.c | 25 +-
.../gpu/drm/amd/display/dc/dcn20/dcn20_opp.h | 4 +-
.../drm/amd/display/dc/dcn201/dcn201_opp.c| 1 +
.../gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h | 4 -
.../display/dc/dcn32/dcn32_dio_link_encoder.c | 3 -
.../display/dc/dcn32/dcn32_resource_helpers.c | 2 +-
.../gpu/drm/amd/display/dc/dcn401/Makefile| 1 -
.../dc/dcn401/dcn401_dio_stream_encoder.c | 20 +-
.../drm/amd/display/dc/dcn401/dcn401_mpc.c| 8 +
.../drm/amd/display/dc/dcn401/dcn401_mpc.h| 5 +
.../drm/amd/display/dc/dml2/dml2_wrapper.h| 3 +
.../display/dc/dpp/dcn401/dcn401_dpp_dscl.c | 4 +-
.../amd/display/dc/dsc/dcn401/dcn401_dsc.c| 412 ++---
.../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 67 +-
.../amd/display/dc/hwss/dcn314/dcn314_hwseq.c | 4 +-
.../amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 8 +-
.../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 49 +-
.../amd/display/dc/hwss/dcn35/dcn35_hwseq.h | 2 +
.../amd/display/dc/hwss/dcn35/dcn35_init.c| 1 +
.../amd/display/dc/hwss/dcn351/dcn351_init.c | 1 +
.../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 63 +-
.../display/dc/hwss/hw_sequencer_private.h| 4 +
drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 7 +
drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 1 +
drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 7 +-
.../amd/display/dc/inc/hw/timing_generator.h | 2 +-
drivers/gpu/drm/amd/display/dc/inc/resource.h | 10 +
.../dc/link/protocols/link_dp_capability.c| 25 +-
.../amd/display/dc/optc/dcn20/dcn20_optc.c| 6 +-
.../amd/display/dc/optc/dcn20/dcn20_optc.h| 2 +-
.../amd/display/dc/optc/dcn30/dcn30_optc.c| 6 +-
.../amd/display/dc/optc/dcn30/dcn30_optc.h| 2 +-
.../amd/display/dc/optc/dcn31/dcn31_optc.c| 8 +-
.../amd/display/dc/optc/dcn314/dcn314_optc.c | 7 +-
.../amd/display/dc/optc/dcn32/dcn32_optc.c| 7 +-
.../amd/display/dc/optc/dcn35/dcn35_optc.c| 7 +-
.../amd/display/dc/optc/dcn401/dcn401_optc.c | 22 +-
.../dc/resource/dcn401/dcn401_resource.c | 4 +-
.../gpu/drm/amd/display/dmub/src/dmub_dcn35.c | 5 +-
.../gpu/drm/amd/display/include/dal_asic_id.h | 3 +
56 files changed, 1293 insertions(+), 668 deletions(-)
rename drivers/gpu/drm/amd/display/dc/{ => dccg}/dcn401/dcn401_dccg.c (100%)
rename
Re: [PATCH v2 01/12] drm/amdgpu, drm/radeon: Make I2C terminology more inclusive
On Tue, May 7, 2024 at 2:32 PM Easwar Hariharan wrote: > > On 5/3/2024 11:13 AM, Easwar Hariharan wrote: > > I2C v7, SMBus 3.2, and I3C 1.1.1 specifications have replaced "master/slave" > > with more appropriate terms. Inspired by and following on to Wolfram's > > series to fix drivers/i2c/[1], fix the terminology for users of > > I2C_ALGOBIT bitbanging interface, now that the approved verbiage exists > > in the specification. > > > > Compile tested, no functionality changes intended > > > > [1]: > > https://lore.kernel.org/all/20240322132619.6389-1-wsa+rene...@sang-engineering.com/ > > > > Signed-off-by: Easwar Hariharan > > --- > > .../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 8 +++--- > > drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c | 10 +++ > > drivers/gpu/drm/amd/amdgpu/atombios_i2c.c | 8 +++--- > > drivers/gpu/drm/amd/amdgpu/atombios_i2c.h | 2 +- > > drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c| 20 ++--- > > .../gpu/drm/amd/display/dc/bios/bios_parser.c | 2 +- > > .../drm/amd/display/dc/bios/bios_parser2.c| 2 +- > > .../drm/amd/display/dc/core/dc_link_exports.c | 4 +-- > > drivers/gpu/drm/amd/display/dc/dc.h | 2 +- > > drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c | 4 +-- > > .../display/include/grph_object_ctrl_defs.h | 2 +- > > drivers/gpu/drm/amd/include/atombios.h| 2 +- > > drivers/gpu/drm/amd/include/atomfirmware.h| 26 - > > .../powerplay/hwmgr/vega20_processpptables.c | 4 +-- > > .../amd/pm/powerplay/inc/smu11_driver_if.h| 2 +- > > .../inc/pmfw_if/smu11_driver_if_arcturus.h| 2 +- > > .../inc/pmfw_if/smu11_driver_if_navi10.h | 2 +- > > .../pmfw_if/smu11_driver_if_sienna_cichlid.h | 2 +- > > .../inc/pmfw_if/smu13_driver_if_aldebaran.h | 2 +- > > .../inc/pmfw_if/smu13_driver_if_v13_0_0.h | 2 +- > > .../inc/pmfw_if/smu13_driver_if_v13_0_7.h | 2 +- > > .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 4 +-- > > .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 8 +++--- > > drivers/gpu/drm/radeon/atombios.h | 16 +-- > > drivers/gpu/drm/radeon/atombios_i2c.c | 4 +-- > > drivers/gpu/drm/radeon/radeon_combios.c | 28 +-- > > drivers/gpu/drm/radeon/radeon_i2c.c | 10 +++ > > drivers/gpu/drm/radeon/radeon_mode.h | 6 ++-- > > 28 files changed, 93 insertions(+), 93 deletions(-) > > > > > > Hello Christian, Daniel, David, others, > > Could you re-review v2 since the feedback provided in v0 [1] has now been > addressed? I can send v3 with > all other feedback and signoffs from the other maintainers incorporated when > I have something for amdgpu > and radeon. This seems like a lot of churn. Additionally, a bunch of these headers are shared with other OSes, so it's possible some of the changes may end up getting reverted accidently when we sync up or we may add new headers in new code with the old nomenclature and then we'd need to make sure to adjust it to make sure everything was aligned again. I would just as soon leave things as is, but I'm open to acking them if there is a strong desire to update things. Alex
[PATCH 3/3] drm/amd/amdgpu: Enable ISP in amdgpu_discovery
Enable ISP for ISP V4.1.0 and V4.1.1 in amdgpu_discovery.
Signed-off-by: Pratap Nirujogi
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 22 +++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 6586feab8c2c..82d064adaa49 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -107,6 +107,7 @@
#include "jpeg_v5_0_0.h"
#include "amdgpu_vpe.h"
+#include "amdgpu_isp.h"
#define FIRMWARE_IP_DISCOVERY "amdgpu/ip_discovery.bin"
MODULE_FIRMWARE(FIRMWARE_IP_DISCOVERY);
@@ -682,6 +683,10 @@ static void
amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev,
adev->sdma.sdma_mask &=
~(1U << harvest_info->list[i].number_instance);
break;
+ case ISP_HWID:
+ adev->isp.harvest_config |=
+ ~(1U << harvest_info->list[i].number_instance);
+ break;
default:
break;
}
@@ -2303,6 +2308,20 @@ static int
amdgpu_discovery_set_umsch_mm_ip_blocks(struct amdgpu_device *adev)
return 0;
}
+static int amdgpu_discovery_set_isp_ip_blocks(struct amdgpu_device *adev)
+{
+ switch (amdgpu_ip_version(adev, ISP_HWIP, 0)) {
+ case IP_VERSION(4, 1, 0):
+ case IP_VERSION(4, 1, 1):
+ amdgpu_device_ip_block_add(adev, _ip_block);
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
{
int r;
@@ -2829,6 +2848,9 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device
*adev)
if (r)
return r;
+ r = amdgpu_discovery_set_isp_ip_blocks(adev);
+ if (r)
+ return r;
return 0;
}
--
2.34.1
[PATCH 2/3] drm/amd/amdgpu: Add ISP driver support
Add the isp driver in amdgpu to support ISP device on the APUs that
supports ISP IP block. ISP hw block is used for camera front-end, pre
and post processing operations.
Signed-off-by: Pratap Nirujogi
---
drivers/gpu/drm/amd/amdgpu/Makefile | 3 +
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 +
drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c | 298 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_isp.h | 54
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 5 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 1 +
7 files changed, 368 insertions(+)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_isp.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index de7b76327f5b..12ba76025cb7 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -324,4 +324,7 @@ amdgpu-y += $(AMD_DISPLAY_FILES)
endif
+# add isp block
+amdgpu-y += amdgpu_isp.o
+
obj-$(CONFIG_DRM_AMDGPU)+= amdgpu.o
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index eb60d28a3a13..6d7f9ef53269 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -112,6 +112,7 @@
#include "amdgpu_xcp.h"
#include "amdgpu_seq64.h"
#include "amdgpu_reg_state.h"
+#include "amdgpu_isp.h"
#define MAX_GPU_INSTANCE 64
@@ -1045,6 +1046,9 @@ struct amdgpu_device {
/* display related functionality */
struct amdgpu_display_manager dm;
+ /* isp */
+ struct amdgpu_isp isp;
+
/* mes */
boolenable_mes;
boolenable_mes_kiq;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
new file mode 100644
index ..dcc01a339a43
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
@@ -0,0 +1,298 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "amdgpu_smu.h"
+#include "atom.h"
+#include "amdgpu_isp.h"
+#include "smu_internal.h"
+#include "smu_v11_5_ppsmc.h"
+#include "smu_v11_5_pmfw.h"
+
+#define mmDAGB0_WRCLI5_V4_10x6811C
+#define mmDAGB0_WRCLI9_V4_10x6812C
+#define mmDAGB0_WRCLI10_V4_1 0x68130
+#define mmDAGB0_WRCLI14_V4_1 0x68140
+#define mmDAGB0_WRCLI19_V4_1 0x68154
+#define mmDAGB0_WRCLI20_V4_1 0x68158
+
+static int isp_sw_init(void *handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ pr_info("%s called adev %p\n", __func__, adev);
+
+ adev->isp.parent = adev->dev;
+
+ adev->isp.cgs_device = amdgpu_cgs_create_device(adev);
+ if (!adev->isp.cgs_device)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int isp_sw_fini(void *handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ pr_info("%s called adev %p\n", __func__, adev);
+
+ if (adev->isp.cgs_device)
+ amdgpu_cgs_destroy_device(adev->isp.cgs_device);
+
+ return 0;
+}
+
+/**
+ * isp_hw_init - start and test isp block
+ *
+ * @adev: amdgpu_device pointer
+ *
+ */
+static int isp_hw_init(void *handle)
+{
+ int r;
+ u64 isp_base;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ const struct amdgpu_ip_block *ip_block =
+ amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_ISP);
+
+ if (!ip_block)
+ return -EINVAL;
+
+ if (adev->rmmio_size == 0 || adev->rmmio_size < 0x5289)
+ return
[PATCH 1/3] drm/amd/amdgpu: Add ISP support to amdgpu_discovery
ISP hw block is supported in some of the AMD GPU versions, add support
to discover ISP IP in amdgpu_discovery.
Signed-off-by: Pratap Nirujogi
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
drivers/gpu/drm/amd/include/amd_shared.h | 1 +
3 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 8bb8b414d511..eb60d28a3a13 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -718,6 +718,7 @@ enum amd_hw_ip_block_type {
XGMI_HWIP,
DCI_HWIP,
PCIE_HWIP,
+ ISP_HWIP,
MAX_HWIP
};
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index ece462f8a324..6586feab8c2c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -226,6 +226,7 @@ static int hw_id_map[MAX_HWIP] = {
[DCI_HWIP] = DCI_HWID,
[PCIE_HWIP] = PCIE_HWID,
[VPE_HWIP] = VPE_HWID,
+ [ISP_HWIP] = ISP_HWID,
};
static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device
*adev, uint8_t *binary)
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h
b/drivers/gpu/drm/amd/include/amd_shared.h
index 36ee9d3d6d9c..8bc2134cdd6b 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -105,6 +105,7 @@ enum amd_ip_block_type {
AMD_IP_BLOCK_TYPE_JPEG,
AMD_IP_BLOCK_TYPE_VPE,
AMD_IP_BLOCK_TYPE_UMSCH_MM,
+ AMD_IP_BLOCK_TYPE_ISP,
AMD_IP_BLOCK_TYPE_NUM,
};
--
2.34.1
Re: [PATCH 2/5] drm/amdgpu: Use drm_crtc_vblank_crtc()
On Mon, Apr 8, 2024 at 3:06 PM Ville Syrjala
wrote:
>
> From: Ville Syrjälä
>
> Replace the open coded drm_crtc_vblank_crtc() with the real
> thing.
>
> Cc: Alex Deucher
> Cc: "Christian König"
> Cc: "Pan, Xinhui"
> Cc: amd-gfx@lists.freedesktop.org
> Signed-off-by: Ville Syrjälä
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 8 ++--
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
> 2 files changed, 3 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
> index 8baa2e0935cc..258703145161 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
> @@ -65,9 +65,7 @@ static enum hrtimer_restart
> amdgpu_vkms_vblank_simulate(struct hrtimer *timer)
>
> static int amdgpu_vkms_enable_vblank(struct drm_crtc *crtc)
> {
> - struct drm_device *dev = crtc->dev;
> - unsigned int pipe = drm_crtc_index(crtc);
> - struct drm_vblank_crtc *vblank = >vblank[pipe];
> + struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);
> struct amdgpu_vkms_output *out = drm_crtc_to_amdgpu_vkms_output(crtc);
> struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
>
> @@ -91,10 +89,8 @@ static bool amdgpu_vkms_get_vblank_timestamp(struct
> drm_crtc *crtc,
> ktime_t *vblank_time,
> bool in_vblank_irq)
> {
> - struct drm_device *dev = crtc->dev;
> - unsigned int pipe = crtc->index;
> struct amdgpu_vkms_output *output =
> drm_crtc_to_amdgpu_vkms_output(crtc);
> - struct drm_vblank_crtc *vblank = >vblank[pipe];
> + struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);
> struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
>
> if (!READ_ONCE(vblank->enabled)) {
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 71d2d44681b2..662d2d83473b 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -528,7 +528,7 @@ static void dm_vupdate_high_irq(void *interrupt_params)
> if (acrtc) {
> vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
> drm_dev = acrtc->base.dev;
> - vblank = _dev->vblank[acrtc->base.index];
> + vblank = drm_crtc_vblank_crtc(>base);
> previous_timestamp =
> atomic64_read(_params->previous_timestamp);
> frame_duration_ns = vblank->time - previous_timestamp;
>
> --
> 2.43.2
>
Re: [PATCH] drm/amdgpu: Fix comparison in amdgpu_res_cpu_visible
On Wed, May 8, 2024 at 9:25 AM Michel Dänzer wrote:
>
> From: Michel Dänzer
>
> It incorrectly claimed a resource isn't CPU visible if it's located at
> the very end of CPU visible VRAM.
>
> Fixes: a6ff969fe9 ("drm/amdgpu: fix visible VRAM handling during faults")
> Reported-and-Tested-by: Jeremy Day
> Signed-off-by: Michel Dänzer
Reviewed-by: Alex Deucher
and applied. Thanks!
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index 109fe557a02b..29c197c00018 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -427,7 +427,7 @@ bool amdgpu_res_cpu_visible(struct amdgpu_device *adev,
>
> amdgpu_res_first(res, 0, res->size, );
> while (cursor.remaining) {
> - if ((cursor.start + cursor.size) >=
> adev->gmc.visible_vram_size)
> + if ((cursor.start + cursor.size) >
> adev->gmc.visible_vram_size)
> return false;
> amdgpu_res_next(, cursor.size);
> }
> --
> 2.43.0
>
[PATCH] drm/amdgpu: Fix comparison in amdgpu_res_cpu_visible
From: Michel Dänzer
It incorrectly claimed a resource isn't CPU visible if it's located at
the very end of CPU visible VRAM.
Fixes: a6ff969fe9 ("drm/amdgpu: fix visible VRAM handling during faults")
Reported-and-Tested-by: Jeremy Day
Signed-off-by: Michel Dänzer
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 109fe557a02b..29c197c00018 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -427,7 +427,7 @@ bool amdgpu_res_cpu_visible(struct amdgpu_device *adev,
amdgpu_res_first(res, 0, res->size, );
while (cursor.remaining) {
- if ((cursor.start + cursor.size) >= adev->gmc.visible_vram_size)
+ if ((cursor.start + cursor.size) > adev->gmc.visible_vram_size)
return false;
amdgpu_res_next(, cursor.size);
}
--
2.43.0
Re: [PATCH 07/11] drm/gma500: Use fbdev client helpers
On Tue, May 7, 2024 at 2:04 PM Thomas Zimmermann wrote:
>
> Implement struct drm_client_funcs with the respective helpers and
> remove the custom code from the emulation. The generic helpers are
> equivalent in functionality.
>
> Signed-off-by: Thomas Zimmermann
Acked-by: Patrik Jakobsson
> ---
> drivers/gpu/drm/gma500/fbdev.c | 58 ++
> 1 file changed, 3 insertions(+), 55 deletions(-)
>
> diff --git a/drivers/gpu/drm/gma500/fbdev.c b/drivers/gpu/drm/gma500/fbdev.c
> index 98b44974d42dd..8a6cb47e83f8f 100644
> --- a/drivers/gpu/drm/gma500/fbdev.c
> +++ b/drivers/gpu/drm/gma500/fbdev.c
> @@ -8,7 +8,6 @@
> #include
> #include
>
> -#include
> #include
> #include
> #include
> @@ -252,63 +251,12 @@ static const struct drm_fb_helper_funcs
> psb_fbdev_fb_helper_funcs = {
> };
>
> /*
> - * struct drm_client_funcs and setup code
> + * struct drm_client_funcs
> */
>
> -static void psb_fbdev_client_unregister(struct drm_client_dev *client)
> -{
> - struct drm_fb_helper *fb_helper = drm_fb_helper_from_client(client);
> -
> - if (fb_helper->info) {
> - drm_fb_helper_unregister_info(fb_helper);
> - } else {
> - drm_fb_helper_unprepare(fb_helper);
> - drm_client_release(_helper->client);
> - kfree(fb_helper);
> - }
> -}
> -
> -static int psb_fbdev_client_restore(struct drm_client_dev *client)
> -{
> - drm_fb_helper_lastclose(client->dev);
> -
> - return 0;
> -}
> -
> -static int psb_fbdev_client_hotplug(struct drm_client_dev *client)
> -{
> - struct drm_fb_helper *fb_helper = drm_fb_helper_from_client(client);
> - struct drm_device *dev = client->dev;
> - int ret;
> -
> - if (dev->fb_helper)
> - return drm_fb_helper_hotplug_event(dev->fb_helper);
> -
> - ret = drm_fb_helper_init(dev, fb_helper);
> - if (ret)
> - goto err_drm_err;
> -
> - if (!drm_drv_uses_atomic_modeset(dev))
> - drm_helper_disable_unused_functions(dev);
> -
> - ret = drm_fb_helper_initial_config(fb_helper);
> - if (ret)
> - goto err_drm_fb_helper_fini;
> -
> - return 0;
> -
> -err_drm_fb_helper_fini:
> - drm_fb_helper_fini(fb_helper);
> -err_drm_err:
> - drm_err(dev, "Failed to setup gma500 fbdev emulation (ret=%d)\n",
> ret);
> - return ret;
> -}
> -
> static const struct drm_client_funcs psb_fbdev_client_funcs = {
> - .owner = THIS_MODULE,
> - .unregister = psb_fbdev_client_unregister,
> - .restore= psb_fbdev_client_restore,
> - .hotplug= psb_fbdev_client_hotplug,
> + .owner = THIS_MODULE,
> + DRM_FBDEV_HELPER_CLIENT_FUNCS,
> };
>
> void psb_fbdev_setup(struct drm_psb_private *dev_priv)
> --
> 2.44.0
>
Re: [PATCH] drm/amdgpu: Fix truncation by resizing ucode_prefix in imu_v12_0_init_microcode
On 5/7/2024 10:14 PM, Srinivasan Shanmugam wrote:
> This commit fixes potential truncation when writing the string _imu.bin
> into the fw_name buffer in the imu_v12_0_init_microcode function in the
> imu_v12_0.c file
>
> The ucode_prefix size was reduced from 30 to 15 to ensure the snprintf
> function does not exceed the size of the fw_name buffer.
>
> Thus fixing the below with gcc W=1:
> drivers/gpu/drm/amd/amdgpu/imu_v12_0.c: In function
> ‘imu_v12_0_init_microcode’:
> drivers/gpu/drm/amd/amdgpu/imu_v12_0.c:51:54: warning: ‘_imu.bin’ directive
> output may be truncated writing 8 bytes into a region of size between 4 and
> 33 [-Wformat-truncation=]
>51 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_imu.bin",
> ucode_prefix);
> | ^~~~
> drivers/gpu/drm/amd/amdgpu/imu_v12_0.c:51:9: note: ‘snprintf’ output between
> 16 and 45 bytes into a destination of size 40
>51 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_imu.bin",
> ucode_prefix);
> |
> ^
>
> Cc: Lijo Lazar
> Cc: Christian König
> Cc: Alex Deucher
> Signed-off-by: Srinivasan Shanmugam
Reviewed-by: Lijo Lazar
Thanks,
Lijo
> ---
> drivers/gpu/drm/amd/amdgpu/imu_v12_0.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c
> b/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c
> index ec2a4613567a..032ae12b2be2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c
> @@ -39,7 +39,7 @@ MODULE_FIRMWARE("amdgpu/gc_12_0_1_imu.bin");
> static int imu_v12_0_init_microcode(struct amdgpu_device *adev)
> {
> char fw_name[40];
> - char ucode_prefix[30];
> + char ucode_prefix[15];
> int err;
> const struct imu_firmware_header_v1_0 *imu_hdr;
> struct amdgpu_firmware_info *info = NULL;
Re: [PATCH] drm/amdgpu: Fix buffer size to prevent truncation in gfx_v12_0_init_microcode
On 5/7/2024 10:14 PM, Srinivasan Shanmugam wrote:
> This commit addresses multiple warnings in the gfx_v12_0_init_microcode
> function in the gfx_v12_0.c file. The warnings were related to potential
> truncation when writing the strings _pfp.bin, _me.bin, _rlc.bin, and
> _mec.bin into the fw_name buffer.
>
> This commit fixes multiple potential truncations when writing the
> strings _pfp.bin, _me.bin, _rlc.bin, and _mec.bin into the fw_name
> buffer in the gfx_v12_0_init_microcode function in the gfx_v12_0.c file
>
> The ucode_prefix size was reduced from 30 to 15 to ensure the snprintf
> function does not exceed the size of the fw_name buffer.
>
> Thus fixing the below with gcc W=1:
> drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c: In function ‘gfx_v12_0_early_init’:
> drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c:421:54: warning: ‘_pfp.bin’ directive
> output may be truncated writing 8 bytes into a region of size between 4 and
> 33 [-Wformat-truncation=]
> 421 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin",
> ucode_prefix);
> | ^~~~
> drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c:421:9: note: ‘snprintf’ output between
> 16 and 45 bytes into a destination of size 40
> 421 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin",
> ucode_prefix);
> |
> ^
> drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c:428:54: warning: ‘_me.bin’ directive
> output may be truncated writing 7 bytes into a region of size between 4 and
> 33 [-Wformat-truncation=]
> 428 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin",
> ucode_prefix);
> | ^~~
> drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c:428:9: note: ‘snprintf’ output between
> 15 and 44 bytes into a destination of size 40
> 428 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin",
> ucode_prefix);
> |
> ^~~~
> drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c:436:62: warning: ‘_rlc.bin’ directive
> output may be truncated writing 8 bytes into a region of size between 4 and
> 33 [-Wformat-truncation=]
> 436 | snprintf(fw_name, sizeof(fw_name),
> "amdgpu/%s_rlc.bin", ucode_prefix);
> | ^~~~
> drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c:436:17: note: ‘snprintf’ output
> between 16 and 45 bytes into a destination of size 40
> 436 | snprintf(fw_name, sizeof(fw_name),
> "amdgpu/%s_rlc.bin", ucode_prefix);
> |
> ^
> drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c:448:54: warning: ‘_mec.bin’ directive
> output may be truncated writing 8 bytes into a region of size between 4 and
> 33 [-Wformat-truncation=]
> 448 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin",
> ucode_prefix);
> | ^~~~
> drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c:448:9: note: ‘snprintf’ output between
> 16 and 45 bytes into a destination of size 40
> 448 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin",
> ucode_prefix);
> |
> ^
>
> Cc: Lijo Lazar
> Cc: Christian König
> Cc: Alex Deucher
> Signed-off-by: Srinivasan Shanmugam
Reviewed-by: Lijo Lazar
Thanks,
Lijo
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> index b53ca25012e6..b6e5a2230622 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> @@ -408,7 +408,7 @@ static int gfx_v12_0_init_toc_microcode(struct
> amdgpu_device *adev, const char *
> static int gfx_v12_0_init_microcode(struct amdgpu_device *adev)
> {
> char fw_name[40];
> - char ucode_prefix[30];
> + char ucode_prefix[15];
> int err;
> const struct rlc_firmware_header_v2_0 *rlc_hdr;
> uint16_t version_major;
Re: [patch] problems with "fix visible VRAM handling during faults"
Am 08.05.24 um 12:17 schrieb Michel Dänzer:
On 2024-05-07 18:39, Jeremy Day wrote:
This is just to report that I've had usually well-behaved applications
sometimes having problems with memory access violations since kernel
version 6.9-rc5. This past weekend I stumbled across a way to reliably
reproduce the problem in the form of a Skyrim save file which causes a
crash shortly after loading the game on affected kernels.
Things go back to running smoothly only if I revert one of the changes
in 5th April's "[PATCH] drm/amdgpu: fix visible VRAM handling during
faults" as follows.
Patch is against v6.9-rc7. It restores the check for partially
visible-to-cpu memory in amdgpu_bo_fault_reserve_notify. Things
seem stable again with this change.
Does this instead of your patch help by any chance?
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 109fe557a02b..29c197c00018 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -427,7 +427,7 @@ bool amdgpu_res_cpu_visible(struct amdgpu_device *adev,
amdgpu_res_first(res, 0, res->size, );
while (cursor.remaining) {
- if ((cursor.start + cursor.size) >= adev->gmc.visible_vram_size)
+ if ((cursor.start + cursor.size) > adev->gmc.visible_vram_size)
Oh, good catch. Yes that might be it.
Thanks a lot,
Christian.
return false;
amdgpu_res_next(, cursor.size);
}
Re: [patch] problems with "fix visible VRAM handling during faults"
On 2024-05-07 18:39, Jeremy Day wrote:
> This is just to report that I've had usually well-behaved applications
> sometimes having problems with memory access violations since kernel
> version 6.9-rc5. This past weekend I stumbled across a way to reliably
> reproduce the problem in the form of a Skyrim save file which causes a
> crash shortly after loading the game on affected kernels.
>
> Things go back to running smoothly only if I revert one of the changes
> in 5th April's "[PATCH] drm/amdgpu: fix visible VRAM handling during
> faults" as follows.
>
> Patch is against v6.9-rc7. It restores the check for partially
> visible-to-cpu memory in amdgpu_bo_fault_reserve_notify. Things
> seem stable again with this change.
Does this instead of your patch help by any chance?
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 109fe557a02b..29c197c00018 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -427,7 +427,7 @@ bool amdgpu_res_cpu_visible(struct amdgpu_device *adev,
amdgpu_res_first(res, 0, res->size, );
while (cursor.remaining) {
- if ((cursor.start + cursor.size) >= adev->gmc.visible_vram_size)
+ if ((cursor.start + cursor.size) > adev->gmc.visible_vram_size)
return false;
amdgpu_res_next(, cursor.size);
}
--
Earthling Michel Dänzer| https://redhat.com
Libre software enthusiast | Mesa and Xwayland developer
Re: [PATCH 2/5] drm/amdgpu: Use drm_crtc_vblank_crtc()
On Mon, 08 Apr 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Replace the open coded drm_crtc_vblank_crtc() with the real
> thing.
>
> Cc: Alex Deucher
> Cc: "Christian König"
> Cc: "Pan, Xinhui"
> Cc: amd-gfx@lists.freedesktop.org
> Signed-off-by: Ville Syrjälä
FWIW,
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 8 ++--
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
> 2 files changed, 3 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
> index 8baa2e0935cc..258703145161 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
> @@ -65,9 +65,7 @@ static enum hrtimer_restart
> amdgpu_vkms_vblank_simulate(struct hrtimer *timer)
>
> static int amdgpu_vkms_enable_vblank(struct drm_crtc *crtc)
> {
> - struct drm_device *dev = crtc->dev;
> - unsigned int pipe = drm_crtc_index(crtc);
> - struct drm_vblank_crtc *vblank = >vblank[pipe];
> + struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);
> struct amdgpu_vkms_output *out = drm_crtc_to_amdgpu_vkms_output(crtc);
> struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
>
> @@ -91,10 +89,8 @@ static bool amdgpu_vkms_get_vblank_timestamp(struct
> drm_crtc *crtc,
>ktime_t *vblank_time,
>bool in_vblank_irq)
> {
> - struct drm_device *dev = crtc->dev;
> - unsigned int pipe = crtc->index;
> struct amdgpu_vkms_output *output =
> drm_crtc_to_amdgpu_vkms_output(crtc);
> - struct drm_vblank_crtc *vblank = >vblank[pipe];
> + struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);
> struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
>
> if (!READ_ONCE(vblank->enabled)) {
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 71d2d44681b2..662d2d83473b 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -528,7 +528,7 @@ static void dm_vupdate_high_irq(void *interrupt_params)
> if (acrtc) {
> vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
> drm_dev = acrtc->base.dev;
> - vblank = _dev->vblank[acrtc->base.index];
> + vblank = drm_crtc_vblank_crtc(>base);
> previous_timestamp =
> atomic64_read(_params->previous_timestamp);
> frame_duration_ns = vblank->time - previous_timestamp;
--
Jani Nikula, Intel
Re: [PATCH] drm/buddy: Fix the range bias clear memory allocation issue
On Wed, May 08, 2024 at 12:27:20PM +0530, Arunpravin Paneer Selvam wrote:
> Problem statement: During the system boot time, an application request
> for the bulk volume of cleared range bias memory when the clear_avail
> is zero, we dont fallback into normal allocation method as we had an
> unnecessary clear_avail check which prevents the fallback method leads
> to fb allocation failure following system goes into unresponsive state.
>
> Solution: Remove the unnecessary clear_avail check in the range bias
> allocation function.
>
> Signed-off-by: Arunpravin Paneer Selvam
> Fixes: 96950929eb23 ("drm/buddy: Implement tracking clear page feature")
> Reviewed-by: Matthew Auld
> ---
> drivers/gpu/drm/drm_buddy.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Can you please also add a kunit test case to exercise this corner case and
make sure it stays fixed?
Thanks, Sima
>
> diff --git a/drivers/gpu/drm/drm_buddy.c b/drivers/gpu/drm/drm_buddy.c
> index 284ebae71cc4..831929ac95eb 100644
> --- a/drivers/gpu/drm/drm_buddy.c
> +++ b/drivers/gpu/drm/drm_buddy.c
> @@ -574,7 +574,7 @@ __drm_buddy_alloc_range_bias(struct drm_buddy *mm,
>
> block = __alloc_range_bias(mm, start, end, order,
> flags, fallback);
> - if (IS_ERR(block) && mm->clear_avail)
> + if (IS_ERR(block))
> return __alloc_range_bias(mm, start, end, order,
> flags, !fallback);
>
> --
> 2.25.1
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
Re: [PATCH v2 01/12] drm/amdgpu, drm/radeon: Make I2C terminology more inclusive
On 5/3/2024 11:13 AM, Easwar Hariharan wrote: > I2C v7, SMBus 3.2, and I3C 1.1.1 specifications have replaced "master/slave" > with more appropriate terms. Inspired by and following on to Wolfram's > series to fix drivers/i2c/[1], fix the terminology for users of > I2C_ALGOBIT bitbanging interface, now that the approved verbiage exists > in the specification. > > Compile tested, no functionality changes intended > > [1]: > https://lore.kernel.org/all/20240322132619.6389-1-wsa+rene...@sang-engineering.com/ > > Signed-off-by: Easwar Hariharan > --- > .../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 8 +++--- > drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c | 10 +++ > drivers/gpu/drm/amd/amdgpu/atombios_i2c.c | 8 +++--- > drivers/gpu/drm/amd/amdgpu/atombios_i2c.h | 2 +- > drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c| 20 ++--- > .../gpu/drm/amd/display/dc/bios/bios_parser.c | 2 +- > .../drm/amd/display/dc/bios/bios_parser2.c| 2 +- > .../drm/amd/display/dc/core/dc_link_exports.c | 4 +-- > drivers/gpu/drm/amd/display/dc/dc.h | 2 +- > drivers/gpu/drm/amd/display/dc/dce/dce_i2c.c | 4 +-- > .../display/include/grph_object_ctrl_defs.h | 2 +- > drivers/gpu/drm/amd/include/atombios.h| 2 +- > drivers/gpu/drm/amd/include/atomfirmware.h| 26 - > .../powerplay/hwmgr/vega20_processpptables.c | 4 +-- > .../amd/pm/powerplay/inc/smu11_driver_if.h| 2 +- > .../inc/pmfw_if/smu11_driver_if_arcturus.h| 2 +- > .../inc/pmfw_if/smu11_driver_if_navi10.h | 2 +- > .../pmfw_if/smu11_driver_if_sienna_cichlid.h | 2 +- > .../inc/pmfw_if/smu13_driver_if_aldebaran.h | 2 +- > .../inc/pmfw_if/smu13_driver_if_v13_0_0.h | 2 +- > .../inc/pmfw_if/smu13_driver_if_v13_0_7.h | 2 +- > .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 4 +-- > .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 8 +++--- > drivers/gpu/drm/radeon/atombios.h | 16 +-- > drivers/gpu/drm/radeon/atombios_i2c.c | 4 +-- > drivers/gpu/drm/radeon/radeon_combios.c | 28 +-- > drivers/gpu/drm/radeon/radeon_i2c.c | 10 +++ > drivers/gpu/drm/radeon/radeon_mode.h | 6 ++-- > 28 files changed, 93 insertions(+), 93 deletions(-) > Hello Christian, Daniel, David, others, Could you re-review v2 since the feedback provided in v0 [1] has now been addressed? I can send v3 with all other feedback and signoffs from the other maintainers incorporated when I have something for amdgpu and radeon. Thanks, Easwar [1] https://lore.kernel.org/all/53f3afba-4759-4ea1-b408-8a929b262...@amd.com/
[RFC PATCH] drm/amd/display: Disable panel_power_savings sysfs entry for OLED displays
The panel_power_savings sysfs entry sets the Adaptive Backlight
Management level (abm_level). OLED displays work without backlight, so
it is unnecessary for them.
Before creating the sysfs entry, make sure the display is not an OLED
display.
Signed-off-by: Gergo Koteles
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index d6e71aa808d8..d54065a76f63 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -6535,9 +6535,11 @@ static const struct attribute_group amdgpu_group = {
static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
{
struct amdgpu_dm_connector *amdgpu_dm_connector =
to_amdgpu_dm_connector(connector);
+ union dpcd_sink_ext_caps *ext_caps =
+ _dm_connector->dc_link->dpcd_sink_ext_caps;
if (connector->connector_type == DRM_MODE_CONNECTOR_eDP &&
- amdgpu_dm_abm_level < 0)
+ amdgpu_dm_abm_level < 0 && !ext_caps->bits.oled)
sysfs_remove_group(>kdev->kobj, _group);
drm_dp_aux_unregister(_dm_connector->dm_dp_aux.aux);
@@ -6642,10 +6644,12 @@ amdgpu_dm_connector_late_register(struct drm_connector
*connector)
{
struct amdgpu_dm_connector *amdgpu_dm_connector =
to_amdgpu_dm_connector(connector);
+ union dpcd_sink_ext_caps *ext_caps =
+ _dm_connector->dc_link->dpcd_sink_ext_caps;
int r;
if (connector->connector_type == DRM_MODE_CONNECTOR_eDP &&
- amdgpu_dm_abm_level < 0) {
+ amdgpu_dm_abm_level < 0 && !ext_caps->bits.oled) {
r = sysfs_create_group(>kdev->kobj,
_group);
if (r)
base-commit: dccb07f2914cdab2ac3a5b6c98406f765acab803
--
2.45.0
Re: [RFC 0/5] Add capacity key to fdinfo
On 03/05/2024 15:28, Alex Deucher wrote: On Fri, May 3, 2024 at 7:50 AM Tvrtko Ursulin wrote: On 02/05/2024 16:00, Alex Deucher wrote: On Thu, May 2, 2024 at 10:43 AM Tvrtko Ursulin wrote: On 02/05/2024 14:07, Christian König wrote: Am 01.05.24 um 15:27 schrieb Tvrtko Ursulin: Hi Alex, On 30/04/2024 19:32, Alex Deucher wrote: On Tue, Apr 30, 2024 at 1:27 PM Tvrtko Ursulin wrote: From: Tvrtko Ursulin I have noticed AMD GPUs can have more than one "engine" (ring?) of the same type but amdgpu is not reporting that in fdinfo using the capacity engine tag. This series is therefore an attempt to improve that, but only an RFC since it is quite likely I got stuff wrong on the first attempt. Or if not wrong it may not be very beneficial in AMDs case. So I tried to figure out how to count and store the number of instances of an "engine" type and spotted that could perhaps be used in more than one place in the driver. I was more than a little bit confused by the ip_instance and uapi rings, then how rings are selected to context entities internally. Anyway.. hopefully it is a simple enough series to easily spot any such large misses. End result should be that, assuming two "engine" instances, one fully loaded and one idle will only report client using 50% of that engine type. That would only be true if there are multiple instantiations of the IP on the chip which in most cases is not true. In most cases there is one instance of the IP that can be fed from multiple rings. E.g. for graphics and compute, all of the rings ultimately feed into the same compute units on the chip. So if you have a gfx ring and a compute rings, you can schedule work to them asynchronously, but ultimately whether they execute serially or in parallel depends on the actual shader code in the command buffers and the extent to which it can utilize the available compute units in the shader cores. This is the same as with Intel/i915. Fdinfo is not intended to provide utilisation of EUs and such, just how busy are the "entities" kernel submits to. So doing something like in this series would make the reporting more similar between the two drivers. I think both the 0-800% or 0-100% range (taking 8 ring compute as an example) can be misleading for different workloads. Neither <800% in the former means one can send more work and same for <100% in the latter. Yeah, I think that's what Alex tries to describe. By using 8 compute rings your 800% load is actually incorrect and quite misleading. Background is that those 8 compute rings won't be active all at the same time, but rather waiting on each other for resources. But this "waiting" is unfortunately considered execution time since the used approach is actually not really capable of separating waiting and execution time. Right, so 800% is what gputop could be suggesting today, by the virtue 8 context/clients can each use 100% if they only use a subset of compute units. I was proposing to expose the capacity in fdinfo so it can be scaled down and then dicussing how both situation have pros and cons. There is also a parallel with the CPU world here and hyper threading, if not wider, where "What does 100% actually mean?" is also wishy-washy. Also note that the reporting of actual time based values in fdinfo would not changing with this series. Of if you can guide me towards how to distinguish real vs fake parallelism in HW IP blocks I could modify the series to only add capacity tags where there are truly independent blocks. That would be different from i915 though were I did not bother with that distinction. (For reasons that assignment of for instance EUs to compute "rings" (command streamers in i915) was supposed to be possible to re-configure on the fly. So it did not make sense to try and be super smart in fdinfo.) Well exactly that's the point we don't really have truly independent blocks on AMD hardware. There are things like independent SDMA instances, but those a meant to be used like the first instance for uploads and the second for downloads etc.. When you use both instances for the same job they will pretty much limit each other because of a single resource. So _never_ multiple instances of the same IP block? No video decode, encode, anything? Some chips have multiple encode/decode IP blocks that are actually separate instances, however, we load balance between them so userspace sees just one engine. Also in some cases they are asymmetric (e.g., different sets of supported CODECs on each instance). The driver handles this by inspecting the command buffer and scheduling on the appropriate instance based on the requested CODEC. SDMA also supports multiple IP blocks that are independent. Similar to i915 just that we don't inspect buffers but expose the instance capabilities and userspace is responsible to set up the load balancing engine with the correct physical mask. How do you handle load balancing across applications? From the uapi side
[patch] problems with "fix visible VRAM handling during faults"
This is just to report that I've had usually well-behaved applications
sometimes having problems with memory access violations since kernel
version 6.9-rc5. This past weekend I stumbled across a way to reliably
reproduce the problem in the form of a Skyrim save file which causes a
crash shortly after loading the game on affected kernels.
Things go back to running smoothly only if I revert one of the changes
in 5th April's "[PATCH] drm/amdgpu: fix visible VRAM handling during
faults" as follows.
Patch is against v6.9-rc7. It restores the check for partially
visible-to-cpu memory in amdgpu_bo_fault_reserve_notify. Things
seem stable again with this change.
--
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 5 -
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 22 ++
2 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index f6d503432a9e..a6874aea7820 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -1396,7 +1396,10 @@ vm_fault_t amdgpu_bo_fault_reserve_notify(struct
ttm_buffer_object *bo)
/* Remember that this BO was accessed by the CPU */
abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
- if (amdgpu_res_cpu_visible(adev, bo->resource))
+ if (bo->resource->mem_type != TTM_PL_VRAM)
+ return 0;
+
+ if (amdgpu_bo_in_cpu_visible_vram(abo))
return 0;
/* Can't move a pinned BO to visible VRAM */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index bc42ccbde659..0503af75dc26 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -250,6 +250,28 @@ static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo
*bo)
return drm_vma_node_offset_addr(>tbo.base.vma_node);
}
+/**
+ * amdgpu_bo_in_cpu_visible_vram - check if BO is (partly) in visible VRAM
+ */
+static inline bool amdgpu_bo_in_cpu_visible_vram(struct amdgpu_bo *bo)
+{
+ struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
+ struct amdgpu_res_cursor cursor;
+
+ if (!bo->tbo.resource || bo->tbo.resource->mem_type != TTM_PL_VRAM)
+ return false;
+
+ amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), );
+ while (cursor.remaining) {
+ if (cursor.start < adev->gmc.visible_vram_size)
+ return true;
+
+ amdgpu_res_next(, cursor.size);
+ }
+
+ return false;
+}
+
/**
* amdgpu_bo_explicit_sync - return whether the bo is explicitly synced
*/
[PATCH] drm/buddy: Fix the range bias clear memory allocation issue
Problem statement: During the system boot time, an application request
for the bulk volume of cleared range bias memory when the clear_avail
is zero, we dont fallback into normal allocation method as we had an
unnecessary clear_avail check which prevents the fallback method leads
to fb allocation failure following system goes into unresponsive state.
Solution: Remove the unnecessary clear_avail check in the range bias
allocation function.
Signed-off-by: Arunpravin Paneer Selvam
Fixes: 96950929eb23 ("drm/buddy: Implement tracking clear page feature")
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/drm_buddy.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_buddy.c b/drivers/gpu/drm/drm_buddy.c
index 284ebae71cc4..831929ac95eb 100644
--- a/drivers/gpu/drm/drm_buddy.c
+++ b/drivers/gpu/drm/drm_buddy.c
@@ -574,7 +574,7 @@ __drm_buddy_alloc_range_bias(struct drm_buddy *mm,
block = __alloc_range_bias(mm, start, end, order,
flags, fallback);
- if (IS_ERR(block) && mm->clear_avail)
+ if (IS_ERR(block))
return __alloc_range_bias(mm, start, end, order,
flags, !fallback);
--
2.25.1
Re: [PATCH 11/11] drm/tegra: Use fbdev client helpers
Hi
Am 07.05.24 um 23:03 schrieb Felix Kuehling:
On 2024-05-07 07:58, Thomas Zimmermann wrote:
Implement struct drm_client_funcs with the respective helpers and
remove the custom code from the emulation. The generic helpers are
equivalent in functionality.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/radeon/radeon_fbdev.c | 66 ++-
Was radeon meant to be a separate patch?
Indeed. It also _was_ a separate patch. This looks like a mistake during
rebasing. Thanks for noticing. I'll fix that in v2.
Best regards
Thomas
Regards,
Felix
drivers/gpu/drm/tegra/fbdev.c | 58 ++-
2 files changed, 6 insertions(+), 118 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_fbdev.c
b/drivers/gpu/drm/radeon/radeon_fbdev.c
index 02bf25759059a..cf790922174ea 100644
--- a/drivers/gpu/drm/radeon/radeon_fbdev.c
+++ b/drivers/gpu/drm/radeon/radeon_fbdev.c
@@ -29,7 +29,6 @@
#include
#include
-#include
#include
#include
#include
@@ -293,71 +292,12 @@ static const struct drm_fb_helper_funcs
radeon_fbdev_fb_helper_funcs = {
};
/*
- * Fbdev client and struct drm_client_funcs
+ * struct drm_client_funcs
*/
-static void radeon_fbdev_client_unregister(struct drm_client_dev
*client)
-{
- struct drm_fb_helper *fb_helper =
drm_fb_helper_from_client(client);
- struct drm_device *dev = fb_helper->dev;
- struct radeon_device *rdev = dev->dev_private;
-
- if (fb_helper->info) {
- vga_switcheroo_client_fb_set(rdev->pdev, NULL);
- drm_helper_force_disable_all(dev);
- drm_fb_helper_unregister_info(fb_helper);
- } else {
- drm_client_release(_helper->client);
- drm_fb_helper_unprepare(fb_helper);
- kfree(fb_helper);
- }
-}
-
-static int radeon_fbdev_client_restore(struct drm_client_dev *client)
-{
- drm_fb_helper_lastclose(client->dev);
- vga_switcheroo_process_delayed_switch();
-
- return 0;
-}
-
-static int radeon_fbdev_client_hotplug(struct drm_client_dev *client)
-{
- struct drm_fb_helper *fb_helper =
drm_fb_helper_from_client(client);
- struct drm_device *dev = client->dev;
- struct radeon_device *rdev = dev->dev_private;
- int ret;
-
- if (dev->fb_helper)
- return drm_fb_helper_hotplug_event(dev->fb_helper);
-
- ret = drm_fb_helper_init(dev, fb_helper);
- if (ret)
- goto err_drm_err;
-
- if (!drm_drv_uses_atomic_modeset(dev))
- drm_helper_disable_unused_functions(dev);
-
- ret = drm_fb_helper_initial_config(fb_helper);
- if (ret)
- goto err_drm_fb_helper_fini;
-
- vga_switcheroo_client_fb_set(rdev->pdev, fb_helper->info);
-
- return 0;
-
-err_drm_fb_helper_fini:
- drm_fb_helper_fini(fb_helper);
-err_drm_err:
- drm_err(dev, "Failed to setup radeon fbdev emulation
(ret=%d)\n", ret);
- return ret;
-}
-
static const struct drm_client_funcs radeon_fbdev_client_funcs = {
- .owner = THIS_MODULE,
- .unregister = radeon_fbdev_client_unregister,
- .restore = radeon_fbdev_client_restore,
- .hotplug = radeon_fbdev_client_hotplug,
+ .owner = THIS_MODULE,
+ DRM_FBDEV_HELPER_CLIENT_FUNCS,
};
void radeon_fbdev_setup(struct radeon_device *rdev)
diff --git a/drivers/gpu/drm/tegra/fbdev.c
b/drivers/gpu/drm/tegra/fbdev.c
index db6eaac3d30e6..f9cc365cfed94 100644
--- a/drivers/gpu/drm/tegra/fbdev.c
+++ b/drivers/gpu/drm/tegra/fbdev.c
@@ -12,7 +12,6 @@
#include
#include
-#include
#include
#include
#include
@@ -150,63 +149,12 @@ static const struct drm_fb_helper_funcs
tegra_fb_helper_funcs = {
};
/*
- * struct drm_client
+ * struct drm_client_funcs
*/
-static void tegra_fbdev_client_unregister(struct drm_client_dev
*client)
-{
- struct drm_fb_helper *fb_helper =
drm_fb_helper_from_client(client);
-
- if (fb_helper->info) {
- drm_fb_helper_unregister_info(fb_helper);
- } else {
- drm_client_release(_helper->client);
- drm_fb_helper_unprepare(fb_helper);
- kfree(fb_helper);
- }
-}
-
-static int tegra_fbdev_client_restore(struct drm_client_dev *client)
-{
- drm_fb_helper_lastclose(client->dev);
-
- return 0;
-}
-
-static int tegra_fbdev_client_hotplug(struct drm_client_dev *client)
-{
- struct drm_fb_helper *fb_helper =
drm_fb_helper_from_client(client);
- struct drm_device *dev = client->dev;
- int ret;
-
- if (dev->fb_helper)
- return drm_fb_helper_hotplug_event(dev->fb_helper);
-
- ret = drm_fb_helper_init(dev, fb_helper);
- if (ret)
- goto err_drm_err;
-
- if (!drm_drv_uses_atomic_modeset(dev))
- drm_helper_disable_unused_functions(dev);
-
- ret = drm_fb_helper_initial_config(fb_helper);
- if (ret)
- goto err_drm_fb_helper_fini;
-
- return 0;
-
-err_drm_fb_helper_fini:
- drm_fb_helper_fini(fb_helper);
-err_drm_err:
- drm_err(dev, "Failed to setup fbdev emulation (ret=%d)\n", ret);
- return ret;
-}
-
