[clang] [llvm] [RISCV] Add processor definition and scheduling model for XiangShan-KunMingHu (PR #90392)

[Camel Coder via cfe-commits]

=?utf-8?b?6YOd5bq36L6+?= 
Message-ID:
In-Reply-To: 


https://github.com/camel-cdr edited 
https://github.com/llvm/llvm-project/pull/90392
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add processor definition and scheduling model for XiangShan-KunMingHu (PR #90392)

[Camel Coder via cfe-commits]

=?utf-8?b?6YOd5bq36L6+?= 
Message-ID:
In-Reply-To: 



@@ -0,0 +1,1489 @@
+//==- RISCVSchedXiangShanKunMingHu.td - XiangShanKunMingHu Scheduling Defs -*- 
tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+// The XiangShan is a high-performance open-source RISC-V processor project 
+// initiated by the Institute of Computing Technology(ICT), Chinese Academy of 
Sciences(CAS). 
+// The KunMingHu architecture is its third-generation derivative, 
+// developed by the Institute of Computing Technology, Chinese Academy of 
Sciences  
+// and the Beijing Institute of Open Source Chip (BOSC), 
+// with a focus on achieving higher performance.
+// Source: https://github.com/OpenXiangShan/XiangShan
+// Documentation: https://github.com/OpenXiangShan/XiangShan-doc
+
+//===--===//
+// KunMingHu core supports 
"RV64IMAFDCV_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd_zkne_zknh
+// _zksed_zksh_svinval_zicbom_zicboz_zicsr_zifencei"
+// then floating-point SEW can only be 64 and 32, not 16 and 8.
+class NoZvfhSchedSEWSet_rm8and16 {
+  defvar t = SchedSEWSet.val; 
+  defvar remove8and16 = !if(isF, !listremove(t, [8, 16]), t);
+  list val = remove8and16;
+}
+
+class NoZvfhSmallestSEW {
+  int r = !head(NoZvfhSchedSEWSet_rm8and16.val);
+}
+
+multiclass NoZvfh_LMULSEWReadAdvanceImpl writes = [],
+  list MxList, bit isF = 0,
+  bit isWidening = 0> {
+  if !exists(name # "_WorstCase") then
+def : ReadAdvance(name # "_WorstCase"), val, writes>;
+  foreach mx = MxList in {
+foreach sew = NoZvfhSchedSEWSet_rm8and16.val in
+  if !exists(name # "_" # mx # "_E" # sew) then
+def : ReadAdvance(name # "_" # mx # "_E" # sew), val, 
writes>;
+  }
+}
+
+multiclass LMULSEWReadAdvanceFnoZvfh 
writes = []>
+  : NoZvfh_LMULSEWReadAdvanceImpl;
+
+multiclass LMULSEWReadAdvanceFWnoZvfh 
writes = []>
+: NoZvfh_LMULSEWReadAdvanceImpl;
+
+//===--===//
+// If Zvfhmin and Zvfh are not supported, floating-point SEW can only be 32 or 
64.
+class NoZvfhSchedSEWSet_rm32and64 {
+  defvar t = SchedSEWSet.val;
+  defvar remove32and64 = !if(isF, !listremove(t, [32, 64]), t);
+  list val = remove32and64;
+}
+
+// Write-Impl
+multiclass NoZvfhLMULSEWWriteResImpl 
resources,
+   list MxList, bit isF = 0,
+   bit isWidening = 0> {
+  foreach mx = MxList in {
+foreach sew = NoZvfhSchedSEWSet_rm32and64.val in
+  if !exists(name # "_" # mx # "_E" # sew) then
+def : WriteRes(name # "_" # mx # "_E" # sew), 
resources>;
+  }
+}
+// Read-Impl
+multiclass NoZvfhLMULSEWReadAdvanceImpl 
writes = [],
+  list MxList, bit isF = 0,
+  bit isWidening = 0> {
+  foreach mx = MxList in {
+foreach sew = NoZvfhSchedSEWSet_rm32and64.val in
+  if !exists(name # "_" # mx # "_E" # sew) then
+def : ReadAdvance(name # "_" # mx # "_E" # sew), val, 
writes>;
+  }
+}
+
+// Write
+multiclass NoZvfhLMULSEWWriteResF 
resources>
+: NoZvfhLMULSEWWriteResImpl;
+
+multiclass NoZvfhLMULSEWWriteResFW 
resources>
+: NoZvfhLMULSEWWriteResImpl;
+
+multiclass NoZvfhLMULSEWWriteResFWRed 
resources>
+: NoZvfhLMULSEWWriteResImpl;
+
+// Read
+multiclass NoZvfhLMULSEWReadAdvanceF 
writes = []>
+  : NoZvfhLMULSEWReadAdvanceImpl;
+multiclass
+NoZvfhLMULSEWReadAdvanceFW writes = 
[]>
+: NoZvfhLMULSEWReadAdvanceImpl;
+
+multiclass UnsupportedSchedZvfh {
+let Unsupported = true in {
+// Write 
+// 13. Vector Floating-Point Instructions
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFALUV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFALUF", []>;
+defm "" : NoZvfhLMULSEWWriteResFW<"WriteVFWALUV", []>;
+defm "" : NoZvfhLMULSEWWriteResFW<"WriteVFWALUF", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFMulV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFMulF", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFDivV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFDivF", []>;
+defm "" : NoZvfhLMULSEWWriteResFW<"WriteVFWMulV", []>;
+defm "" : NoZvfhLMULSEWWriteResFW<"WriteVFWMulF", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFMulAddV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFMulAddF", []>;
+defm "" : NoZvfhLMULSEWWriteResFW<"WriteVFWMulAddV", []>;
+defm "" : NoZvfhLMULSEWWriteResFW<"WriteVFWMulAddF", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFSqrtV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFRecpV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFMinMaxV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFMinMaxF", []>;
+defm "" : 

[clang] [llvm] [RISCV] Add processor definition and scheduling model for XiangShan-KunMingHu (PR #90392)

[Pengcheng Wang via cfe-commits]

=?utf-8?b?6YOd5bq36L6+?= 
Message-ID:
In-Reply-To: 


wangpc-pp wrote:

I'd like to see the support of KunMingHu, but please hold this PR and wait for 
the finalization of KunMingHu's architecture.

https://github.com/llvm/llvm-project/pull/90392
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add processor definition and scheduling model for XiangShan-KunMingHu (PR #90392)

[Camel Coder via cfe-commits]

=?utf-8?b?6YOd5bq36L6+?= 
Message-ID:
In-Reply-To: 


camel-cdr wrote:

The execution unit layout does not match the current XiangShan master. Has the 
final execution unit layout been decided on?

[earlier 
layout](https://github.com/OpenXiangShan/XiangShan/blob/e25e4d90505c592524b410b127fe611ac49a3adf/src/main/scala/xiangshan/Parameters.scala#L355),
 which this PR seems to be based on:
```
VFEX0: VfaluCfg, VfmaCfg, VialuCfg, VimacCfg
VFEX1: VipuCfg, VppuCfg, VfcvtCfg, F2vCfg, F2fCfg, F2iCfg, VSetRvfWvfCfg
VFEX2: VfaluCfg, VfmaCfg, VialuCfg
VFEX3: VfdivCfg, VidivCfg
```
[current master 
layout](https://github.com/OpenXiangShan/XiangShan/blob/2e61107/src/main/scala/xiangshan/Parameters.scala#L357):
```
VFEX0: VfmaCfg, VialuCfg, VimacCfg, VppuCfg
VFEX1: VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg
VFEX2: VfmaCfg, VialuCfg, F2vCfg
VFEX3: VfaluCfg, VfcvtCfg
VFEX4: VfdivCfg, VidivCfg
VFEX5: VfdivCfg, VidivCfg
```

There even is a open branch that seperates the vpu and fpu pipelines: 
https://github.com/OpenXiangShan/XiangShan/blob/fp-split/src/main/scala/xiangshan/Parameters.scala#L365

I'd love to have proper scheduling support for kunminghu, but it currectly 
doesn't look like a stable target.

BTW: Having two div, but only a single vppu seems like a bit of an odd choice. 
XuanTie C920 has two permutation execution units, and so do the more comparable 
ARM Neoverse N2 and AMD Zen1.


https://github.com/llvm/llvm-project/pull/90392
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add processor definition and scheduling model for XiangShan-KunMingHu (PR #90392)

[Yingwei Zheng via cfe-commits]

=?utf-8?b?6YOd5bq36L6+?= 
Message-ID:
In-Reply-To: 



@@ -0,0 +1,1489 @@
+//==- RISCVSchedXiangShanKunMingHu.td - XiangShanKunMingHu Scheduling Defs -*- 
tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+// The XiangShan is a high-performance open-source RISC-V processor project 
+// initiated by the Institute of Computing Technology(ICT), Chinese Academy of 
Sciences(CAS). 
+// The KunMingHu architecture is its third-generation derivative, 
+// developed by the Institute of Computing Technology, Chinese Academy of 
Sciences  
+// and the Beijing Institute of Open Source Chip (BOSC), 
+// with a focus on achieving higher performance.
+// Source: https://github.com/OpenXiangShan/XiangShan
+// Documentation: https://github.com/OpenXiangShan/XiangShan-doc
+
+//===--===//
+// KunMingHu core supports 
"RV64IMAFDCV_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd_zkne_zknh
+// _zksed_zksh_svinval_zicbom_zicboz_zicsr_zifencei"
+// then floating-point SEW can only be 64 and 32, not 16 and 8.
+class NoZvfhSchedSEWSet_rm8and16 {
+  defvar t = SchedSEWSet.val; 
+  defvar remove8and16 = !if(isF, !listremove(t, [8, 16]), t);
+  list val = remove8and16;
+}
+
+class NoZvfhSmallestSEW {
+  int r = !head(NoZvfhSchedSEWSet_rm8and16.val);
+}
+
+multiclass NoZvfh_LMULSEWReadAdvanceImpl writes = [],
+  list MxList, bit isF = 0,
+  bit isWidening = 0> {
+  if !exists(name # "_WorstCase") then
+def : ReadAdvance(name # "_WorstCase"), val, writes>;
+  foreach mx = MxList in {
+foreach sew = NoZvfhSchedSEWSet_rm8and16.val in
+  if !exists(name # "_" # mx # "_E" # sew) then
+def : ReadAdvance(name # "_" # mx # "_E" # sew), val, 
writes>;
+  }
+}
+
+multiclass LMULSEWReadAdvanceFnoZvfh 
writes = []>
+  : NoZvfh_LMULSEWReadAdvanceImpl;
+
+multiclass LMULSEWReadAdvanceFWnoZvfh 
writes = []>
+: NoZvfh_LMULSEWReadAdvanceImpl;
+
+//===--===//
+// If Zvfhmin and Zvfh are not supported, floating-point SEW can only be 32 or 
64.
+class NoZvfhSchedSEWSet_rm32and64 {
+  defvar t = SchedSEWSet.val;
+  defvar remove32and64 = !if(isF, !listremove(t, [32, 64]), t);
+  list val = remove32and64;
+}
+
+// Write-Impl
+multiclass NoZvfhLMULSEWWriteResImpl 
resources,
+   list MxList, bit isF = 0,
+   bit isWidening = 0> {
+  foreach mx = MxList in {
+foreach sew = NoZvfhSchedSEWSet_rm32and64.val in
+  if !exists(name # "_" # mx # "_E" # sew) then
+def : WriteRes(name # "_" # mx # "_E" # sew), 
resources>;
+  }
+}
+// Read-Impl
+multiclass NoZvfhLMULSEWReadAdvanceImpl 
writes = [],
+  list MxList, bit isF = 0,
+  bit isWidening = 0> {
+  foreach mx = MxList in {
+foreach sew = NoZvfhSchedSEWSet_rm32and64.val in
+  if !exists(name # "_" # mx # "_E" # sew) then
+def : ReadAdvance(name # "_" # mx # "_E" # sew), val, 
writes>;
+  }
+}
+
+// Write
+multiclass NoZvfhLMULSEWWriteResF 
resources>
+: NoZvfhLMULSEWWriteResImpl;
+
+multiclass NoZvfhLMULSEWWriteResFW 
resources>
+: NoZvfhLMULSEWWriteResImpl;
+
+multiclass NoZvfhLMULSEWWriteResFWRed 
resources>
+: NoZvfhLMULSEWWriteResImpl;
+
+// Read
+multiclass NoZvfhLMULSEWReadAdvanceF 
writes = []>
+  : NoZvfhLMULSEWReadAdvanceImpl;
+multiclass
+NoZvfhLMULSEWReadAdvanceFW writes = 
[]>
+: NoZvfhLMULSEWReadAdvanceImpl;
+
+multiclass UnsupportedSchedZvfh {
+let Unsupported = true in {
+// Write 
+// 13. Vector Floating-Point Instructions
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFALUV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFALUF", []>;
+defm "" : NoZvfhLMULSEWWriteResFW<"WriteVFWALUV", []>;
+defm "" : NoZvfhLMULSEWWriteResFW<"WriteVFWALUF", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFMulV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFMulF", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFDivV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFDivF", []>;
+defm "" : NoZvfhLMULSEWWriteResFW<"WriteVFWMulV", []>;
+defm "" : NoZvfhLMULSEWWriteResFW<"WriteVFWMulF", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFMulAddV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFMulAddF", []>;
+defm "" : NoZvfhLMULSEWWriteResFW<"WriteVFWMulAddV", []>;
+defm "" : NoZvfhLMULSEWWriteResFW<"WriteVFWMulAddF", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFSqrtV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFRecpV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFMinMaxV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFMinMaxF", []>;
+defm "" : 

[clang] [llvm] [RISCV] Add processor definition and scheduling model for XiangShan-KunMingHu (PR #90392)

[Yingwei Zheng via cfe-commits]

=?utf-8?b?6YOd5bq36L6+?= 
Message-ID:
In-Reply-To: 



@@ -0,0 +1,1489 @@
+//==- RISCVSchedXiangShanKunMingHu.td - XiangShanKunMingHu Scheduling Defs -*- 
tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+// The XiangShan is a high-performance open-source RISC-V processor project 
+// initiated by the Institute of Computing Technology(ICT), Chinese Academy of 
Sciences(CAS). 
+// The KunMingHu architecture is its third-generation derivative, 
+// developed by the Institute of Computing Technology, Chinese Academy of 
Sciences  
+// and the Beijing Institute of Open Source Chip (BOSC), 
+// with a focus on achieving higher performance.
+// Source: https://github.com/OpenXiangShan/XiangShan
+// Documentation: https://github.com/OpenXiangShan/XiangShan-doc
+
+//===--===//
+// KunMingHu core supports 
"RV64IMAFDCV_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd_zkne_zknh
+// _zksed_zksh_svinval_zicbom_zicboz_zicsr_zifencei"
+// then floating-point SEW can only be 64 and 32, not 16 and 8.
+class NoZvfhSchedSEWSet_rm8and16 {
+  defvar t = SchedSEWSet.val; 
+  defvar remove8and16 = !if(isF, !listremove(t, [8, 16]), t);
+  list val = remove8and16;
+}
+
+class NoZvfhSmallestSEW {
+  int r = !head(NoZvfhSchedSEWSet_rm8and16.val);
+}
+
+multiclass NoZvfh_LMULSEWReadAdvanceImpl writes = [],
+  list MxList, bit isF = 0,
+  bit isWidening = 0> {
+  if !exists(name # "_WorstCase") then
+def : ReadAdvance(name # "_WorstCase"), val, writes>;
+  foreach mx = MxList in {
+foreach sew = NoZvfhSchedSEWSet_rm8and16.val in
+  if !exists(name # "_" # mx # "_E" # sew) then
+def : ReadAdvance(name # "_" # mx # "_E" # sew), val, 
writes>;
+  }
+}
+
+multiclass LMULSEWReadAdvanceFnoZvfh 
writes = []>
+  : NoZvfh_LMULSEWReadAdvanceImpl;
+
+multiclass LMULSEWReadAdvanceFWnoZvfh 
writes = []>
+: NoZvfh_LMULSEWReadAdvanceImpl;
+
+//===--===//
+// If Zvfhmin and Zvfh are not supported, floating-point SEW can only be 32 or 
64.
+class NoZvfhSchedSEWSet_rm32and64 {
+  defvar t = SchedSEWSet.val;
+  defvar remove32and64 = !if(isF, !listremove(t, [32, 64]), t);
+  list val = remove32and64;
+}
+
+// Write-Impl
+multiclass NoZvfhLMULSEWWriteResImpl 
resources,
+   list MxList, bit isF = 0,
+   bit isWidening = 0> {
+  foreach mx = MxList in {
+foreach sew = NoZvfhSchedSEWSet_rm32and64.val in
+  if !exists(name # "_" # mx # "_E" # sew) then
+def : WriteRes(name # "_" # mx # "_E" # sew), 
resources>;
+  }
+}
+// Read-Impl
+multiclass NoZvfhLMULSEWReadAdvanceImpl 
writes = [],
+  list MxList, bit isF = 0,
+  bit isWidening = 0> {
+  foreach mx = MxList in {
+foreach sew = NoZvfhSchedSEWSet_rm32and64.val in
+  if !exists(name # "_" # mx # "_E" # sew) then
+def : ReadAdvance(name # "_" # mx # "_E" # sew), val, 
writes>;
+  }
+}
+
+// Write
+multiclass NoZvfhLMULSEWWriteResF 
resources>
+: NoZvfhLMULSEWWriteResImpl;
+
+multiclass NoZvfhLMULSEWWriteResFW 
resources>
+: NoZvfhLMULSEWWriteResImpl;
+
+multiclass NoZvfhLMULSEWWriteResFWRed 
resources>
+: NoZvfhLMULSEWWriteResImpl;
+
+// Read
+multiclass NoZvfhLMULSEWReadAdvanceF 
writes = []>
+  : NoZvfhLMULSEWReadAdvanceImpl;
+multiclass
+NoZvfhLMULSEWReadAdvanceFW writes = 
[]>
+: NoZvfhLMULSEWReadAdvanceImpl;
+
+multiclass UnsupportedSchedZvfh {
+let Unsupported = true in {
+// Write 
+// 13. Vector Floating-Point Instructions
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFALUV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFALUF", []>;
+defm "" : NoZvfhLMULSEWWriteResFW<"WriteVFWALUV", []>;
+defm "" : NoZvfhLMULSEWWriteResFW<"WriteVFWALUF", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFMulV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFMulF", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFDivV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFDivF", []>;
+defm "" : NoZvfhLMULSEWWriteResFW<"WriteVFWMulV", []>;
+defm "" : NoZvfhLMULSEWWriteResFW<"WriteVFWMulF", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFMulAddV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFMulAddF", []>;
+defm "" : NoZvfhLMULSEWWriteResFW<"WriteVFWMulAddV", []>;
+defm "" : NoZvfhLMULSEWWriteResFW<"WriteVFWMulAddF", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFSqrtV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFRecpV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFMinMaxV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFMinMaxF", []>;
+defm "" : 

[clang] [llvm] [RISCV] Add processor definition and scheduling model for XiangShan-KunMingHu (PR #90392)

[Yingwei Zheng via cfe-commits]

=?utf-8?b?6YOd5bq36L6+?= 
Message-ID:
In-Reply-To: 



@@ -0,0 +1,1489 @@
+//==- RISCVSchedXiangShanKunMingHu.td - XiangShanKunMingHu Scheduling Defs -*- 
tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+// The XiangShan is a high-performance open-source RISC-V processor project 
+// initiated by the Institute of Computing Technology(ICT), Chinese Academy of 
Sciences(CAS). 
+// The KunMingHu architecture is its third-generation derivative, 
+// developed by the Institute of Computing Technology, Chinese Academy of 
Sciences  
+// and the Beijing Institute of Open Source Chip (BOSC), 
+// with a focus on achieving higher performance.
+// Source: https://github.com/OpenXiangShan/XiangShan
+// Documentation: https://github.com/OpenXiangShan/XiangShan-doc
+
+//===--===//
+// KunMingHu core supports 
"RV64IMAFDCV_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd_zkne_zknh
+// _zksed_zksh_svinval_zicbom_zicboz_zicsr_zifencei"
+// then floating-point SEW can only be 64 and 32, not 16 and 8.
+class NoZvfhSchedSEWSet_rm8and16 {
+  defvar t = SchedSEWSet.val; 
+  defvar remove8and16 = !if(isF, !listremove(t, [8, 16]), t);
+  list val = remove8and16;
+}
+
+class NoZvfhSmallestSEW {
+  int r = !head(NoZvfhSchedSEWSet_rm8and16.val);
+}
+
+multiclass NoZvfh_LMULSEWReadAdvanceImpl writes = [],
+  list MxList, bit isF = 0,
+  bit isWidening = 0> {
+  if !exists(name # "_WorstCase") then
+def : ReadAdvance(name # "_WorstCase"), val, writes>;
+  foreach mx = MxList in {
+foreach sew = NoZvfhSchedSEWSet_rm8and16.val in
+  if !exists(name # "_" # mx # "_E" # sew) then
+def : ReadAdvance(name # "_" # mx # "_E" # sew), val, 
writes>;
+  }
+}
+
+multiclass LMULSEWReadAdvanceFnoZvfh 
writes = []>
+  : NoZvfh_LMULSEWReadAdvanceImpl;
+
+multiclass LMULSEWReadAdvanceFWnoZvfh 
writes = []>
+: NoZvfh_LMULSEWReadAdvanceImpl;
+
+//===--===//
+// If Zvfhmin and Zvfh are not supported, floating-point SEW can only be 32 or 
64.
+class NoZvfhSchedSEWSet_rm32and64 {
+  defvar t = SchedSEWSet.val;
+  defvar remove32and64 = !if(isF, !listremove(t, [32, 64]), t);
+  list val = remove32and64;
+}
+
+// Write-Impl
+multiclass NoZvfhLMULSEWWriteResImpl 
resources,
+   list MxList, bit isF = 0,
+   bit isWidening = 0> {
+  foreach mx = MxList in {
+foreach sew = NoZvfhSchedSEWSet_rm32and64.val in
+  if !exists(name # "_" # mx # "_E" # sew) then
+def : WriteRes(name # "_" # mx # "_E" # sew), 
resources>;
+  }
+}
+// Read-Impl
+multiclass NoZvfhLMULSEWReadAdvanceImpl 
writes = [],
+  list MxList, bit isF = 0,
+  bit isWidening = 0> {
+  foreach mx = MxList in {
+foreach sew = NoZvfhSchedSEWSet_rm32and64.val in
+  if !exists(name # "_" # mx # "_E" # sew) then
+def : ReadAdvance(name # "_" # mx # "_E" # sew), val, 
writes>;
+  }
+}
+
+// Write
+multiclass NoZvfhLMULSEWWriteResF 
resources>
+: NoZvfhLMULSEWWriteResImpl;
+
+multiclass NoZvfhLMULSEWWriteResFW 
resources>
+: NoZvfhLMULSEWWriteResImpl;
+
+multiclass NoZvfhLMULSEWWriteResFWRed 
resources>
+: NoZvfhLMULSEWWriteResImpl;
+
+// Read
+multiclass NoZvfhLMULSEWReadAdvanceF 
writes = []>
+  : NoZvfhLMULSEWReadAdvanceImpl;
+multiclass
+NoZvfhLMULSEWReadAdvanceFW writes = 
[]>
+: NoZvfhLMULSEWReadAdvanceImpl;
+
+multiclass UnsupportedSchedZvfh {
+let Unsupported = true in {
+// Write 
+// 13. Vector Floating-Point Instructions
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFALUV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFALUF", []>;
+defm "" : NoZvfhLMULSEWWriteResFW<"WriteVFWALUV", []>;
+defm "" : NoZvfhLMULSEWWriteResFW<"WriteVFWALUF", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFMulV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFMulF", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFDivV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFDivF", []>;
+defm "" : NoZvfhLMULSEWWriteResFW<"WriteVFWMulV", []>;
+defm "" : NoZvfhLMULSEWWriteResFW<"WriteVFWMulF", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFMulAddV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFMulAddF", []>;
+defm "" : NoZvfhLMULSEWWriteResFW<"WriteVFWMulAddV", []>;
+defm "" : NoZvfhLMULSEWWriteResFW<"WriteVFWMulAddF", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFSqrtV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFRecpV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFMinMaxV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFMinMaxF", []>;
+defm "" : 

[clang] [llvm] [RISCV] Add processor definition and scheduling model for XiangShan-KunMingHu (PR #90392)

[Yingwei Zheng via cfe-commits]

=?utf-8?b?6YOd5bq36L6+?= 
Message-ID:
In-Reply-To: 



@@ -0,0 +1,1489 @@
+//==- RISCVSchedXiangShanKunMingHu.td - XiangShanKunMingHu Scheduling Defs -*- 
tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+// The XiangShan is a high-performance open-source RISC-V processor project 
+// initiated by the Institute of Computing Technology(ICT), Chinese Academy of 
Sciences(CAS). 
+// The KunMingHu architecture is its third-generation derivative, 
+// developed by the Institute of Computing Technology, Chinese Academy of 
Sciences  
+// and the Beijing Institute of Open Source Chip (BOSC), 
+// with a focus on achieving higher performance.
+// Source: https://github.com/OpenXiangShan/XiangShan
+// Documentation: https://github.com/OpenXiangShan/XiangShan-doc
+
+//===--===//
+// KunMingHu core supports 
"RV64IMAFDCV_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd_zkne_zknh
+// _zksed_zksh_svinval_zicbom_zicboz_zicsr_zifencei"
+// then floating-point SEW can only be 64 and 32, not 16 and 8.
+class NoZvfhSchedSEWSet_rm8and16 {
+  defvar t = SchedSEWSet.val; 
+  defvar remove8and16 = !if(isF, !listremove(t, [8, 16]), t);
+  list val = remove8and16;
+}
+
+class NoZvfhSmallestSEW {
+  int r = !head(NoZvfhSchedSEWSet_rm8and16.val);
+}
+
+multiclass NoZvfh_LMULSEWReadAdvanceImpl writes = [],
+  list MxList, bit isF = 0,
+  bit isWidening = 0> {
+  if !exists(name # "_WorstCase") then
+def : ReadAdvance(name # "_WorstCase"), val, writes>;
+  foreach mx = MxList in {
+foreach sew = NoZvfhSchedSEWSet_rm8and16.val in
+  if !exists(name # "_" # mx # "_E" # sew) then
+def : ReadAdvance(name # "_" # mx # "_E" # sew), val, 
writes>;
+  }
+}
+
+multiclass LMULSEWReadAdvanceFnoZvfh 
writes = []>
+  : NoZvfh_LMULSEWReadAdvanceImpl;
+
+multiclass LMULSEWReadAdvanceFWnoZvfh 
writes = []>
+: NoZvfh_LMULSEWReadAdvanceImpl;
+
+//===--===//
+// If Zvfhmin and Zvfh are not supported, floating-point SEW can only be 32 or 
64.
+class NoZvfhSchedSEWSet_rm32and64 {
+  defvar t = SchedSEWSet.val;
+  defvar remove32and64 = !if(isF, !listremove(t, [32, 64]), t);
+  list val = remove32and64;
+}
+
+// Write-Impl
+multiclass NoZvfhLMULSEWWriteResImpl 
resources,
+   list MxList, bit isF = 0,
+   bit isWidening = 0> {
+  foreach mx = MxList in {
+foreach sew = NoZvfhSchedSEWSet_rm32and64.val in
+  if !exists(name # "_" # mx # "_E" # sew) then
+def : WriteRes(name # "_" # mx # "_E" # sew), 
resources>;
+  }
+}
+// Read-Impl
+multiclass NoZvfhLMULSEWReadAdvanceImpl 
writes = [],
+  list MxList, bit isF = 0,
+  bit isWidening = 0> {
+  foreach mx = MxList in {
+foreach sew = NoZvfhSchedSEWSet_rm32and64.val in
+  if !exists(name # "_" # mx # "_E" # sew) then
+def : ReadAdvance(name # "_" # mx # "_E" # sew), val, 
writes>;
+  }
+}
+
+// Write
+multiclass NoZvfhLMULSEWWriteResF 
resources>
+: NoZvfhLMULSEWWriteResImpl;
+
+multiclass NoZvfhLMULSEWWriteResFW 
resources>
+: NoZvfhLMULSEWWriteResImpl;
+
+multiclass NoZvfhLMULSEWWriteResFWRed 
resources>
+: NoZvfhLMULSEWWriteResImpl;
+
+// Read
+multiclass NoZvfhLMULSEWReadAdvanceF 
writes = []>
+  : NoZvfhLMULSEWReadAdvanceImpl;
+multiclass
+NoZvfhLMULSEWReadAdvanceFW writes = 
[]>
+: NoZvfhLMULSEWReadAdvanceImpl;
+
+multiclass UnsupportedSchedZvfh {
+let Unsupported = true in {
+// Write 
+// 13. Vector Floating-Point Instructions
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFALUV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFALUF", []>;
+defm "" : NoZvfhLMULSEWWriteResFW<"WriteVFWALUV", []>;
+defm "" : NoZvfhLMULSEWWriteResFW<"WriteVFWALUF", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFMulV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFMulF", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFDivV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFDivF", []>;
+defm "" : NoZvfhLMULSEWWriteResFW<"WriteVFWMulV", []>;
+defm "" : NoZvfhLMULSEWWriteResFW<"WriteVFWMulF", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFMulAddV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFMulAddF", []>;
+defm "" : NoZvfhLMULSEWWriteResFW<"WriteVFWMulAddV", []>;
+defm "" : NoZvfhLMULSEWWriteResFW<"WriteVFWMulAddF", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFSqrtV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFRecpV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFMinMaxV", []>;
+defm "" : NoZvfhLMULSEWWriteResF<"WriteVFMinMaxF", []>;
+defm "" : 

[clang] [llvm] [RISCV] Add processor definition and scheduling model for XiangShan-KunMingHu (PR #90392)

[Yingwei Zheng via cfe-commits]

=?utf-8?b?6YOd5bq36L6+?= 
Message-ID:
In-Reply-To: 



@@ -378,3 +378,31 @@ def XIANGSHAN_NANHU : 
RISCVProcessorModel<"xiangshan-nanhu",
 TuneZExtHFusion,
 TuneZExtWFusion,
 TuneShiftedZExtWFusion]>;
+   
 
+def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunminghu",
+  XiangShanKunMingHuModel,
+  [Feature64Bit,
+   FeatureStdExtI,
+   FeatureStdExtZicsr,
+   FeatureStdExtZifencei,
+   FeatureStdExtM,
+   FeatureStdExtA,
+   FeatureStdExtF,
+   FeatureStdExtD,
+   FeatureStdExtC,
+   FeatureStdExtZba,
+   FeatureStdExtZbb,
+   FeatureStdExtZbc,
+   FeatureStdExtZbs,
+   FeatureStdExtZkn,
+   FeatureStdExtZksed,
+   FeatureStdExtZksh,
+   FeatureStdExtSvinval,
+   FeatureStdExtZicbom,
+   FeatureStdExtZicboz,
+   FeatureStdExtV,
+   FeatureStdExtZvl128b],
+   [TuneNoDefaultUnroll,

dtcxzyw wrote:

See https://github.com/llvm/llvm-project/pull/89359#discussion_r1574366104

https://github.com/llvm/llvm-project/pull/90392
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add processor definition and scheduling model for XiangShan-KunMingHu (PR #90392)

[via cfe-commits]

=?utf-8?b?6YOd5bq36L6+?= 
Message-ID:
In-Reply-To: 


llvmbot wrote:




@llvm/pr-subscribers-clang

Author: None (Bhe6669)


Changes

The "XiangShan" is a high-performance open-source RISC-V processor project, and 
The "KunMingHu" architecture is its third generation. Official documentation 
can be found 
at:[documentation](https://xiangshan-doc.readthedocs.io/zh-cn/latest/).

Currently, the KunMingHu core 
supports"RV64IMAFDCV_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_svinval_zicbom_zicboz_zicsr_zifencei".
 The scheduling model encompasses the basic configurations and instruction 
latencies of the KunMingHu core. Other components will be submitted in 
subsequent patches.

Co-authored-by:
Chen Jianchenjian@bosc.ac.cn
Lv Fanglvfang@bosc.ac.cn

---

Patch is 319.05 KiB, truncated to 20.00 KiB below, full version: 
https://github.com/llvm/llvm-project/pull/90392.diff


8 Files Affected:

- (modified) clang/test/Driver/riscv-cpus.c (+37) 
- (modified) clang/test/Misc/target-invalid-cpu-note.c (+2-2) 
- (modified) llvm/lib/Target/RISCV/RISCV.td (+1) 
- (modified) llvm/lib/Target/RISCV/RISCVProcessors.td (+28) 
- (added) llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td (+1489) 
- (added) llvm/test/tools/llvm-mca/RISCV/XiangShan/gpr-bypass-kmh.s (+534) 
- (added) llvm/test/tools/llvm-mca/RISCV/XiangShan/no-sew-fp-8-16.s (+10) 
- (added) llvm/test/tools/llvm-mca/RISCV/XiangShan/vector-integer-arithmetic.s 
(+2271) 


``diff
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index ff2bd6f7c8ba34..54c44a35c3e82e 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -31,6 +31,40 @@
 // MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zks" "-target-feature" 
"+zksed" "-target-feature" "+zksh" "-target-feature" "+svinval"
 // MCPU-XIANGSHAN-NANHU-SAME: "-target-abi" "lp64d"
 
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=xiangshan-kunminghu | 
FileCheck -check-prefix=MCPU-XIANGSHAN-KUNMINGHU %s
+// MCPU-XIANGSHAN-KUNMINGHU: "-nostdsysteminc" "-target-cpu" 
"xiangshan-kunminghu"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+m"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+a"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+f"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+d"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+c"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+v"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicbom" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicboz" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zicsr" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zifencei"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zba" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbb" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbc"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbkb" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbkc" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbkx" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zbs"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zkn" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zknd" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zkne" 
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zknh"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zve32f"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zve32x"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zve64d"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zve64f"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zve64x"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zvl128b"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zvl32b"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-feature" "+zvl64b"
+// MCPU-XIANGSHAN-KUNMINGHU-SAME: "-target-abi" "lp64d"
+
+
 // We cannot check much for -mcpu=native, but it should be replaced by a valid 
CPU string.
 // RUN: %clang --target=riscv64 -### -c %s -mcpu=native 2> %t.err || true
 // RUN: FileCheck --input-file=%t.err -check-prefix=MCPU-NATIVE %s
@@ -76,6 +110,9 @@
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=xiangshan-nanhu | 
FileCheck -check-prefix=MTUNE-XIANGSHAN-NANHU %s
 // MTUNE-XIANGSHAN-NANHU: "-tune-cpu" "xiangshan-nanhu"
 
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=xiangshan-kunminghu | 
FileCheck -check-prefix=MTUNE-XIANGSHAN-KUNMINGHU %s
+// MTUNE-XIANGSHAN-KUNMINGHU: "-tune-cpu" "xiangshan-kunminghu"
+
 // Check mtune alias CPU has resolved to the right CPU according XLEN.
 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=generic | FileCheck 
-check-prefix=MTUNE-GENERIC-32 %s
 // MTUNE-GENERIC-32: "-tune-cpu" "generic"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index 21d80b7134508f..a95170aa01abd2 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ 

[clang] [llvm] [RISCV] Add processor definition and scheduling model for XiangShan-KunMingHu (PR #90392)

[via cfe-commits]

=?utf-8?b?6YOd5bq36L6+?= 
Message-ID:
In-Reply-To: 


github-actions[bot] wrote:



Thank you for submitting a Pull Request (PR) to the LLVM Project!

This PR will be automatically labeled and the relevant teams will be
notified.

If you wish to, you can add reviewers by using the "Reviewers" section on this 
page.

If this is not working for you, it is probably because you do not have write
permissions for the repository. In which case you can instead tag reviewers by
name in a comment by using `@` followed by their GitHub username.

If you have received no comments on your PR for a week, you can request a review
by "ping"ing the PR by adding a comment “Ping”. The common courtesy "ping" rate
is once a week. Please remember that you are asking for valuable time from 
other developers.

If you have further questions, they may be answered by the [LLVM GitHub User 
Guide](https://llvm.org/docs/GitHub.html).

You can also ask questions in a comment on this PR, on the [LLVM 
Discord](https://discord.com/invite/xS7Z362) or on the 
[forums](https://discourse.llvm.org/).

https://github.com/llvm/llvm-project/pull/90392
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits