[coreboot] [commit] r6008 - trunk/src/northbridge/amd/gx2
Author: uwe
Date: Mon Nov 1 15:18:11 2010
New Revision: 6008
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6008
Log:
GX2: Change MSR register numbers into more descriptive names.
Signed-off-by: Nils Jacobs njaco...@hetnet.nl
Acked-by: Uwe Hermann u...@hermann-uwe.de
Modified:
trunk/src/northbridge/amd/gx2/raminit.c
Modified: trunk/src/northbridge/amd/gx2/raminit.c
==
--- trunk/src/northbridge/amd/gx2/raminit.c Mon Nov 1 00:24:18 2010
(r6007)
+++ trunk/src/northbridge/amd/gx2/raminit.c Mon Nov 1 15:18:11 2010
(r6008)
@@ -12,31 +12,31 @@
msr_t msr;
/* 2. clock gating for PMode */
- msr = rdmsr(0x20002004);
+ msr = rdmsr(MC_GLD_MSR_PM);
msr.lo = ~0x04;
msr.lo |= 0x01;
- wrmsr(0x20002004, msr);
+ wrmsr(MC_GLD_MSR_PM, msr);
/* undocmented bits in GX, in LX there are
* 8 bits in PM1_UP_DLY */
- msr = rdmsr(0x201a);
+ msr = rdmsr(MC_CF1017_DATA);
msr.lo = 0x0101;
- wrmsr(0x201a, msr);
+ wrmsr(MC_CF1017_DATA, msr);
//print_debug(sdram_enable step 2\n);
/* 3. release CKE mask to enable CKE */
- msr = rdmsr(0x201d);
+ msr = rdmsr(MC_CFCLK_DBUG);
msr.lo = ~(0x03 8);
- wrmsr(0x2000201d, msr);
+ wrmsr(MC_CFCLK_DBUG, msr);
//print_debug(sdram_enable step 3\n);
/* 4. set and clear REF_TST 16 times, more shouldn't hurt
* why this is before EMRS and MRS ? */
for (i = 0; i 19; i++) {
- msr = rdmsr(0x2018);
+ msr = rdmsr(MC_CF07_DATA);
msr.lo |= (0x01 3);
- wrmsr(0x2018, msr);
+ wrmsr(MC_CF07_DATA, msr);
msr.lo = ~(0x01 3);
- wrmsr(0x2018, msr);
+ wrmsr(MC_CF07_DATA, msr);
}
//print_debug(sdram_enable step 4\n);
@@ -53,29 +53,29 @@
//print_debug(sdram_enable step 5\n);
/* 6. enable DLL, load Extended Mode Register by set and clear
PROG_DRAM */
- msr = rdmsr(0x2018);
+ msr = rdmsr(MC_CF07_DATA);
msr.lo |= ((0x01 28) | 0x01);
- wrmsr(0x2018, msr);
+ wrmsr(MC_CF07_DATA, msr);
msr.lo = ~((0x01 28) | 0x01);
- wrmsr(0x2018, msr);
+ wrmsr(MC_CF07_DATA, msr);
//print_debug(sdram_enable step 6\n);
/* 7. Reset DLL, Bit 27 is undocumented in GX datasheet,
* it is documented in LX datasheet */
/* load Mode Register by set and clear PROG_DRAM */
- msr = rdmsr(0x2018);
+ msr = rdmsr(MC_CF07_DATA);
msr.lo |= ((0x01 27) | 0x01);
- wrmsr(0x2018, msr);
+ wrmsr(MC_CF07_DATA, msr);
msr.lo = ~((0x01 27) | 0x01);
- wrmsr(0x2018, msr);
+ wrmsr(MC_CF07_DATA, msr);
//print_debug(sdram_enable step 7\n);
/* 8. load Mode Register by set and clear PROG_DRAM */
- msr = rdmsr(0x2018);
+ msr = rdmsr(MC_CF07_DATA);
msr.lo |= 0x01;
- wrmsr(0x2018, msr);
+ wrmsr(MC_CF07_DATA, msr);
msr.lo = ~0x01;
- wrmsr(0x2018, msr);
+ wrmsr(MC_CF07_DATA, msr);
//print_debug(sdram_enable step 8\n);
/* wait 200 SDCLKs */
@@ -83,7 +83,7 @@
outb(0xaa, 0x80);
/* load RDSYNC */
- msr = rdmsr(0x201f);
+ msr = rdmsr(MC_CF_RDSYNC);
msr.hi = 0x000ff310;
/* the above setting is supposed to be good for slow ram. We have
found that for
* some dram, at some clock rates, e.g. hynix at 366/244, this will
actually
@@ -94,13 +94,13 @@
*/
msr.hi = 0x0310;
msr.lo = 0x;
- wrmsr(0x201f, msr);
+ wrmsr(MC_CF_RDSYNC, msr);
/* set delay control */
- msr = rdmsr(0x4c0f);
+ msr = rdmsr(GLCP_DELAY_CONTROLS);
msr.hi = 0x830d415a;
msr.lo = 0x8ea0ad6a;
- wrmsr(0x4c0f, msr);
+ wrmsr(GLCP_DELAY_CONTROLS, msr);
/* The RAM dll needs a write to lock on so generate a few dummy writes
*/
/* Note: The descriptor needs to be enabled to point at memory */
--
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[coreboot] [commit] r6009 - in trunk/src: include/cpu/amd northbridge/amd/gx2
Author: uwe Date: Mon Nov 1 15:36:54 2010 New Revision: 6009 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6009 Log: GX2: Clean up some white space and comments. Also, add a copyright header to pll_reset.c. Signed-off-by: Nils Jacobs njaco...@hetnet.nl Acked-by: Uwe Hermann u...@hermann-uwe.de Modified: trunk/src/include/cpu/amd/gx2def.h trunk/src/northbridge/amd/gx2/pll_reset.c Modified: trunk/src/include/cpu/amd/gx2def.h == --- trunk/src/include/cpu/amd/gx2def.h Mon Nov 1 15:18:11 2010(r6008) +++ trunk/src/include/cpu/amd/gx2def.h Mon Nov 1 15:36:54 2010(r6009) @@ -1,5 +1,6 @@ #ifndef CPU_AMD_GX2DEF_H #define CPU_AMD_GX2DEF_H + #defineCPU_ID_1_X 0x540 /* Stepping ID 1.x*/ #defineCPU_ID_2_0 0x551 /* Stepping ID 2.0*/ #defineCPU_ID_2_1 0x552 /* Stepping ID 2.1*/ @@ -13,6 +14,7 @@ #defineCPU_REV_2_1 0x021 #defineCPU_REV_2_2 0x022 #defineCPU_REV_3_0 0x030 + /* GeodeLink Control Processor Registers, GLIU1, Port 3 */ #defineGLCP_CLK_DIS_DELAY 0x4c08 #defineGLCP_PMCLKDISABLE 0x4c09 @@ -37,28 +39,27 @@ #defineGLCP_SYS_RSTPLL_PCI_SEMI_SYNC_MODE 8 #defineGLCP_SYS_RSTPLL_CHIP_RESET 0 -/* MSR routing as follows*/ -/* MSB = 1 means not for CPU*/ -/* next 3 bits 1st port*/ -/* next3 bits next port if through an GLIU*/ -/* etc...*/ +/* MSR routing as follows */ +/* MSB = 1 means not for CPU */ +/* next 3 bits 1st port */ +/* next3 bits next port if through an GLIU */ +/* etc... */ -/*Redcloud as follows.*/ +/* Redcloud as follows. */ /* GLIU0*/ -/* port0 - GLIU0*/ -/* port1 - MC*/ -/* port2 - GLIU1*/ -/* port3 - CPU*/ -/* port4 - VG*/ -/* port5 - GP*/ -/* port6 - DF*/ +/* port0 - GLIU0 */ +/* port1 - MC */ +/* port2 - GLIU1 */ +/* port3 - CPU */ +/* port4 - VG */ +/* port5 - GP */ +/* port6 - DF */ /* GLIU1*/ -/* port1 - GLIU0*/ -/* port3 - GLCP*/ -/* port4 - PCI*/ -/* port5 - FG*/ - +/* port1 - GLIU0 */ +/* port3 - GLCP */ +/* port4 - PCI */ +/* port5 - FG */ #defineGL0_GLIU0 0 #defineGL0_MC 1 @@ -78,7 +79,7 @@ #defineMSR_GLIU0 (GL0_GLIU0 29) + (1 28) /* 1000 - To get on GeodeLink one bit has to be set */ #defineMSR_MC (GL0_MC 29) /* 2000 */ #defineMSR_GLIU1 (GL0_GLIU1 29) /* 4000 */ -#defineMSR_CPU (GL0_CPU 29) /* 6000 - this is not used for BIOS since code executing on CPU doesn't need to be routed*/ +#defineMSR_CPU (GL0_CPU 29) /* 6000 - this is not used for BIOS since code executing on CPU doesn't need to be routed */ #defineMSR_VG (GL0_VG 29) /* 8000 */ #defineMSR_GP (GL0_GP 29) /* A000 */ #defineMSR_DF (GL0_DF 29) /* C000 */ @@ -88,14 +89,11 @@ #defineMSR_FG (GL1_FG 26) + MSR_GLIU1 /* 5400 */ #define MSR_VIP((GL1_VIP 26) + MSR_GLIU1) /* 5400 */ #define MSR_AES((GL1_AES 26) + MSR_GLIU1) /* 5800 */ -/* South Bridge*/ -#define SB_PORT2 /* port of the SouthBridge */ - -/**/ -/*GeodeLink Interface Unit 0 (GLIU0) port0*/ -/**/ +/* South Bridge */ +#define SB_PORT2 /* port of the SouthBridge */ +/* GeodeLink Interface Unit 0 (GLIU0) port0 */ #defineGLIU0_GLD_MSR_CAP (MSR_GLIU0 + 0x2000) #defineGLIU0_GLD_MSR_PM(MSR_GLIU0 + 0x2004) @@ -103,10 +101,7 @@ #defineGLIU0_CAP (MSR_GLIU0 + 0x86) #defineGLIU0_GLD_MSR_COH (MSR_GLIU0 + 0x80) - -/**/ -/* Memory Controller GLIU0 port 1*/ -/**/ +/* Memory Controller GLIU0 port 1 */ #defineMC_GLD_MSR_CAP (MSR_MC + 0x2000) #defineMC_GLD_MSR_PM (MSR_MC + 0x2004) @@ -129,7 +124,6 @@ #defineCF07_LOWER_REF_TEST_SET (1 3) #defineCF07_LOWER_PROG_DRAM_SET(1 0) - #defineMC_CF8F_DATA
Re: [coreboot] [PATCH 2/4] Geode GX2 auto DRAM detect patch V2
On Sun, Oct 31, 2010 at 10:57:58PM +0100, Nils wrote: This patch cleans up some white space and comments. It also adds a copyright header to pll_reset.c . Signed-off-by: Nils Jacobs njaco...@hetnet.nl Thanks, r6009. I took the freedom to do a few more whitespace cleanups. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r6010 - trunk/src/northbridge/amd/gx2
Author: uwe
Date: Mon Nov 1 15:39:49 2010
New Revision: 6010
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6010
Log:
Remove some unused code.
Signed-off-by: Nils Jacobs njaco...@hetnet.nl
Acked-by: Uwe Hermann u...@hermann-uwe.de
Modified:
trunk/src/northbridge/amd/gx2/pll_reset.c
Modified: trunk/src/northbridge/amd/gx2/pll_reset.c
==
--- trunk/src/northbridge/amd/gx2/pll_reset.c Mon Nov 1 15:36:54 2010
(r6009)
+++ trunk/src/northbridge/amd/gx2/pll_reset.c Mon Nov 1 15:39:49 2010
(r6010)
@@ -24,69 +24,6 @@
#define CALIBRATE_INTERVAL ((20*CLOCK_TICK_RATE)/1000) /* 20ms */
#define CALIBRATE_DIVISOR (20*1000) /* 20ms / 2 == 1usec */
-#if 0
-static unsigned int calibrate_tsc(void)
-{
- /* Set the Gate high, disable speaker */
- outb((inb(0x61) ~0x02) | 0x01, 0x61);
-
- /*
-* Now let's take care of CTC channel 2
-*
-* Set the Gate high, program CTC channel 2 for mode 0,
-* (interrupt on terminal count mode), binary count,
-* load 5 * LATCH count, (LSB and MSB) to begin countdown.
-*/
- outb(0xb0, 0x43); /* binary, mode 0, LSB/MSB, Ch
2 */
- outb(CALIBRATE_INTERVAL 0xff, 0x42); /* LSB of count */
- outb(CALIBRATE_INTERVAL 8, 0x42);/* MSB of count */
-
- {
- tsc_t start;
- tsc_t end;
- unsigned long count;
-
- start = rdtsc();
- count = 0;
- do {
- count++;
- } while ((inb(0x61) 0x20) == 0);
- end = rdtsc();
-
- /* Error: ECTCNEVERSET */
- if (count = 1)
- goto bad_ctc;
-
- /* 64-bit subtract - gcc just messes up with long longs */
- __asm__(subl %2,%0\n\t
- sbbl %3,%1
- :=a (end.lo), =d (end.hi)
- :g (start.lo), g (start.hi),
-0 (end.lo), 1 (end.hi));
-
- /* Error: ECPUTOOFAST */
- if (end.hi)
- goto bad_ctc;
-
-
- /* Error: ECPUTOOSLOW */
- if (end.lo = CALIBRATE_DIVISOR)
- goto bad_ctc;
-
- return (end.lo + CALIBRATE_DIVISOR -1)/CALIBRATE_DIVISOR;
- }
-
- /*
-* The CTC wasn't reliable: we got a hit on the very first read,
-* or the CPU was so fast/slow that the quotient wouldn't fit in
-* 32 bits..
-*/
-bad_ctc:
- print_err(bad_ctc\n);
- return 0;
-}
-#endif
-
/* spll_raw_clk = SYSREF * FbDIV,
* GLIU Clock = spll_raw_clk / MDIV
* CPU Clock= spll_raw_clk / VDIV
@@ -108,17 +45,6 @@
49, 40, 19, 59, 32, 54, 35, 0, 41, 60, 55, 0, 61, 0, 0, 0
};
-static const unsigned char pci33_ddr_crt [] = {
- /* FbDIV, VDIV, MDIV CPU/GeodeLink */
-12,2,3,// 200/133
-16,2,3,// 266/177
- 18,2,3, // 300/200
- 20,2,3, // 333/222
- 22,2,3, // 366/244
- 24,2,3, // 400/266
- 26,2,3 // 433/289
-};
-
/* FbDIV VDIVMDIVCPU/GeodeLink */
/* 12 2 3 200/133 */
/* 16 2 3 266/177 */
@@ -128,31 +54,12 @@
/* 24 2 3 400/266 */
/* 26 2 3 433/289 */
-#if 0
-static unsigned int get_memory_speed(void)
-{
- unsigned char val, hi, lo;
-
- val = spd_read_byte(0xA0, 9);
- hi = (val 4) 0x0f;
- lo = val 0x0f;
-
- return 2/(hi*10 + lo);
-}
-#endif
-
-#define USE_GOODRICH_VERSION 1
-
-#if USE_GOODRICH_VERSION
-///
-// Goodrich Version of pll_reset
-
/* PLLCHECK_COMPLETED is the we've already done this flag */
#define PLLCHECK_COMPLETED (1 RSTPLL_LOWER_SWFLAGS_SHIFT)
#ifndef RSTPPL_LOWER_BYPASS_SET
#define RSTPPL_LOWER_BYPASS_SET (1 GLCP_SYS_RSTPLL_BYPASS)
-#endif /* RSTPPL_LOWER_BYPASS_SET */
+#endif // RSTPPL_LOWER_BYPASS_SET
#define DEFAULT_MDIV 3
#define DEFAULT_VDIV 2
@@ -218,7 +125,7 @@
/* CheckSemiSync proc */
/* Check for Semi-Sync in GeodeLink and CPU. */
/* We need to do this here since the strap settings don't
account for these bits. */
- SyncBits = 0; // store the sync bits in up ebx
+ SyncBits = 0; /* store the sync bits in up
ebx */
/* Check for Bypass mode. */
if (msrGlcpSysRstpll.lo RSTPPL_LOWER_BYPASS_SET)
@@ -247,7 +154,6 @@
}
}
-
/*
Re: [coreboot] [PATCH 3/4] Geode GX2 auto DRAM detect patch V2
On Sun, Oct 31, 2010 at 10:58:06PM +0100, Nils wrote: This patch removes some unused code. Signed-off-by: Nils Jacobs njaco...@hetnet.nl Thanks, r6010. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH 1/4] Geode GX2 auto DRAM detect patch V2
On Sun, Oct 31, 2010 at 10:57:51PM +0100, Nils wrote: This patch changes the MSR register numbers in to more descriptive names. Signed-off-by: Nils Jacobs njaco...@hetnet.nl Thanks, r6008. I cross-checked against the datasheet and gx2def.h. /* 3. release CKE mask to enable CKE */ - msr = rdmsr(0x201d); + msr = rdmsr(MC_CFCLK_DBUG); msr.lo = ~(0x03 8); - wrmsr(0x2000201d, msr); + wrmsr(MC_CFCLK_DBUG, msr); Heh, fun. This was a bug anyway (0x201d vs. 0x2000201d). Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Trac reminder: list of new ticket(s)
Ticket Owner Status Description #168 ste...@coresystems.de new USBDEBUG might slow down coreboot #162 oxygene new Move SYSTEM_TYPE to Kconfig #160 oxygene new Build system: There's no convincing CFLAGS management for util/* #158 w...@gnu.org new buildrom svn error #156 hailfinger new Add Layout File capability to v3 and LAR tool #154 hailfinger new Flashing BIOSes from Fujitsu/Siemens is not supported #150 somebody new AMD DB800 dev board PLL strapping leaves CPU and GLIU in non-optimal clock #147 somebody new Linux kernel halts when scanning the PCI bus below 0:14.4 on RS690 #145 somebody new Fix CMOS handling #143 oxygene new unify intel car for model_6[ef]x #135 ward new Flashrom deletes MAC addresses on Tyan Tomcat n3400B (S2925-E) #129 stepan new etherboot payload does not work with HIGH_TABLES #128 somebody new Improve email user interface for trac #125 somebody new BCM5785 / HT1000 reset functions #111 somebody new Add i18n support for translating strings e.g. for bayou / coreinfo #110 somebody new Allow for per-device subsystem IDs #77 somebody new hang on the "Jumping to coreboot" step on via epia-m with 4-chip 128Mbyte DDR module #76 rminnich new coreboot messages should be accessible in dmesg #18 oxygene new autoprobe apic cluster and application processors on K8 systems #17 stepan new clean up coreboot table handling #16 ollie new I2C driver and mainboard Config.lb #11 yhlu new pirq table automation #5 uwe new Add license header to all source files #2 somebody new Complete tables of supported motherboards -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r6011 - in trunk/src: include/cpu/amd mainboard/amd/rumba mainboard/lippert/frontrunner mainboard/wyse/s50 northbridge/amd/gx2
Author: uwe
Date: Mon Nov 1 16:20:27 2010
New Revision: 6011
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6011
Log:
Change Geode GX2 to use the auto DRAM detect code from Geode LX.
Also, change the GX2 boards to use it.
Add a processor speed setting function in human readable MHz and remove
the useless and broken PLLMSR settings (the processor speed was hardcoded
to 366MHz in pll_reset.c).
Signed-off-by: Nils Jacobs njaco...@hetnet.nl
Acked-by: Uwe Hermann u...@hermann-uwe.de
Modified:
trunk/src/include/cpu/amd/gx2def.h
trunk/src/mainboard/amd/rumba/romstage.c
trunk/src/mainboard/lippert/frontrunner/Kconfig
trunk/src/mainboard/lippert/frontrunner/romstage.c
trunk/src/mainboard/wyse/s50/romstage.c
trunk/src/northbridge/amd/gx2/Kconfig
trunk/src/northbridge/amd/gx2/pll_reset.c
trunk/src/northbridge/amd/gx2/raminit.c
Modified: trunk/src/include/cpu/amd/gx2def.h
==
--- trunk/src/include/cpu/amd/gx2def.h Mon Nov 1 15:39:49 2010(r6010)
+++ trunk/src/include/cpu/amd/gx2def.h Mon Nov 1 16:20:27 2010(r6011)
@@ -413,6 +413,13 @@
#define AES_GLD_MSR_PM (MSR_AES + 0x2004)
#define AES_CONTROL(MSR_AES + 0x2006)
+/* from MC spec */
+#define MIN_MOD_BANKS 1
+#define MAX_MOD_BANKS 2
+#define MIN_DEV_BANKS 2
+#define MAX_DEV_BANKS 4
+#define MAX_COL_ADDR 17
+
/* more fun stuff */
#define BM 1 /* Base Mask - map power of 2 size
aligned region */
#define BMO2 /* BM with an offset */
Modified: trunk/src/mainboard/amd/rumba/romstage.c
==
--- trunk/src/mainboard/amd/rumba/romstage.cMon Nov 1 15:39:49 2010
(r6010)
+++ trunk/src/mainboard/amd/rumba/romstage.cMon Nov 1 16:20:27 2010
(r6011)
@@ -15,87 +15,21 @@
#include southbridge/amd/cs5536/cs5536_early_smbus.c
#include southbridge/amd/cs5536/cs5536_early_setup.c
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-return smbus_read_byte(device, address);
-}
+#define DIMM0 0xA0
+#define DIMM1 0xA2
-#include northbridge/amd/gx2/raminit.h
-
-static inline unsigned int fls(unsigned int x)
-{
-int r;
-
-__asm__(bsfl %1,%0\n\t
-jnz 1f\n\t
-movl $32,%0\n
-1: : =r (r) : g (x));
-return r;
-}
-
-static void sdram_set_spd_registers(const struct mem_controller *ctrl)
+static inline int spd_read_byte(unsigned device, unsigned address)
{
- /* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4)
*
-* component Banks (byte 17) * module banks, side
(byte 5) *
-* width in bits (byte 6,7)
-*= Density per side (byte 31) * number of sides
(byte 5) */
- /* 1. Initialize GLMC registers base on SPD values, do one DIMM for now
*/
- msr_t msr;
- unsigned char module_banks, val;
-
- msr = rdmsr(MC_CF07_DATA);
-
- /* get module banks (sides) per dimm, SPD byte 5 */
- module_banks = spd_read_byte(0xA0, 5);
- if (module_banks 1 || module_banks 2)
- print_err(Module banks per dimm\n);
- module_banks = 1;
- msr.hi = ~(1 CF07_UPPER_D0_MB_SHIFT);
- msr.hi |= (module_banks CF07_UPPER_D0_MB_SHIFT);
-
- /* get component banks per module bank, SPD byte 17 */
- val = spd_read_byte(0xA0, 17);
- if (val 2 || val 4)
- print_err(Component banks per module bank\n);
- val = 2;
- msr.hi = ~(0x1 CF07_UPPER_D0_CB_SHIFT);
- msr.hi |= (val CF07_UPPER_D0_CB_SHIFT);
-
- /* get the module bank density, SPD byte 31 */
- val = spd_read_byte(0xA0, 31);
- val = fls(val);
- val = module_banks;
- msr.hi = ~(0xf CF07_UPPER_D0_SZ_SHIFT);
- msr.hi |= (val CF07_UPPER_D0_SZ_SHIFT);
-
- /* page size = 2^col address */
- val = spd_read_byte(0xA0, 4);
- val -= 7;
- msr.hi = ~(0x7 CF07_UPPER_D0_PSZ_SHIFT);
- msr.hi |= (val CF07_UPPER_D0_PSZ_SHIFT);
-
- print_debug(computed msr.hi );
- print_debug_hex32(msr.hi);
- print_debug(\n);
-
- msr.lo = 0x3000;
- wrmsr(MC_CF07_DATA, msr);
-
- msr = rdmsr(0x2019);
- msr.hi = 0x18000108;
- msr.lo = 0x696332a3;
- wrmsr(0x2019, msr);
+ if (device != DIMM0)
+ return 0xFF;/* No DIMM1, don't even try. */
+ return smbus_read_byte(device, address);
}
+#include northbridge/amd/gx2/raminit.h
+#include northbridge/amd/gx2/pll_reset.c
#include northbridge/amd/gx2/raminit.c
#include lib/generic_sdram.c
-
-#define PLLMSRhi 0x1490
-#define PLLMSRlo 0x0230
-#define PLLMSRlo1 ((0xde 16) | (1 26) | (1 24))
-#define PLLMSRlo2 ((114)
Re: [coreboot] [PATCH 4/4] Geode GX2 auto DRAM detect patch V2
On Sun, Oct 31, 2010 at 10:58:28PM +0100, Nils wrote:
This patch changes Geode GX2 to use the auto DRAM detect code
from Geode LX and changes the boards to use it.
It also adds a processor speed setting function in human
readable Mhz and removes the useless and broken PLLMSR settings.
(the processor speed was hardcoded to 366Mhz in pll_reset.c)
Signed-off-by: Nils Jacobs njaco...@hetnet.nl
Thanks, r6011 with some small whitespace changes and s/Mhz/MHz/.
Index: src/northbridge/amd/gx2/Kconfig
===
--- src/northbridge/amd/gx2/Kconfig (revision 6006)
+++ src/northbridge/amd/gx2/Kconfig (working copy)
@@ -21,3 +21,9 @@
bool
select GEODE_VSA
+# Valid PROCESSOR_MHZ options: 300 ; 366 ; 400 Mhz
+config PROCESSOR_MHZ
+ int
+ default 366
+ depends on NORTHBRIDGE_AMD_GX2
Maybe we could make a GX2_PROCESSOR_MHZ_300, GX2_PROCESSOR_MHZ_366 etc.
here, and let each board select the correct one in its Kconfig file?
+static void banner(const char *s)
+{
+ printk(BIOS_DEBUG, * %s\n, s);
+}
I'd personally drop this (also in the LX code), let's just use printk(),
there's no reason to add such a mini-wrapper.
+ if (CONFIG_PROCESSOR_MHZ == 400){
+ DEFAULT_FBDIV = 24;
+ }
+ else if (CONFIG_PROCESSOR_MHZ == 366){
+ DEFAULT_FBDIV = 22;
+ }
+ else if (CONFIG_PROCESSOR_MHZ == 300){
+ DEFAULT_FBDIV = 18;
+ } else {
+ printk(BIOS_ERR, Unsupported PROCESSOR_MHZ setting !\n);
+ post_code(POST_PLL_CPU_VER_FAIL);
+ __asm__ __volatile__(hlt\n);
Shouldn't there be a while (1) around the hlt instruction?
Uwe.
--
http://hermann-uwe.de | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org
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[coreboot] [PATCH] don't print too early on mcp55-based boards
See attached. Perhaps we should also print a post code if the SMBus
controller can't be found - suggestions for a value?
Thanks,
Ward.
--
Ward Vandewege w...@fsf.org
Free Software Foundation - Senior Systems Administrator
We can't print this early.
This patch fixes a hang on
supermicro/h8dme
supermicro/h8dmr
supermicro/h8dmr_fam10
and possibly on other mcp55-based boards.
Signed-off-by: Ward Vandewege w...@gnu.org
Index: src/southbridge/nvidia/mcp55/mcp55_early_smbus.c
===
--- src/southbridge/nvidia/mcp55/mcp55_early_smbus.c (revision 6011)
+++ src/southbridge/nvidia/mcp55/mcp55_early_smbus.c (working copy)
@@ -32,11 +32,8 @@
device_t dev;
dev = pci_locate_device(PCI_ID(0x10de, 0x0368), 0);
- if (dev == PCI_DEV_INVALID) {
- printk(BIOS_WARNING, SMBUS controller not found\n);
- } else {
- printk(BIOS_DEBUG, SMBus controller enabled\n);
- }
+ if (dev == PCI_DEV_INVALID)
+ die(SMBus controller not found\n);
/* set smbus iobase */
pci_write_config32(dev, 0x20, SMBUS0_IO_BASE | 1);
--
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Re: [coreboot] [PATCH 0/4] Geode GX2 auto DRAM detect patch V2
Hi Uwe, Thanks for the fast review and commit! Heh, fun. This was a bug anyway (0x201d vs. 0x2000201d). Yes. Thanks, r6009. I took the freedom to do a few more whitespace cleanups. Thanks, i must have overlooked them. Thanks, r6011 with some small whitespace changes and s/Mhz/MHz/. OK thanks. Maybe we could make a GX2_PROCESSOR_MHZ_300, GX2_PROCESSOR_MHZ_366 etc. here, and let each board select the correct one in its Kconfig file? This sounds good, i actually thought about something like that but i didn’t quite know how. And because at the moment there are only boards with 366 Mhz so i skipped it. I will study it some more and try to make a patch for it. I'd personally drop this (also in the LX code), let's just use printk(), there's no reason to add such a mini-wrapper. I copied it from LX. I will make a patch for that when i find some time. Shouldn't there be a while (1) around the hlt instruction? ?? i don't know should it? The code seems to work, but if it is preferred/needed i will add it. Can you point me to some example code or could you supply some code snipped i can test? Thanks, Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [superiotool] patch for fintek f71889fg
The patch (attached) was tested by a user on IRC who had the F71889FG. I
wrote it using documentation from Fintek's website available here:
http://www.fintek.com.tw/files/productfiles/F71889_V0.28P.pdf
This patch also seems to work for the F71889ED, which uses 0x09 and 0x09 for
chip ID bytes 1 2. However, I have not been able to find documentation to
verify that the two chips are identical from superiotool's perspective.
The F71889 seems popular on current generation platforms with AMD chipsets,
in case there are folks looking to try it on a presently unsupported
board...
Signed-off-by: David Hendricks dhend...@google.com
--
David Hendricks (dhendrix)
Systems Software Engineer, Google Inc.
Index: fintek.c
===
--- fintek.c (revision 5953)
+++ fintek.c (working copy)
@@ -122,6 +122,50 @@
{0x30,0xf0,0xf1,0xf4,0xf5,EOT},
{0x00,0x00,0x01,0x06,0x1c,EOT}},
{EOT}}},
+ {0x2307, F71889FG, {
+ /* We assume reserved bits are read as 0. */
+ {NOLDN, NULL,
+ {0x20,0x21,0x23,0x24,0x25,0x26,0x27,0x28,0x29,0x2a,
+ 0x2b,0x2c,0x2d,EOT},
+ {0x05,0x41,0x19,0x34,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x08,0x08,EOT}},
+ {0x0, Floppy,
+ {0x30,0x60,0x61,0x70,0x74,0xf0,0xf2,0xf4,EOT},
+ {0x01,0x03,0xf0,0x06,0x02,0x0e,0x03,0x00,EOT}},
+ {0x1, COM1,
+ {0x30,0x60,0x61,0x70,0xf0,EOT},
+ {0x01,0x03,0xf8,0x04,0x00,EOT}},
+ {0x2, COM2,
+ {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT},
+ {0x01,0x02,0xf8,0x03,0x00,0x04,EOT}},
+ {0x3, Parallel port,
+ {0x30,0x60,0x61,0x70,0x74,0xf0,EOT},
+ {0x01,0x03,0x78,0x07,0x03,0x42,EOT}},
+ {0x4, Hardware monitor,
+ {0x30,0x60,0x61,0x70,EOT},
+ {0x01,0x02,0x95,0x00,EOT}},
+ {0x5, Keyboard,
+ {0x30,0x60,0x61,0x70,0x72,0xf0,EOT},
+ {0x01,0x00,0x60,0x00,0x00,0x83,EOT}},
+ {0x6, GPIO,
+ {0x70,0xe0,0xe1,0xe2,0xe3,0xd0,0xd1,0xd2,0xd3,0xc0,
+ 0xc1,0xc2,0xc3,0xb0,0xb1,0xb2,0xb3,0xf0,0xf1,0xf2,
+ 0xf3,EOT},
+ {0x00,0x00,0xff,NANA,0x00,0x00,0xff,NANA,0x00,0x00,
+ 0x0f,NANA,0x00,0x00,0x0f,NANA,0x00,0x00,0xff,NANA,
+ 0x00,EOT}},
+ {0x7, VID,
+ {0x30,0x60,0x61,EOT},
+ {0x00,0x00,0x00,EOT}},
+ {0x7, SPI,
+ {0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xfa,
+ 0xfb,0xfc,0xfd,0xfe,0xff,EOT},
+ {0x10,0x04,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,EOT}},
+ {0xa, PME, ACPI,
+ {0x30,0xf0,0xf1,0xf4,0xf5,EOT},
+ {0x00,0x00,0x01,0x06,0x1c,EOT}},
+ {EOT}}},
{0x0604, F71805F/FG, {
/* We assume reserved bits are read as 0. */
{NOLDN, NULL,
--
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[coreboot] Fw: Re: [superiotool] patch for fintek f71889fg
--- On Mon, 11/1/10, Neo The User neotheu...@ymail.com wrote: From: Neo The User neotheu...@ymail.com Subject: Re: [superiotool] patch for fintek f71889fg To: David Hendricks dhend...@google.com Date: Monday, November 1, 2010, 9:04 PM Works and tested on f71889fg super IO (motherboard MS785GT-E63) -Alec Ari --- On Mon, 11/1/10, David Hendricks dhend...@google.com wrote: From: David Hendricks dhend...@google.com Subject: [superiotool] patch for fintek f71889fg To: Coreboot coreboot@coreboot.org Cc: neotheu...@ymail.com Date: Monday, November 1, 2010, 8:02 PM The patch (attached) was tested by a user on IRC who had the F71889FG. I wrote it using documentation from Fintek's website available here: http://www.fintek.com.tw/files/productfiles/F71889_V0.28P.pdf This patch also seems to work for the F71889ED, which uses 0x09 and 0x09 for chip ID bytes 1 2. However, I have not been able to find documentation to verify that the two chips are identical from superiotool's perspective. The F71889 seems popular on current generation platforms with AMD chipsets, in case there are folks looking to try it on a presently unsupported board... Signed-off-by: David Hendricks dhend...@google.com -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] don't print too early on mcp55-based boards
Ward Vandewege wrote: See attached. Perhaps we should also print a post code if the SMBus controller can't be found - suggestions for a value? 0x5B ? We can't print this early. This patch fixes a hang on supermicro/h8dme supermicro/h8dmr supermicro/h8dmr_fam10 and possibly on other mcp55-based boards. Signed-off-by: Ward Vandewege w...@gnu.org Acked-by: Peter Stuge pe...@stuge.se -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Trouble converting Truxton to CAR
Hello, After all the excitement of converting the i810 boards to CAR, I've been looking at converting the Truxton board to cache-as-RAM. However, I'm not sure how to validate that the cpu/intel/car/cache_as_ram.inc code is valid for an Intel EP80579. Is there a way I can validate that this CPU will work with the existing CAR code? I've gone so far as doing a code-n-pray conversion, but my linux boot hangs at Jumping to Entry and running memtest causes it to bork on Test #2 with an unhandled interrupt. Cheers Dustin -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
