llvmbot wrote:
@llvm/pr-subscribers-backend-risc-v
Author: Pengcheng Wang (wangpc-pp)
Changes
This PR includes:
* vsadd.vv/vsaddu.vv
* vaadd.vv/vaaddu.vv
* vsmul.vv
---
Full diff: https://github.com/llvm/llvm-project/pull/90372.diff
3 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (+5)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td (+16-13)
- (modified) llvm/test/CodeGen/RISCV/rvv/commutable.ll (+6-8)
``diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 3efd09aeae879d..8cb9a40a98bcd8 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -3132,6 +3132,11 @@ bool RISCVInstrInfo::findCommutedOpIndices(const
MachineInstr ,
case CASE_RVV_OPCODE_WIDEN(VWMACC_VV):
case CASE_RVV_OPCODE_WIDEN(VWMACCU_VV):
case CASE_RVV_OPCODE_UNMASK(VADC_VVM):
+ case CASE_RVV_OPCODE(VSADD_VV):
+ case CASE_RVV_OPCODE(VSADDU_VV):
+ case CASE_RVV_OPCODE(VAADD_VV):
+ case CASE_RVV_OPCODE(VAADDU_VV):
+ case CASE_RVV_OPCODE(VSMUL_VV):
// Operands 2 and 3 are commutable.
return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3);
case CASE_VFMA_SPLATS(FMADD):
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index e9715b40adc079..fc60a9cc7cd30e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -2146,8 +2146,9 @@ multiclass VPseudoBinaryRoundingMode {
- let VLMul = MInfo.value, SEW=sew in {
+ int TargetConstraintType = 1,
+ bit Commutable = 0> {
+ let VLMul = MInfo.value, SEW=sew, isCommutable = Commutable in {
defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);
def suffix : VPseudoBinaryNoMaskRoundingMode;
}
-multiclass VPseudoBinaryV_VV_RM {
- defm _VV : VPseudoBinaryRoundingMode;
+multiclass VPseudoBinaryV_VV_RM {
+ defm _VV : VPseudoBinaryRoundingMode;
}
// Similar to VPseudoBinaryV_VV, but uses MxListF.
@@ -2715,10 +2717,11 @@ multiclass VPseudoVGTR_VV_VX_VI
}
}
-multiclass VPseudoVSALU_VV_VX_VI {
+multiclass VPseudoVSALU_VV_VX_VI {
foreach m = MxList in {
defvar mx = m.MX;
-defm "" : VPseudoBinaryV_VV,
+defm "" : VPseudoBinaryV_VV,
SchedBinary<"WriteVSALUV", "ReadVSALUV", "ReadVSALUX", mx,
forceMergeOpRead=true>;
defm "" : VPseudoBinaryV_VX,
@@ -2788,7 +2791,7 @@ multiclass VPseudoVSALU_VV_VX {
multiclass VPseudoVSMUL_VV_VX_RM {
foreach m = MxList in {
defvar mx = m.MX;
-defm "" : VPseudoBinaryV_VV_RM,
+defm "" : VPseudoBinaryV_VV_RM,
SchedBinary<"WriteVSMulV", "ReadVSMulV", "ReadVSMulV", mx,
forceMergeOpRead=true>;
defm "" : VPseudoBinaryV_VX_RM,
@@ -2797,10 +2800,10 @@ multiclass VPseudoVSMUL_VV_VX_RM {
}
}
-multiclass VPseudoVAALU_VV_VX_RM {
+multiclass VPseudoVAALU_VV_VX_RM {
foreach m = MxList in {
defvar mx = m.MX;
-defm "" : VPseudoBinaryV_VV_RM,
+defm "" : VPseudoBinaryV_VV_RM,
SchedBinary<"WriteVAALUV", "ReadVAALUV", "ReadVAALUV", mx,
forceMergeOpRead=true>;
defm "" : VPseudoBinaryV_VX_RM,
@@ -6448,8 +6451,8 @@ defm PseudoVMV_V : VPseudoUnaryVMV_V_X_I;
// 12.1. Vector Single-Width Saturating Add and Subtract
//===--===//
let Defs = [VXSAT], hasSideEffects = 1 in {
- defm PseudoVSADDU : VPseudoVSALU_VV_VX_VI;
- defm PseudoVSADD : VPseudoVSALU_VV_VX_VI;
+ defm PseudoVSADDU : VPseudoVSALU_VV_VX_VI;
+ defm PseudoVSADD : VPseudoVSALU_VV_VX_VI;
defm PseudoVSSUBU : VPseudoVSALU_VV_VX;
defm PseudoVSSUB : VPseudoVSALU_VV_VX;
}
@@ -6457,8 +6460,8 @@ let Defs = [VXSAT], hasSideEffects = 1 in {
//===--===//
// 12.2. Vector Single-Width Averaging Add and Subtract
//===--===//
-defm PseudoVAADDU : VPseudoVAALU_VV_VX_RM;
-defm PseudoVAADD : VPseudoVAALU_VV_VX_RM;
+defm PseudoVAADDU : VPseudoVAALU_VV_VX_RM;
+defm PseudoVAADD : VPseudoVAALU_VV_VX_RM;
defm PseudoVASUBU : VPseudoVAALU_VV_VX_RM;
defm PseudoVASUB : VPseudoVAALU_VV_VX_RM;
diff --git a/llvm/test/CodeGen/RISCV/rvv/commutable.ll
b/llvm/test/CodeGen/RISCV/rvv/commutable.ll
index e383c1b477c45d..06a6327d3892b6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/commutable.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/commutable.ll
@@ -724,10 +724,9 @@ define @commutable_vaadd_vv( %0, @llvm.riscv.vaadd.nxv1i64.nxv1i64( undef, %0, %1, iXLen 0, iXLen %2)
@@ -743,7 +742,7 @@ define
@commutable_vaadd_vv_masked( %0, @commutable_vaaddu_vv( %0, @llvm.riscv.vaaddu.nxv1i64.nxv1i64( undef, %0, %1, iXLen 0, iXLen %2)
@@ -779,7 +777,7 @@ define
