hould be considered for SHA calculation or not.
>
> Given that the KEXEC_UPDATE_ELFCOREHDR is no longer required and was
> colliding with the KEXEC_LIVE_UPDATE update flag, it is removed.
>
> Cc: Aditya Gupta
> Cc: Baoquan He
> Cc: Coiby Xu
> Cc: Hari Bathini
> Cc: Mahesh
Power11 core is same as Power10, reuse PNV10_SBER initialisation, by
declaring PNV11_PSI as child class of PNV10_PSI
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
-by: Aditya Gupta
---
docs/system/ppc/pseries.rst | 6 +++---
hw/ppc/spapr_cpu_core.c | 1 +
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/docs/system/ppc/pseries.rst b/docs/system/ppc/pseries.rst
index a876d897b6e4..3277564b34c2 100644
--- a/docs/system/ppc/pseries.rst
+++ b/docs
Cc: Nicholas Piggin
Signed-off-by: Aditya Gupta
---
Multiple alternative approaches were tried to fix this:
1. New PCR for Power11: No
2. 'Hacky fix': chose (n-1) entry in compat table in case of Power10.
Commit:
https://github.com/adi-g15-ibm/qemu/commit
Power11 core is same as Power10, reuse PNV10_PSI initialisation, by
declaring 'PNV11_PSI' as child class of 'PNV10_PSI'
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
Power11 core is same as Power10, reuse PNV10_OCC initialisation,
by declaring `PNV11_OCC` as child class of `PNV10_OCC`
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
kiboot.lid
Aditya Gupta (11):
ppc: Add Power11 DD2.0 processor
ppc/pseries: Add Power11 cpu type
target/ppc: Introduce 'PowerPCCPUClass::logical_pvr'
target/ppc: Fix regression due to Power10 and Power11 having same PCR
ppc/pnv: Add a Power11 Pnv11Chip, and a Power11 Machine
ppc/pnv:
: Nicholas Piggin
Signed-off-by: Aditya Gupta
---
docs/system/ppc/powernv.rst | 9 +--
hw/ppc/pnv.c| 120 ++--
hw/ppc/pnv_core.c | 11
include/hw/ppc/pnv.h| 5 ++
include/hw/ppc/pnv_chip.h | 7 +++
include/hw/ppc/pnv_core.h
Power11 core is same as Power10, declare PNV11_HOMER as a child
class of PNV10_HOMER, so it goes through same class init
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
Power11 core is same as Power10 core, declare PNV11_LPC as a child
class of PNV10_LPC, so it goes through same class init
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
with compat-mode.
Cc: Cédric Le Goater
Cc: Daniel Henrique Barboza
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Signed-off-by: Aditya Gupta
---
target/ppc/cpu.h | 1 +
target/ppc/cpu_init.c | 5 +
2 files changed, 6 insertions(+)
diff --git a/target/ppc/cpu.h b/target
-by: Aditya Gupta
---
target/ppc/compat.c | 7 +++
target/ppc/cpu-models.c | 3 ++
target/ppc/cpu-models.h | 3 ++
target/ppc/cpu_init.c | 102
4 files changed, 115 insertions(+)
diff --git a/target/ppc/compat.c b/target/ppc/compat.c
index
On Mon, May 27, 2024 at 05:15:05PM GMT, Cédric Le Goater wrote:
> On 5/27/24 09:10, Aditya Gupta wrote:
> > Power11 core is same as Power10, use the existing functionalities to
> > introduce a Power11 chip and machine, with Power10 chip as parent of
> > Power11 chip, thus
Power11 core is same as Power10, reuse PNV10_SBER initialisation, by
declaring PNV11_PSI as child class of PNV10_PSI
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
Power11 core is same as Power10, reuse PNV10_OCC initialisation,
by declaring `PNV11_OCC` as child class of `PNV10_OCC`
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
cc,psi,sbe
+ reduce code duplication by reusing power10 code
+ make power11 as default
+ rebase on qemu upstream/master
+ add more information in commit descriptions
+ update docs
+ update skiboot.lid
Aditya Gupta (11):
ppc: Add Power11 DD2.0 processor
ppc/pseries: Add Power1
Cc: Nicholas Piggin
Signed-off-by: Aditya Gupta
---
Multiple alternative approaches were tried to fix this:
1. New PCR for Power11: No
2. 'Hacky fix': chose (n-1) entry in compat table in case of Power10.
Commit:
https://github.com/adi-g15-ibm/qemu/commit
: Nicholas Piggin
Signed-off-by: Aditya Gupta
---
docs/system/ppc/powernv.rst | 9 +--
hw/ppc/pnv.c| 119 ++--
hw/ppc/pnv_core.c | 11
include/hw/ppc/pnv.h| 5 ++
include/hw/ppc/pnv_chip.h | 7 +++
include/hw/ppc/pnv_core.h
Power11 core is same as Power10, reuse PNV10_PSI initialisation, by
declaring 'PNV11_PSI' as child class of 'PNV10_PSI'
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
-by: Aditya Gupta
---
target/ppc/compat.c | 7 +++
target/ppc/cpu-models.c | 3 ++
target/ppc/cpu-models.h | 3 ++
target/ppc/cpu_init.c | 102
4 files changed, 115 insertions(+)
diff --git a/target/ppc/compat.c b/target/ppc/compat.c
index
with compat-mode.
Cc: Cédric Le Goater
Cc: Daniel Henrique Barboza
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Signed-off-by: Aditya Gupta
---
target/ppc/cpu.h | 1 +
target/ppc/cpu_init.c | 5 +
2 files changed, 6 insertions(+)
diff --git a/target/ppc/cpu.h b/target
Power11 core is same as Power10 core, declare PNV11_LPC as a child
class of PNV10_LPC, so it goes through same class init
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
Power11 core is same as Power10, declare PNV11_HOMER as a child
class of PNV10_HOMER, so it goes through same class init
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
-by: Aditya Gupta
---
docs/system/ppc/pseries.rst | 6 +++---
hw/ppc/spapr_cpu_core.c | 1 +
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/docs/system/ppc/pseries.rst b/docs/system/ppc/pseries.rst
index a876d897b6e4..3277564b34c2 100644
--- a/docs/system/ppc/pseries.rst
+++ b/docs
Hello Tao,
Will continue with testing unwinding with vmcores.
It works for me on both x86 and ppc64le !
Thanks,
Aditya Gupta
Thanks,
Aditya Gupta
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To unsubscribe send an email to devel-le...@lists.crash
won't be supported from this patch
till the patch renaming 'x86_64_get_cpu_reg'
Will continue with testing unwinding with vmcores.
Thanks,
Aditya Gupta
--
Crash-utility mailing list -- devel@lists.crash-utility.osci.io
To unsubscribe send an email to devel-le...@lists.crash-utility.osci.i
it before going.
Will test today and let you know.
Thanks,
Aditya Gupta
Thanks,
Tao Liu
Thanks,
Tao Liu
Thanks,
Aditya Gupta
Thanks,
Tao Liu
Thanks,
Aditya Gupta
On 28/04/24 09:32, Tao Liu wrote:
Currently for most gdb_interface call, in which a non-null file pointer
is passed, GDB's output
TTRS_UNSPECIFIED);
or
+ cpu_physical_memory_read(ADI_REGION_BASE, , 4);
1st should return your MemoryRegion, and second one should call your
.read callback.
Thanks,
Aditya Gupta
On 03/05/24 10:22, Nicholas Piggin wrote:
On Sat Apr 27, 2024 at 12:32 AM AEST, Cédric Le Goater wrote:
On 4/26/24 13:00, Aditya Gupta wrote:
Make Power11 as default cpu type for 'pseries' and 'powernv' machine type,
with Power11 being the newest supported Power processor in QEMU
: Nicholas Piggin
Cc: Paolo Bonzini
Cc: Thomas Huth
Signed-off-by: Aditya Gupta
---
hw/ppc/pnv.c| 2 +-
tests/qtest/pnv-xscom.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 6e3a5ccdec76..06a4e4d13948 100644
--- a/hw/ppc/pnv.
nks,
Aditya Gupta
Thanks,
- Aditya Gupta
C.
Hello David,
On 29/04/24 07:14, David Gibson wrote:
On Fri, Apr 26, 2024 at 04:32:18PM +0200, Cédric le Goater wrote:
On 4/26/24 13:00, Aditya Gupta wrote:
Make Power11 as default cpu type for 'pseries' and 'powernv' machine type,
with Power11 being the newest supported Power processor
"power10".
Do the Power11 and Power10 processors have the same XSCOM and MMIO
address spaces ?
Yes. Hence using the same base and sizes.
Thanks,
Aditya Gupta
Will do it.
pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id),
@@ -2116,6 +2137,35 @@ static
v3.
Skiboot reports :
[ 0.121234172,6] P11 DD1.00 detected
It is a DD2.0, with major revision = 0x2, and minor revision = 0. Might
need some change in skiboot. Will post a v3 series with changes.
Thanks,
- Aditya Gupta
C.
Hi Tao,
On 30/04/24 08:11, Tao Liu wrote:
Hi Aditya,
Sorry for the late reply.
On Sun, Apr 28, 2024 at 4:46 PM Aditya Gupta wrote:
Hi Tao,
Thanks for sending the series.
Maybe you missed CCing people ?
Yeah, I will get it fixed in v3.
Sure.
Also this patch's 'author' line is missing
patches with me in
Cc), and others in my crash-utility folder (those with Cc: crash-utility).
Thanks,
Aditya Gupta
On 28/04/24 09:32, Tao Liu wrote:
Currently for most gdb_interface call, in which a non-null file pointer
is passed, GDB's output stream is replaced with the passed file pointer
Due
e that 'chipTOD' was added in commit 9a69950feb098. I2C mentions
> > yet to merge, is it merged yet ?
>
> yes.
Thanks for confirming Cédric !
- Aditya Gupta
>
> >
> > I will check whether this needs updating, but might do it in a separate
> > patch than this series.
>
> Thanks,
>
>
On Fri, Apr 26, 2024 at 04:38:13PM +0200, Cédric Le Goater wrote:
> On 4/26/24 13:00, Aditya Gupta wrote:
> > Skiboot/OPAL patches are in discussion upstream [1], with corresponding
> > commits in github repository [2].
> >
> > Update skiboot.lid, with binary built fro
On Fri, Apr 26, 2024 at 04:32:18PM +0200, Cédric Le Goater wrote:
> On 4/26/24 13:00, Aditya Gupta wrote:
> > Make Power11 as default cpu type for 'pseries' and 'powernv' machine type,
> > with Power11 being the newest supported Power processor in QEMU.
>
> This is too e
On Fri, Apr 26, 2024 at 04:33:33PM +0200, Cédric Le Goater wrote:
> On 4/26/24 13:00, Aditya Gupta wrote:
> > Power11 core is same as Power10, reuse PNV10_SBER initialisation, by
> > declaring PNV11_PSI as child class of PNV10_PSI
> >
> > Cc: Cédric Le Goater
>
On Fri, Apr 26, 2024 at 04:33:23PM +0200, Cédric Le Goater wrote:
> On 4/26/24 13:00, Aditya Gupta wrote:
> > Power11 core is same as Power10, reuse PNV10_PSI initialisation, by
> > declaring 'PNV11_PSI' as child class of 'PNV10_PSI'
> >
> > Cc: Cédric Le Goater
>
On Fri, Apr 26, 2024 at 04:33:13PM +0200, Cédric Le Goater wrote:
> On 4/26/24 13:00, Aditya Gupta wrote:
> > Power11 core is same as Power10, reuse PNV10_OCC initialisation,
> > by declaring `PNV11_OCC` as child class of `PNV10_OCC`
>
> Reviewed-by: Cédric Le Goater
Than
On Fri, Apr 26, 2024 at 04:32:52PM +0200, Cédric Le Goater wrote:
> On 4/26/24 13:00, Aditya Gupta wrote:
> > Power11 core is same as Power10 core, declare PNV11_LPC as a child
> > class of PNV10_LPC, so it goes through same class init
> >
> > Cc: Cédric Le Goater
>
On Fri, Apr 26, 2024 at 04:32:37PM +0200, Cédric Le Goater wrote:
> On 4/26/24 13:00, Aditya Gupta wrote:
> > Power11 core is same as Power10, declare PNV11_HOMER as a child
> > class of PNV10_HOMER, so it goes through same class init
> >
> > Cc: Cédric Le Goater
>
PE(power10, "power10_v2.0"),
> > +{
> > +.parent = TYPE_PNV_CORE,
> > +.name = PNV_CORE_TYPE_NAME("power10_v2.0"),
> > +.class_init = pnv_core_power10_class_init,
> > +.class_base_init = pnv_core_power10_class_init,
>
ggested one possible way in patch #3, to replicate the
*_dt_populate and quad_realize functions for Power11 also.
Another way to do this was depending on the type string in qemu
object's class type name, or object_cast_cache, but I decided not to go
with string comparison or depending on internal strings.
Will use your suggestion in patch #3.
Thanks,
Aditya Gupta
>
> Thanks,
>
> C.
>
>
I bus.
I can see that 'chipTOD' was added in commit 9a69950feb098. I2C mentions
yet to merge, is it merged yet ?
I will check whether this needs updating, but might do it in a separate
patch than this series.
Thanks,
- Aditya Gupta
>
> > + * Interrupt Controller, XICS (POWER8)
Hello Cédric,
Thanks for your reviews.
On Fri, Apr 26, 2024 at 04:27:04PM +0200, Cédric Le Goater wrote:
> Hello Aditya
>
> On 4/26/24 13:00, Aditya Gupta wrote:
> > Add base support for "--cpu power11" in QEMU.
> >
> > Power11 core is same as P
Power11 core is same as Power10, reuse PNV10_SBER initialisation, by
declaring PNV11_PSI as child class of PNV10_PSI
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Signed-off-by: Aditya Gupta
---
hw/ppc/pnv_sbe.c | 15
Power11 core is same as Power10, reuse PNV10_PSI initialisation, by
declaring 'PNV11_PSI' as child class of 'PNV10_PSI'
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Signed-off-by: Aditya Gupta
---
hw/ppc/pnv_psi.c | 24
Power11 core is same as Power10 core, declare PNV11_LPC as a child
class of PNV10_LPC, so it goes through same class init
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Signed-off-by: Aditya Gupta
---
hw/ppc/pnv_lpc.c
+ update skiboot.lid
Aditya Gupta (10):
ppc/pseries: Add Power11 cpu type
ppc/pnv: Introduce 'PnvChipClass::chip_type'
ppc/pnv: Add a Power11 Pnv11Chip, and a Power11 Machine
ppc/pnv: Add HOMER for POWER11
ppc/pnv: Add a LPC controller for POWER11
ppc/pnv: Add OCC for Power11
ppc/pnv
Power11 core is same as Power10, declare PNV11_HOMER as a child
class of PNV10_HOMER, so it goes through same class init
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Signed-off-by: Aditya Gupta
---
hw/ppc/pnv_homer.c
Signed-off-by: Aditya Gupta
---
docs/system/ppc/pseries.rst | 6 +--
hw/ppc/spapr_cpu_core.c | 1 +
target/ppc/compat.c | 7 +++
target/ppc/cpu-models.c | 2 +
target/ppc/cpu-models.h | 2 +
target/ppc/cpu_init.c | 99 +
6 files ch
: Nicholas Piggin
Signed-off-by: Aditya Gupta
---
docs/system/ppc/powernv.rst | 9 ++--
hw/ppc/pnv.c| 98 +++--
hw/ppc/pnv_core.c | 16 +-
include/hw/ppc/pnv.h| 5 ++
include/hw/ppc/pnv_chip.h | 10
5 files changed, 130
Power11 core is same as Power10, reuse PNV10_OCC initialisation,
by declaring `PNV11_OCC` as child class of `PNV10_OCC`
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Signed-off-by: Aditya Gupta
---
hw/ppc/pnv_occ.c | 14
Srinivasan
Cc: Nicholas Piggin
Signed-off-by: Aditya Gupta
---
hw/ppc/pnv.c | 4 ++--
hw/ppc/spapr.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 06e272f3bdd3..0c5a6bc424af 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -2531,8 +2531,6
: Madhavan Srinivasan
Cc: Nicholas Piggin
Signed-off-by: Aditya Gupta
---
hw/ppc/pnv.c | 5 +
include/hw/ppc/pnv_chip.h | 10 ++
2 files changed, 15 insertions(+)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 6e3a5ccdec76..74e7908e5ffb 100644
--- a/hw/ppc/pnv.c
+++ b/hw
gave. I had recently started
contributing to open-source, and crash-utility was one of the first I
started contributing to. You have been an amazing maintainer, my
interactions as a open-source contributor started very nicely due to
maintainers like you.
Thanks again,
- Aditya Gupta
Hi all,
In Flink SQL, in UPSERT mode, I have observed that if I INSERT a new record
with a new equality field Id, then a equality delete file is also created with
the corresponding entry, for example I executed following commands in Flink SQL
with Apache Iceberg-
CREATE TABLE
Hi Tao & Alexey,
On Mon, Apr 01, 2024 at 05:14:41PM +0800, Tao Liu wrote:
> Hi Aditya & Alexey,
>
> On Mon, Apr 1, 2024 at 4:39 PM Aditya Gupta wrote:
> >
> > Hi Tao & Alexey,
> >
> > > Please have a test or review, any comments would be nice.
&
, I will add these details also.
>
> > > Also, you will need an OPAL update. The above changes are pointless
> > > without it.
> > > The minimum for now is a git commit from the opal repo, then you will
> > > need to
> > > update QEMU with a binary.
> >
> > Agreed. I will consult when we push it to public. Will update this in
> > next series.
> >
> > There might be some days delay in the next patch series.
>
> We have entered the QEMU 9.1 cycle. There is time. I will comment more
> the next respin.
Thanks Cédric
- Aditya Gupta
>
> Thanks,
>
> C.
>
update this in
next series.
There might be some days delay in the next patch series.
Thanks
>
> Thanks,
>
> C.
>
> On 4/1/24 07:55, Aditya Gupta wrote:
> > This patch series adds support for Power11 pseries and powernv machine
> > targets
> > to emulate
text (ulong task);
+
#endif /* !GDB_COMMON */
```
Since 'gdb_change_cpu_context' is no more defined in any patch, and
gdb_change_thread_context is defined in crash_target.c
Thanks
- Aditya Gupta
>
> Thanks,
> Tao Liu
>
> On Wed, Mar 27, 2024 at 4:05 AM Alexey Makhalov
> wro
Base support for "--cpu power11" in QEMU
Signed-off-by: Aditya Gupta
---
docs/system/ppc/pseries.rst | 6 +-
hw/ppc/spapr_cpu_core.c | 1 +
target/ppc/compat.c | 7 ++
target/ppc/cpu-models.c | 2 +
target/ppc/cpu-models.h | 2 +
target/ppc/cpu_init.c
Most of the base support is based on P10 PowerNV
Signed-off-by: Aditya Gupta
---
hw/ppc/pnv.c | 409 +
hw/ppc/pnv_core.c | 94 +
hw/ppc/pnv_homer.c | 64 ++
hw/ppc/pnv_lpc.c | 14 ++
hw/ppc/pnv_occ.c
-g15-ibm/qemu/tree/p11
Aditya Gupta (2):
ppc: pseries: add P11 cpu type
ppc: powernv11: add base support for P11 PowerNV
docs/system/ppc/pseries.rst | 6 +-
hw/ppc/pnv.c| 409
hw/ppc/pnv_core.c | 94 +
hw/ppc
ll of us using 'CURRENT_CONTEXT',
I guess it makes sense to rename 'machdep->get_cpu_reg' to
'machdep->get_current_reg'.
Any comments ?
- Aditya Gupta
I think you're going to do this later though, just in case.
Thanks,
Tao Liu
[1]https://github.com/crash-utility/crash/wiki#writing-p
Hi Tao,
On Wed, Mar 20, 2024 at 07:39:12PM +0800, Tao Liu wrote:
> Hi Aditya & Alexey,
>
> On Wed, Mar 20, 2024 at 1:57 PM Aditya Gupta wrote:
> >
> > Hi Tao,
> >
> > > From my view, I think we can keep the current "gdb thread/CPUs =
> > &
to fetch registers again, after architectures have set
'machdep->get_cpu_reg'.
Haven't tested this yet.
Thanks,
Aditya Gupta
>
> Do you have any thoughts?
>
> [1]: https://github.com/liutgnu/crash-dev/commits/one-thread
>
> Thanks,
> Tao Liu
>
> > Thanks,
&
On 18/03/24 14:18, HAGIO KAZUHITO(萩尾 一仁) wrote:
On 2024/03/18 17:26, Aditya Gupta wrote:
Hi,
The commit removing 'vmap_area_list' is now merged in Linux mainline tree.
commit: 55c49fee57af99f3c663e69dedc5b85e691bbe50
mm/vmalloc: remove vmap_area_list
Applied with this commit
Hi,
The commit removing 'vmap_area_list' is now merged in Linux mainline tree.
commit: 55c49fee57af99f3c663e69dedc5b85e691bbe50
mm/vmalloc: remove vmap_area_list
Any comments on this patch ?
Thanks,
Aditya Gupta
On 24/02/24 00:33, Aditya Gupta wrote:
Below error was noticed when
fail to collect vmcore:
[PATCH] makedumpfile: ppc64: get vmalloc start address from vmcoreinfo
https://lore.kernel.org/kexec/kjitig4jcelchtqria3mmr2jd3h5uptpoeyesif6crnzdtel72@jlit5ntwzdig/T/#t
Any comments ?
Thanks,
- Aditya Gupta
On 01/03/24 16:16, Sachin Sant wrote:
On 01-Mar-2024
remove 'gdb_refresh_regcache'
later, if CPU 0 isn't initialised at a time when crash has
machdep->get_cpu_reg = NULL.
Really sorry Tao, for causing the confusion here.
- Aditya Gupta
>
> After crash finished loading and we see crash> prompt, the cpu regcaches
> will be all
for
arbitrary unwinding will still work with Tao's approach.
- Aditya Gupta
On Sun, Mar 17, 2024 at 03:40:52PM +0530, Aditya Gupta wrote:
> Hi Tao and Alexey,
>
> On Fri, Mar 15, 2024 at 03:15:19PM -0700, Alexey Makhalov wrote:
> > Hi Tao,
> >
> > Thanks for the
o-one, so `set_cpu`
will then refer to the task ID, I will have to explore more on this.
Any comments ?
Thanks,
Aditya Gupta
>
> Thanks,
> --Alexey
>
>
> On Thu, Mar 14, 2024 at 9:22 PM Tao Liu wrote:
>
> > Hi Alexey,
> >
> > On Thu, Mar 14, 2024 at 6:29 PM
quot;, and no regcache refreshed when
> invoke "info threads".
If i understand clearly, "thread X" causing refresh for one thread/CPU
is expected, as we want only registers for "X" to be refreshed.
But 'info threads' not refreshing any regcache should be solved by
h shortly.
Thanks for the interest in this. Just in case, with both patch series
combined, it should be possible to backtrace and run info locals, etc,
on arbitrary tasks also. Interested in your patch though :)
Thanks,
Aditya Gupta
>
> Thanks,
> --Alexey
>
> On Wed, Mar 13, 2024 at 2:34
On 13/03/24 18:09, Luca Boccassi wrote:
On Wed, 13 Mar 2024 at 12:30, Aditya Gupta wrote:
Hello,
I tried systemd-soft-reboot on a RHEL system, and it's amazing in terms
of it's ability to do a userspace reboot, within fraction of time of a
full system reboot. For example, for a Power system
the service files, but
don't know how and if I can do a similar thing with mounts.
Thanks,
Aditya Gupta
Hi Tao,
On Wed, Mar 13, 2024 at 11:23:56AM +0800, Tao Liu wrote:
> Hi Aditya,
>
> On Tue, Mar 12, 2024 at 5:12 PM Aditya Gupta wrote:
> >
> > Hi Tao,
> >
> > > <...>
> > >
> > > +crash_target *target = NULL;
> > > +
>
On 11/03/24 10:53, Hari Bathini wrote:
On 01/03/24 12:32 pm, Aditya Gupta wrote:
Below error is noticed when running crash on vmcore collected from a
linux-next
kernel crash (linux-next tag next-20240121):
# crash /boot/vmlinuz-6.8.0-rc5-next-20240221 ./vmcore
ol ret = FALSE;
>
> - if (LIVE()) {
> - /* doesn't support reading registers in live dump */
> - return FALSE;
> - }
> -
Thanks for including this change in the series. LGTM.
Thanks,
Aditya Gupta
> /* Currently only handling registers availab
ocessor;
> +}
>
> /*
> * Collect the irq_desc[] entry along with its associated handler and
> diff --git a/task.c b/task.c
> index a405b05..ef79f53 100644
> --- a/task.c
> +++ b/task.c
> @@ -715,7 +715,8 @@ task_init(void)
>* crash_target::fetch_regis
On Tue, Mar 12, 2024 at 02:46:17PM +0800, Lianbo Jiang wrote:
> Hi, Aditya
>
> Sorry for the late reply.
>
> And thank you for improving the patchset. This looks better and test is ok
> for my side, so: Ack.
Hi Lianbo,
Thanks for the ack.
- Aditya Gupta
>
>
> T
On Tue, Mar 12, 2024 at 02:50:37PM +0800, Tao Liu wrote:
> LGTM
>
> Acked-by: Tao Liu
Hi Tao,
Thanks for the ack.
-Aditya Gupta
>
> On Mon, Mar 11, 2024 at 5:13 PM Aditya Gupta wrote:
> >
> >
> > On 11/03/24 10:53, Hari Bathini wrote:
> > >
>
On 11/03/24 10:53, Hari Bathini wrote:
On 01/03/24 12:32 pm, Aditya Gupta wrote:
Below error is noticed when running crash on vmcore collected from a
linux-next
kernel crash (linux-next tag next-20240121):
# crash /boot/vmlinuz-6.8.0-rc5-next-20240221 ./vmcore
Thanks for the Ack !
- Aditya Gupta
>
> Thanks,
> Tao Liu
>
> On Mon, Mar 4, 2024 at 5:59 PM Aditya Gupta wrote:
> >
> > The Problem:
> >
> >
> > Currently crash is unable to show function arguments and local variables, as
>
Hi Tao,
On Tue, Mar 05, 2024 at 07:39:00PM +0800, Tao Liu wrote:
> Hi Aditya,
>
> On Tue, Mar 5, 2024 at 6:30 PM Aditya Gupta wrote:
> >
> > Sorry Tao, I missed this mail earlier, as it got marked as read somehow.
> >
> > On Tue, Feb 27, 2024 at 05:37:05PM +
Sorry Tao, I missed this mail earlier, as it got marked as read somehow.
On Tue, Feb 27, 2024 at 05:37:05PM +0800, Tao Liu wrote:
> On Thu, Feb 22, 2024 at 10:52:56AM +0530, Aditya Gupta wrote:
> >
> > <...snip...>
> >
> > +static int
> > +ppc64_get_cpu_r
sh path, but if checked with
'info registers', they will have different registers.
Cc: Sourabh Jain
Cc: Hari Bathini
Cc: Mahesh J Salgaonkar
Cc: Naveen N. Rao
Cc: Lianbo Jiang
Cc: HAGIO KAZUHITO(萩尾 一仁)
Cc: Tao Liu
Signed-off-by: Aditya Gupta
---
crash_target
onkar
Cc: Naveen N. Rao
Cc: Lianbo Jiang
Cc: HAGIO KAZUHITO(萩尾 一仁)
Cc: Tao Liu
Signed-off-by: Aditya Gupta
---
gdb-10.2.patch | 53 ++
1 file changed, 53 insertions(+)
diff --git a/gdb-10.2.patch b/gdb-10.2.patch
index 677bd9b35882..1fb4212865
t replaced gdb's output stream, losing
output in some cases, such as info threads and extra output in info
variables
+ fix 'info threads'
RFC V2:
- removed patch implementing 'frame', 'up', 'down' in crash
- updated the cover letter by removing the mention of those commands other
d.
Cc: Sourabh Jain
Cc: Hari Bathini
Cc: Mahesh J Salgaonkar
Cc: Naveen N. Rao
Cc: Lianbo Jiang
Cc: HAGIO KAZUHITO(萩尾 一仁)
Cc: Tao Liu
Signed-off-by: Aditya Gupta
---
crash_target.c | 24
defs.h | 3 +++
gdb-10.2.patch | 30 ++
ke
thini
Cc: Mahesh J Salgaonkar
Cc: Naveen N. Rao
Cc: Lianbo Jiang
Cc: HAGIO KAZUHITO(萩尾 一仁)
Cc: Tao Liu
Signed-off-by: Aditya Gupta
---
gdb_interface.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gdb_interface.c b/gdb_interface.c
index b14319c66147..8f99a0d7fd
o support GDB unwinding doesn't support live debugging
Cc: Sourabh Jain
Cc: Hari Bathini
Cc: Mahesh J Salgaonkar
Cc: Naveen N. Rao
Cc: Lianbo Jiang
Cc: HAGIO KAZUHITO(萩尾 一仁)
Improved-by: Tao Liu
Signed-off-by: Aditya Gupta
---
defs.h | 123
Tao, I will post it soon today.
Thanks,
Aditya Gupta
Thanks,
Tao Liu
Thanks,
Aditya Gupta
Thanks.
Lianbo
Thanks,
Aditya Gupta
Do let me know, I will send a v10 accordingly :)
Thanks,
Aditya Gupta
Thanks.
Lianbo
On Thu, Feb 22, 2024 at 4:58 PM Tao Liu wrote:
Hi Aditya,
On Thu, Feb 22
Hi Lianbo and Tao,
On Tue, Feb 27, 2024 at 11:27:32AM +0800, lijiang wrote:
> Hi, Aditya
> On Mon, Feb 26, 2024 at 7:12 PM Aditya Gupta wrote:
> > Hi Lianbo,
> > On Thu, Feb 22, 2024 at 03:59:36PM +0530, Aditya Gupta wrote:
> > > Hi Lianbo,
> > > On Thu, Feb 2
: Sachin Sant
Signed-off-by: Aditya Gupta
---
memory.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/memory.c b/memory.c
index b84e974a3325..b3027bd101cd 100644
--- a/memory.c
+++ b/memory.c
@@ -17220,11 +17220,20 @@ first_vmalloc_address(void)
{
stati
Hi Kazu,
On Wed, Feb 28, 2024 at 12:25:04AM +, HAGIO KAZUHITO(萩尾 一仁) wrote:
> On 2024/02/23 17:39, Aditya Gupta wrote:
> > Currently makedumpfile depends on reading the 'cur_cpu_spec' kernel
> > symbol to get the current MMU type on PowerPC64.
> >
> > The disa
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