The pixel_clock_mhz property is populated in amdgpu_dm when Freesync is setup,
but it is not used anywhere in amdgpu_dm. Remove the dead code.
Cc: chiahsuan.ch...@amd.com
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ---
This reverts commit 9606c08e178f953d22e50b05c64b4b1a48051f3e.
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c| 14 ++
drivers/gpu/drm/amd/include/mes_v12_api_def.h | 3 ++-
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git
Hi Dave, Sima,
Fixes for 6.9.
The following changes since commit dd5a440a31fae6e459c0d627162825505361:
Linux 6.9-rc7 (2024-05-05 14:06:01 -0700)
are available in the Git repository at:
https://gitlab.freedesktop.org/agd5f/linux.git
tags/amd-drm-fixes-6.9-2024-05-08
for you to fetch
MST colorspace property support was disabled due to a series of warnings
that came up when the device was plugged in since the properties weren't
made at device creation. Create the properties in advance instead.
Suggested-by: Ville Syrjälä
Fixes: 69a959610229 ("drm/amd/display: Temporary
On Wed, May 8, 2024 at 4:12 PM Easwar Hariharan
wrote:
>
> On 5/8/2024 7:53 AM, Alex Deucher wrote:
> > On Tue, May 7, 2024 at 2:32 PM Easwar Hariharan
> > wrote:
> >>
> >> On 5/3/2024 11:13 AM, Easwar Hariharan wrote:
> >>> I2C v7, SMBus 3.2, and I3C 1.1.1 specifications have replaced
> >>>
This patch adds basic eviction fence framework for the gfx buffers.
The idea is to:
- One eviction fence is created per gfx process, at kms_open.
- This same fence is attached to all the gem buffers created
by this process.
This framework will be further used for usermode queues.
V2: Addressed
This patch adds support for userqueue resume. What it typically does is
this:
- adds a new delayed work for resuming all the queues.
- schedules this delayed work from the suspend work.
- validates the BOs and replaces the eviction fence before resuming all
the queues running under this instance
This patch adds suspend support for gfx userqueues. It typically does
the following:
- adds an enable_signaling function for the eviction fence, so that it
can trigger the userqueue suspend,
- adds a delayed function for suspending the userqueues, to suspend all
the queues under this userq
This patch adds userqueue suspend/resume functions at
core MES V11 IP level.
Cc: Alex Deucher
Cc: Christian Koenig
Signed-off-by: Shashank Sharma
---
.../gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c | 31 +++
.../gpu/drm/amd/include/amdgpu_userqueue.h| 5 +++
2 files
This patch series adds support for suspending and resuming the gfx
usermode queues. It also adds eviction fences which are primarily used
by usermode queues.
This patch series is dependent on basic AMDGPU usermode queue series
which is being reviewed here:
On Wed, May 08, 2024 at 02:43:07PM -0500, Mario Limonciello wrote:
> When the colorspace property is registered on MST devices there is
> no `obj_free_cb` callback for it in drm_mode_object_add().
>
> Don't show a warning trace for __drm_mode_object_add() calls for
> DRM_MODE_OBJECT_PROPERTY.
MST colorspace property support was disabled due to a series of warnings
that came up when the device was plugged in. As those warnings are fixed,
revert commit 69a959610229 ("drm/amd/display: Temporary Disable MST DP
Colorspace Property").
Reported-and-tested-by: Tyler Schneider
Closes:
When the colorspace property is registered on MST devices there is
no `obj_free_cb` callback for it in drm_mode_object_add().
Don't show a warning trace for __drm_mode_object_add() calls for
DRM_MODE_OBJECT_PROPERTY.
Reported-and-tested-by: Tyler Schneider
Closes:
This fixes HDP flushes on systems with non-4K pages.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc24.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.c
b/drivers/gpu/drm/amd/amdgpu/soc24.c
index
On 08.05.24 20:09, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
The logic assumed any migration attempt worked and therefore would over-
account the amount of data migrated during buffer re-validation. As a
consequence client can be unfairly penalised by incorrectly considering
its migration
On Wed, May 08, 2024 at 09:47:50AM -0400, Alex Deucher wrote:
> On Mon, Apr 8, 2024 at 3:06 PM Ville Syrjala
> wrote:
> >
> > From: Ville Syrjälä
> >
> > Replace the open coded drm_crtc_vblank_crtc() with the real
> > thing.
> >
> > Cc: Alex Deucher
> > Cc: "Christian König"
> > Cc: "Pan,
From: Tvrtko Ursulin
Currently the fallback placement flag can achieve a hint that buffer
should be migrated back to the non-fallback placement, however that only
works while there is no memory pressure. As soon as we reach full VRAM
utilisation, or worse overcommit, the logic is happy to leave
From: Tvrtko Ursulin
Last few days I was looking at the situation with VRAM over subscription, what
happens versus what perhaps should happen. Browsing through the driver and
running some simple experiments.
I ended up with this patch series which, as a disclaimer, may be completely
wrong but
From: Tvrtko Ursulin
The logic assumed any migration attempt worked and therefore would over-
account the amount of data migrated during buffer re-validation. As a
consequence client can be unfairly penalised by incorrectly considering
its migration budget spent.
Fix it by looking at the before
From: Tvrtko Ursulin
Currently the driver appears to be thinking that it will be attempting to
re-validate the evicted buffers on the next submission if they are not in
their preferred placement.
That however appears not to be true for the very common case of buffers
with allowed placements of
From: Tvrtko Ursulin
Current code appears to live in a misconception that playing with buffer
allowed and preferred placements can control the decision on whether
backing store migration will be attempted or not.
Both from code inspection and from empirical experiments I see that not
being
From: Tvrtko Ursulin
Now that TTM has the preferred placement flag, extend the current
workaround which assumes the GTT placement as fallback in the presence of
the additional VRAM placement.
By marking the VRAM placement as preferred we will make the buffer re-
validation phase actually
Am 08.05.24 um 15:45 schrieb Alex Deucher:
On Wed, May 8, 2024 at 9:25 AM Michel Dänzer wrote:
From: Michel Dänzer
It incorrectly claimed a resource isn't CPU visible if it's located at
the very end of CPU visible VRAM.
Fixes: a6ff969fe9 ("drm/amdgpu: fix visible VRAM handling during
From: Aric Cyr
This version brings along following fixes:
- Read default boot options
- Find max flickerless instant vtotal delta
- Refactor dcn401_update_clocks
- Reduce I2C speed to 95kHz in DCN401
- Allow higher DSC slice support for small timings on dcn401
- Don't offload flip if not only
From: Duncan Ma
[WHY]
DPIA boot option is set by VBIOS. It gets
overwritten when driver loads DMU.
[HOW]
Read PreOS boot options and determine if
dpia is enabled.
Reviewed-by: Ovidiu Bunea
Acked-by: Alex Hung
Signed-off-by: Duncan Ma
---
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c |
From: Ethan Bitnun
[WHAT & HOW]
- Populate dml 2 callback with get_max_flickerless_instant_vtotal_increase
- Use long long when necessary to prevent overflow
- Add asic specific default values, currently disabled by
default for every asic
- Use the pre-existing debug option to protect the
From: Dillon Varone
[WHY & HOW]
Refactor complex code into manageable functions. This also cleans up
some updating logics.
Reviewed-by: Alvin Lee
Acked-by: Alex Hung
Signed-off-by: Dillon Varone
---
.../amd/display/dc/clk_mgr/dcn401/dalsmc.h| 8 +-
From: Chris Park
[WHY]
HW for DCN401 is presented with a small I2C speed fluctuation that
exceeds the hard cap limitation of 100kHz occasionally. This violates
compliance requirement and will result in failure in compliance.
[HOW]
After various measurements and traceback to previous generation
From: Wenjing Liu
[WHY]
DML2.1 has added the support to determine ODM combine based on DSC slice
count limitation. This support would allow us to support DSC slice higher
than 4 on small timings. The change will allow higher DSC slice support
independent from pixel clock in use.
[HOW]
Add a
From: Alvin Lee
[WHAT & HOW]
Fast updates can consist of some stream updates as well (i.e., out_csc).
In these cases we should not offload the flip to FW as we can only
offload address only updates to FW.
Reviewed-by: Chris Park
Acked-by: Alex Hung
Signed-off-by: Alvin Lee
---
From: George Shen
[WHY]
UHBR13.5 support is optional, even if UHBR20 is supported by the device.
If source supports max UHBR13.5 while sink, cable and LTTPR support
UHBR20 but not UHBR13.5, UHBR10 should be used as the max link cap.
Reviewed-by: Wenjing Liu
Acked-by: Alex Hung
Signed-off-by:
From: Daniel Miess
[WHY & HOW]
Enable root clock optimization for SYMCLK and only
disable it when it's actively used.
Reviewed-by: Charlene Liu
Acked-by: Alex Hung
Signed-off-by: Daniel Miess
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
From: Sung Joon Kim
[WHY & HOW]
To support higher link rates that sink allows, we need to make
sure driver is ready and perform correct link-training sequence.
Reviewed-by: Wenjing Liu
Acked-by: Alex Hung
Signed-off-by: Sung Joon Kim
---
From: Wenjing Liu
[WHY]
Currently 3-tap chroma subsampling is used for YCbCr422/420. When ODM
pipesplit is used, pixels on the left edge of ODM slices need one extra
pixel from the right edge of the previous slice to calculate the correct
chroma value.
Without this change, the chroma value is
From: Wenjing Liu
[WHY]
We need an unified location to perform ODM slice rect calculation.
[HOW]
Add three interfaces for ODM slice rect/width calucaltion in resource.h
Reviewed-by: George Shen
Acked-by: Alex Hung
Signed-off-by: Wenjing Liu
---
.../gpu/drm/amd/display/dc/core/dc_resource.c
From: Samson Tam
Add VERTICAL_BLUR_SCALE & HORIZONTAL_BLUR_SCALE types.
Reviewed-by: Jun Lei
Acked-by: Alex Hung
Signed-off-by: Samson Tam
---
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
From: Revalla Hari Krishna
[WHY]
Clean up the code that requires dccg to be in its own component.
[HOW]
Move all files under newly created dccg dir and fix the makefiles.
Acked-by: Alex Hung
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Revalla Hari Krishna
---
From: Adam Nelson
[WHY]
After a non-3dlut test the MPCC_MCM_3DLUT_MODE::MPCC_MCM_3DLUT_SIZE is
incorrect.
[HOW]
Add register write to make valid.
Acked-by: Alex Hung
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Adam Nelson
---
drivers/gpu/drm/amd/display/dc/dcn401/dcn401_mpc.c| 8
From: Ilya Bakoulin
DP_DSC_CNTL no longer exists on DCN401.
Acked-by: Alex Hung
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Ilya Bakoulin
---
.../dc/dcn401/dcn401_dio_stream_encoder.c | 20 +++
1 file changed, 3 insertions(+), 17 deletions(-)
diff --git
From: Rodrigo Siqueira
The CONNECTOR_ID_USBC check was removed to fix a regression, but it was
re-introduced by accident. This commit drops the USBC that causes the
regressions.
Acked-by: Alex Hung
Signed-off-by: Rodrigo Siqueira
---
From: Rodrigo Siqueira
Cleanup unused code in DC.
Acked-by: Alex Hung
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 9 -
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 3 ---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h | 4
3
From: Joshua Aberback
[WHY]
If there are no DC clock limits present, or if the DC limits are the same
as the AC limits, we can disable the AC/DC codepath as there won't be any
validation differences between the two modes.
[HOW]
When all DC power mode clock limits are the same as the max clock
From: Dillon Varone
Create dcn401 specific structure to encapsulate version specific
variables.
Acked-by: Alex Hung
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Dillon Varone
---
.../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 3 +--
.../dc/clk_mgr/dcn401/dcn401_clk_mgr.c| 23
This DC patchset brings improvements in multiple areas. In summary, we have:
* Fixes on DCN401, 3dlut and I2C
* Improvements on AC/DC, link rates, DSC and ODM slice rect and pipe
* Refactoring on code styles and unused code
Cc: Daniel Wheeler
Adam Nelson (1):
drm/amd/display: Fix 3dlut size
On Tue, May 7, 2024 at 2:32 PM Easwar Hariharan
wrote:
>
> On 5/3/2024 11:13 AM, Easwar Hariharan wrote:
> > I2C v7, SMBus 3.2, and I3C 1.1.1 specifications have replaced "master/slave"
> > with more appropriate terms. Inspired by and following on to Wolfram's
> > series to fix drivers/i2c/[1],
Enable ISP for ISP V4.1.0 and V4.1.1 in amdgpu_discovery.
Signed-off-by: Pratap Nirujogi
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 22 +++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
Add the isp driver in amdgpu to support ISP device on the APUs that
supports ISP IP block. ISP hw block is used for camera front-end, pre
and post processing operations.
Signed-off-by: Pratap Nirujogi
---
drivers/gpu/drm/amd/amdgpu/Makefile | 3 +
drivers/gpu/drm/amd/amdgpu/amdgpu.h
ISP hw block is supported in some of the AMD GPU versions, add support
to discover ISP IP in amdgpu_discovery.
Signed-off-by: Pratap Nirujogi
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
drivers/gpu/drm/amd/include/amd_shared.h
On Mon, Apr 8, 2024 at 3:06 PM Ville Syrjala
wrote:
>
> From: Ville Syrjälä
>
> Replace the open coded drm_crtc_vblank_crtc() with the real
> thing.
>
> Cc: Alex Deucher
> Cc: "Christian König"
> Cc: "Pan, Xinhui"
> Cc: amd-gfx@lists.freedesktop.org
> Signed-off-by: Ville Syrjälä
On Wed, May 8, 2024 at 9:25 AM Michel Dänzer wrote:
>
> From: Michel Dänzer
>
> It incorrectly claimed a resource isn't CPU visible if it's located at
> the very end of CPU visible VRAM.
>
> Fixes: a6ff969fe9 ("drm/amdgpu: fix visible VRAM handling during faults")
> Reported-and-Tested-by:
From: Michel Dänzer
It incorrectly claimed a resource isn't CPU visible if it's located at
the very end of CPU visible VRAM.
Fixes: a6ff969fe9 ("drm/amdgpu: fix visible VRAM handling during faults")
Reported-and-Tested-by: Jeremy Day
Signed-off-by: Michel Dänzer
---
On Tue, May 7, 2024 at 2:04 PM Thomas Zimmermann wrote:
>
> Implement struct drm_client_funcs with the respective helpers and
> remove the custom code from the emulation. The generic helpers are
> equivalent in functionality.
>
> Signed-off-by: Thomas Zimmermann
Acked-by: Patrik Jakobsson
>
On 5/7/2024 10:14 PM, Srinivasan Shanmugam wrote:
> This commit fixes potential truncation when writing the string _imu.bin
> into the fw_name buffer in the imu_v12_0_init_microcode function in the
> imu_v12_0.c file
>
> The ucode_prefix size was reduced from 30 to 15 to ensure the snprintf
>
On 5/7/2024 10:14 PM, Srinivasan Shanmugam wrote:
> This commit addresses multiple warnings in the gfx_v12_0_init_microcode
> function in the gfx_v12_0.c file. The warnings were related to potential
> truncation when writing the strings _pfp.bin, _me.bin, _rlc.bin, and
> _mec.bin into the
Am 08.05.24 um 12:17 schrieb Michel Dänzer:
On 2024-05-07 18:39, Jeremy Day wrote:
This is just to report that I've had usually well-behaved applications
sometimes having problems with memory access violations since kernel
version 6.9-rc5. This past weekend I stumbled across a way to reliably
On 2024-05-07 18:39, Jeremy Day wrote:
> This is just to report that I've had usually well-behaved applications
> sometimes having problems with memory access violations since kernel
> version 6.9-rc5. This past weekend I stumbled across a way to reliably
> reproduce the problem in the form of a
On Mon, 08 Apr 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Replace the open coded drm_crtc_vblank_crtc() with the real
> thing.
>
> Cc: Alex Deucher
> Cc: "Christian König"
> Cc: "Pan, Xinhui"
> Cc: amd-gfx@lists.freedesktop.org
> Signed-off-by: Ville Syrjälä
FWIW,
Reviewed-by:
On Wed, May 08, 2024 at 12:27:20PM +0530, Arunpravin Paneer Selvam wrote:
> Problem statement: During the system boot time, an application request
> for the bulk volume of cleared range bias memory when the clear_avail
> is zero, we dont fallback into normal allocation method as we had an
>
On 5/3/2024 11:13 AM, Easwar Hariharan wrote:
> I2C v7, SMBus 3.2, and I3C 1.1.1 specifications have replaced "master/slave"
> with more appropriate terms. Inspired by and following on to Wolfram's
> series to fix drivers/i2c/[1], fix the terminology for users of
> I2C_ALGOBIT bitbanging
The panel_power_savings sysfs entry sets the Adaptive Backlight
Management level (abm_level). OLED displays work without backlight, so
it is unnecessary for them.
Before creating the sysfs entry, make sure the display is not an OLED
display.
Signed-off-by: Gergo Koteles
---
On 03/05/2024 15:28, Alex Deucher wrote:
On Fri, May 3, 2024 at 7:50 AM Tvrtko Ursulin wrote:
On 02/05/2024 16:00, Alex Deucher wrote:
On Thu, May 2, 2024 at 10:43 AM Tvrtko Ursulin
wrote:
On 02/05/2024 14:07, Christian König wrote:
Am 01.05.24 um 15:27 schrieb Tvrtko Ursulin:
Hi
This is just to report that I've had usually well-behaved applications
sometimes having problems with memory access violations since kernel
version 6.9-rc5. This past weekend I stumbled across a way to reliably
reproduce the problem in the form of a Skyrim save file which causes a
crash shortly
Problem statement: During the system boot time, an application request
for the bulk volume of cleared range bias memory when the clear_avail
is zero, we dont fallback into normal allocation method as we had an
unnecessary clear_avail check which prevents the fallback method leads
to fb allocation
Hi
Am 07.05.24 um 23:03 schrieb Felix Kuehling:
On 2024-05-07 07:58, Thomas Zimmermann wrote:
Implement struct drm_client_funcs with the respective helpers and
remove the custom code from the emulation. The generic helpers are
equivalent in functionality.
Signed-off-by: Thomas Zimmermann
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