Re: [casper] PYNQ+Vivado 2019.2+RFDC Block

hi jeb, regarding your ZCU111 RFDC question: here's some info that might be helpful from wei liu, cc'ed on this. btw, wei liu recently made casper yellow blocks for the ZCU111 ADC's. he's now working on ZCU111 yellow blocks for 1, 10, and 100 Gbit ethernet. from Wei Liu:

Re: [casper] PYNQ+Vivado 2019.2+RFDC Block

Hi Lewis, While that does get rid of the sysref KeyError, executing overlay.usp_rf_data_converter_0 now locks up the whole board and I’m forced to power cycle. The contents of ol.ip_dict['usp_rf_data_converter_0’] are (excluding the parameters): {'addr_range': 262144, 'device': ,

Re: [casper] PYNQ+Vivado 2019.2+RFDC Block

Hi Jeb, A workaround you can do is to edit the file "/usr/local/lib/python3.6/dist-packages/xrfdc/config.py" on the board. Comment out lines 46,47,60,90,91. These relate to: _DAC_DDP: FifoEnable, AdderEnable _ADC_DDP: FifoEnable Config: MasterADCTile, MasterDACTile Hopefully that works for

[casper] PYNQ+Vivado 2019.2+RFDC Block

Hi Folks, Has anyone here had any success configuring the RFDC block from python using pynq with a bitstream built in Vivado 2019.2? I’m working with the 2.5 ZCU111 SD image with pynq updated to 2.5.4. By using ignore_version=True with loading the overlay I can get the xrfdc driver