Re: [casper] ERROR:Xflow - map: application received signal 9
Hi, Sorry for the spam but here's a small update. I just restarted the (virtual) machine and tried casper_xps again, and the same error occurred at a later stage. I have successfully compiled non-trivial designs on this same machine/setting/versions before, but this one is by far the most intense (should take up roughly 50% of the FPGA resource). Here's the new error message: Writing file system_map.ngm... Running directed packing... Running delay-based LUT packing... Updating timing models... INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report (.mrp). Running timing-driven placement... Total REAL time at the beginning of Placer: 8 mins 6 secs Total CPU time at the beginning of Placer: 8 mins 3 secs Phase 1.1 Initial Placement Analysis Phase 1.1 Initial Placement Analysis (Checksum:86815621) REAL time: 8 mins 59 secs Phase 2.7 Design Feasibility Check Phase 2.7 Design Feasibility Check (Checksum:86815621) REAL time: 9 mins 14 secs Phase 3.31 Local Placement Optimization Phase 3.31 Local Placement Optimization (Checksum:44c9354) REAL time: 9 mins 14 secs Phase 4.37 Local Placement Optimization Phase 4.37 Local Placement Optimization (Checksum:44c9354) REAL time: 9 mins 14 secs Phase 5.2 Initial Placement for Architecture Specific Features ERROR:Xflow - map: application received signal 9 ERROR:Xflow:42 - Aborting flow execution... gmake: *** [__xps/system_routed] Error 1 ERROR:EDK - Error while running gmake -f system.make bits. Error using gen_xps_files (line 640) XPS failed. Thank you so much for any inputs! Jeff From: casper-boun...@lists.berkeley.edu [casper-boun...@lists.berkeley.edu] on behalf of Haoxuan Zheng [jef...@mit.edu] Sent: Sunday, March 31, 2013 11:45 PM To: casper@lists.berkeley.edu; Jonathan L Losh; sanchez.nev...@gmail.com Subject: [casper] ERROR:Xflow - map: application received signal 9 Hi Casper, I have been getting the following error when running casper_xps compilation (see bold part towards the end). I am running Xilinx ISE 14.2 on Matlab 2012a on Ubuntu 11.10. Any thoughts or suggestions would be greatly appreciated! #--# # Starting program map # map -timing -detail -ol high -xe n -register_duplication -o system_map.ncd -w -pr b system.ngd system.pcf #--# Release 14.2 - Map P.28xd (lin64) Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. PMSPEC -- Overriding Xilinx file /media/80Gb/Programs/Xilinx/14.2/ISE_DS/EDK/data/Xdh_PrimTypeLib.xda with local file /media/80Gb/Programs/Xilinx/14.2/ISE_DS/ISE/data/Xdh_PrimTypeLib.xda Using target part 6vsx475tff1759-1. Mapping design into LUTs... WARNING:MapLib:701 - Signal qdr1_cq_n connected to top level port qdr1_cq_n has been removed. **similar warning skipped here** WARNING:MapLib:701 - Signal qdr1_bw_n3 connected to top level port qdr1_bw_n3 has been removed. **similar warning skipped here** WARNING:MapLib:701 - Signal aux_clk_n connected to top level port aux_clk_n has been removed. WARNING:MapLib:701 - Signal aux_clk_p connected to top level port aux_clk_p has been removed. Writing file system_map.ngm... Running directed packing... Running delay-based LUT packing... Updating timing models... ERROR:Xflow - map: application received signal 9 ERROR:Xflow:42 - Aborting flow execution... gmake: *** [__xps/system_routed] Error 1 ERROR:EDK - Error while running gmake -f system.make bits. Error using gen_xps_files (line 640) XPS failed. Thank you so much! Jeff
Re: [casper] ERROR:Xflow - map: application received signal 9
Sig 9 can be caused by not enough memory - Have you watched memory usage during mapping? On Sun, Mar 31, 2013 at 11:32 PM, Haoxuan Zheng jef...@mit.edu wrote: Hi, Sorry for the spam but here's a small update. I just restarted the (virtual) machine and tried casper_xps again, and the same error occurred at a later stage. I have successfully compiled non-trivial designs on this same machine/setting/versions before, but this one is by far the most intense (should take up roughly 50% of the FPGA resource). Here's the new error message: Writing file system_map.ngm... Running directed packing... Running delay-based LUT packing... *Updating timing models...* INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report (.mrp). Running timing-driven placement... Total REAL time at the beginning of Placer: 8 mins 6 secs Total CPU time at the beginning of Placer: 8 mins 3 secs Phase 1.1 Initial Placement Analysis Phase 1.1 Initial Placement Analysis (Checksum:86815621) REAL time: 8 mins 59 secs Phase 2.7 Design Feasibility Check Phase 2.7 Design Feasibility Check (Checksum:86815621) REAL time: 9 mins 14 secs Phase 3.31 Local Placement Optimization Phase 3.31 Local Placement Optimization (Checksum:44c9354) REAL time: 9 mins 14 secs Phase 4.37 Local Placement Optimization Phase 4.37 Local Placement Optimization (Checksum:44c9354) REAL time: 9 mins 14 secs Phase 5.2 Initial Placement for Architecture Specific Features *ERROR:Xflow - map: application received signal 9* *ERROR:Xflow:42 - Aborting flow execution... * *gmake: *** [__xps/system_routed] Error 1* *ERROR:EDK - * * Error while running gmake -f system.make bits.* *Error using gen_xps_files (line 640)* *XPS failed.* * * Thank you so much for any inputs! Jeff -- *From:* casper-boun...@lists.berkeley.edu [ casper-boun...@lists.berkeley.edu] on behalf of Haoxuan Zheng [ jef...@mit.edu] *Sent:* Sunday, March 31, 2013 11:45 PM *To:* casper@lists.berkeley.edu; Jonathan L Losh; sanchez.nev...@gmail.com *Subject:* [casper] ERROR:Xflow - map: application received signal 9 Hi Casper, I have been getting the following error when running casper_xps compilation (see bold part towards the end). I am running Xilinx ISE 14.2 on Matlab 2012a on Ubuntu 11.10. Any thoughts or suggestions would be greatly appreciated! #--# # Starting program map # map -timing -detail -ol high -xe n -register_duplication -o system_map.ncd -w -pr b system.ngd system.pcf #--# Release 14.2 - Map P.28xd (lin64) Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. PMSPEC -- Overriding Xilinx file /media/80Gb/Programs/Xilinx/14.2/ISE_DS/EDK/data/Xdh_PrimTypeLib.xda with local file /media/80Gb/Programs/Xilinx/14.2/ISE_DS/ISE/data/Xdh_PrimTypeLib.xda Using target part 6vsx475tff1759-1. Mapping design into LUTs... WARNING:MapLib:701 - Signal qdr1_cq_n connected to top level port qdr1_cq_n has been removed. **similar warning skipped here** WARNING:MapLib:701 - Signal qdr1_bw_n3 connected to top level port qdr1_bw_n3 has been removed. **similar warning skipped here** WARNING:MapLib:701 - Signal aux_clk_n connected to top level port aux_clk_n has been removed. WARNING:MapLib:701 - Signal aux_clk_p connected to top level port aux_clk_p has been removed. Writing file system_map.ngm... Running directed packing... Running delay-based LUT packing... *Updating timing models...* *ERROR:Xflow - map: application received signal 9* *ERROR:Xflow:42 - Aborting flow execution... * *gmake: *** [__xps/system_routed] Error 1* *ERROR:EDK - * * Error while running gmake -f system.make bits.* *Error using gen_xps_files (line 640)* *XPS failed.* Thank you so much! Jeff -- Ross Williamson Research Scientist - Sub-mm Group California Institute of Technology 626-395-2647 (office) 312-504-3051 (Cell)
Re: [casper] ERROR:Xflow - map: application received signal 9
Hi Ross, Thank you very much! It was indeed a memory issue. I had 4GB of memory allocated, and after I expanded it to 6GB it finished without the error (although it failed timing constraints, as usual), and during mapping it stably occupied 5GB of memory for about 7 hours. Thanks again! Jeff From: Ross Williamson [rwilliam...@astro.caltech.edu] Sent: Monday, April 01, 2013 3:28 AM To: Haoxuan Zheng Cc: casper@lists.berkeley.edu; Jonathan L Losh; sanchez.nev...@gmail.com Subject: Re: [casper] ERROR:Xflow - map: application received signal 9 Sig 9 can be caused by not enough memory - Have you watched memory usage during mapping? On Sun, Mar 31, 2013 at 11:32 PM, Haoxuan Zheng jef...@mit.edumailto:jef...@mit.edu wrote: Hi, Sorry for the spam but here's a small update. I just restarted the (virtual) machine and tried casper_xps again, and the same error occurred at a later stage. I have successfully compiled non-trivial designs on this same machine/setting/versions before, but this one is by far the most intense (should take up roughly 50% of the FPGA resource). Here's the new error message: Writing file system_map.ngm... Running directed packing... Running delay-based LUT packing... Updating timing models... INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report (.mrp). Running timing-driven placement... Total REAL time at the beginning of Placer: 8 mins 6 secs Total CPU time at the beginning of Placer: 8 mins 3 secs Phase 1.1 Initial Placement Analysis Phase 1.1 Initial Placement Analysis (Checksum:86815621) REAL time: 8 mins 59 secs Phase 2.7 Design Feasibility Check Phase 2.7 Design Feasibility Check (Checksum:86815621) REAL time: 9 mins 14 secs Phase 3.31 Local Placement Optimization Phase 3.31 Local Placement Optimization (Checksum:44c9354) REAL time: 9 mins 14 secs Phase 4.37 Local Placement Optimization Phase 4.37 Local Placement Optimization (Checksum:44c9354) REAL time: 9 mins 14 secs Phase 5.2 Initial Placement for Architecture Specific Features ERROR:Xflow - map: application received signal 9 ERROR:Xflow:42 - Aborting flow execution... gmake: *** [__xps/system_routed] Error 1 ERROR:EDK - Error while running gmake -f system.make bits. Error using gen_xps_files (line 640) XPS failed. Thank you so much for any inputs! Jeff From: casper-boun...@lists.berkeley.edumailto:casper-boun...@lists.berkeley.edu [casper-boun...@lists.berkeley.edumailto:casper-boun...@lists.berkeley.edu] on behalf of Haoxuan Zheng [jef...@mit.edumailto:jef...@mit.edu] Sent: Sunday, March 31, 2013 11:45 PM To: casper@lists.berkeley.edumailto:casper@lists.berkeley.edu; Jonathan L Losh; sanchez.nev...@gmail.commailto:sanchez.nev...@gmail.com Subject: [casper] ERROR:Xflow - map: application received signal 9 Hi Casper, I have been getting the following error when running casper_xps compilation (see bold part towards the end). I am running Xilinx ISE 14.2 on Matlab 2012a on Ubuntu 11.10. Any thoughts or suggestions would be greatly appreciated! #--# # Starting program map # map -timing -detail -ol high -xe n -register_duplication -o system_map.ncd -w -pr b system.ngd system.pcf #--# Release 14.2 - Map P.28xd (lin64) Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. PMSPEC -- Overriding Xilinx file /media/80Gb/Programs/Xilinx/14.2/ISE_DS/EDK/data/Xdh_PrimTypeLib.xda with local file /media/80Gb/Programs/Xilinx/14.2/ISE_DS/ISE/data/Xdh_PrimTypeLib.xda Using target part 6vsx475tff1759-1. Mapping design into LUTs... WARNING:MapLib:701 - Signal qdr1_cq_n connected to top level port qdr1_cq_n has been removed. **similar warning skipped here** WARNING:MapLib:701 - Signal qdr1_bw_n3 connected to top level port qdr1_bw_n3 has been removed. **similar warning skipped here** WARNING:MapLib:701 - Signal aux_clk_n connected to top level port aux_clk_n has been removed. WARNING:MapLib:701 - Signal aux_clk_p connected to top level port aux_clk_p has been removed. Writing file system_map.ngm... Running directed packing... Running delay-based LUT packing... Updating timing models... ERROR:Xflow - map: application received signal 9 ERROR:Xflow:42 - Aborting flow execution... gmake: *** [__xps/system_routed] Error 1 ERROR:EDK - Error while running gmake -f system.make bits. Error using gen_xps_files (line 640) XPS failed. Thank you so much! Jeff -- Ross Williamson Research Scientist - Sub-mm Group California Institute of Technology 626-395-2647 (office) 312-504-3051 (Cell)
[casper] ERROR:Xflow - map: application received signal 9
Hi Casper, I have been getting the following error when running casper_xps compilation (see bold part towards the end). I am running Xilinx ISE 14.2 on Matlab 2012a on Ubuntu 11.10. Any thoughts or suggestions would be greatly appreciated! #--# # Starting program map # map -timing -detail -ol high -xe n -register_duplication -o system_map.ncd -w -pr b system.ngd system.pcf #--# Release 14.2 - Map P.28xd (lin64) Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. PMSPEC -- Overriding Xilinx file /media/80Gb/Programs/Xilinx/14.2/ISE_DS/EDK/data/Xdh_PrimTypeLib.xda with local file /media/80Gb/Programs/Xilinx/14.2/ISE_DS/ISE/data/Xdh_PrimTypeLib.xda Using target part 6vsx475tff1759-1. Mapping design into LUTs... WARNING:MapLib:701 - Signal qdr1_cq_n connected to top level port qdr1_cq_n has been removed. **similar warning skipped here** WARNING:MapLib:701 - Signal qdr1_bw_n3 connected to top level port qdr1_bw_n3 has been removed. **similar warning skipped here** WARNING:MapLib:701 - Signal aux_clk_n connected to top level port aux_clk_n has been removed. WARNING:MapLib:701 - Signal aux_clk_p connected to top level port aux_clk_p has been removed. Writing file system_map.ngm... Running directed packing... Running delay-based LUT packing... Updating timing models... ERROR:Xflow - map: application received signal 9 ERROR:Xflow:42 - Aborting flow execution... gmake: *** [__xps/system_routed] Error 1 ERROR:EDK - Error while running gmake -f system.make bits. Error using gen_xps_files (line 640) XPS failed. Thank you so much! Jeff
[casper] ERROR:Xflow - map: application received signal 9
hi all, I am trying to compile the correlator of tutorial 4 but i changed the adc to the acd083000x1. I have an error in the Starting program map. i went to gen_xps_files (line 636) and there is an error with the system(['xps -nw -scr run_xps.tcl system.xmp']) command. I do not know what this command do, any ideas? this is the matlab log #--# # Starting program map # map -timing -detail -ol high -xe n -register_duplication -o system_map.ncd -w -pr b system.ngd system.pcf #--# Release 14.2 - Map P.28xd (lin64) Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. PMSPEC -- Overriding Xilinx file /home/arturo/xilinx/14.2/ISE_DS/EDK/data/Xdh_PrimTypeLib.xda with local file /home/arturo/xilinx/14.2/ISE_DS/ISE/data/Xdh_PrimTypeLib.xda Using target part 5vsx95tff1136-1. Mapping design into LUTs... WARNING:MapLib:701 - Signal epb_addr_gp5 connected to top level port epb_addr_gp5 has been removed. WARNING:MapLib:701 - Signal epb_addr_gp4 connected to top level port epb_addr_gp4 has been removed. WARNING:MapLib:701 - Signal epb_addr_gp3 connected to top level port epb_addr_gp3 has been removed. WARNING:MapLib:701 - Signal aux0_clk_n connected to top level port aux0_clk_n has been removed. WARNING:MapLib:701 - Signal aux0_clk_p connected to top level port aux0_clk_p has been removed. WARNING:MapLib:701 - Signal aux1_clk_n connected to top level port aux1_clk_n has been removed. WARNING:MapLib:701 - Signal aux1_clk_p connected to top level port aux1_clk_p has been removed. WARNING:MapLib:41 - All members of TNM group infrastructure_inst_infrastructure_inst_sys_clk2x_int have been optimized out of the design. WARNING:MapLib:50 - The period specification TS_infrastructure_inst_infrastructure_inst_sys_clk2x_int has been discarded because the group infrastructure_inst_infrastructure_inst_sys_clk2x_int has been optimized away. *ERROR:Xflow - map: application received signal 9 ERROR:Xflow:42 - Aborting flow execution... * gmake: *** [__xps/system_routed] Error 1 ERROR:EDK - Error while running gmake -f system.make bits. Error using gen_xps_files (line 636) XPS failed. -- Atte. Arturo
Re: [casper] ERROR:Xflow - map: application received signal 9
Hi. Not sure of your error, but signal 9 is a sigkill by the system. Did someone kill your process or did you run completely out of memory? Running out of memory is a common cause of a spontaneous signal 9. John hi all, I am trying to compile the correlator of tutorial 4 but i changed the adc to the acd083000x1. I have an error in the Starting program map. i went to gen_xps_files (line 636) and there is an error with the system(['xps -nw -scr run_xps.tcl system.xmp']) command. I do not know what this command do, any ideas? this is the matlab log #--# # Starting program map # map -timing -detail -ol high -xe n -register_duplication -o system_map.ncd -w -pr b system.ngd system.pcf #--# Release 14.2 - Map P.28xd (lin64) Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. PMSPEC -- Overriding Xilinx file /home/arturo/xilinx/14.2/ISE_DS/EDK/data/Xdh_PrimTypeLib.xda with local file /home/arturo/xilinx/14.2/ISE_DS/ISE/data/Xdh_PrimTypeLib.xda Using target part 5vsx95tff1136-1. Mapping design into LUTs... WARNING:MapLib:701 - Signal epb_addr_gp5 connected to top level port epb_addr_gp5 has been removed. WARNING:MapLib:701 - Signal epb_addr_gp4 connected to top level port epb_addr_gp4 has been removed. WARNING:MapLib:701 - Signal epb_addr_gp3 connected to top level port epb_addr_gp3 has been removed. WARNING:MapLib:701 - Signal aux0_clk_n connected to top level port aux0_clk_n has been removed. WARNING:MapLib:701 - Signal aux0_clk_p connected to top level port aux0_clk_p has been removed. WARNING:MapLib:701 - Signal aux1_clk_n connected to top level port aux1_clk_n has been removed. WARNING:MapLib:701 - Signal aux1_clk_p connected to top level port aux1_clk_p has been removed. WARNING:MapLib:41 - All members of TNM group infrastructure_inst_infrastructure_inst_sys_clk2x_int have been optimized out of the design. WARNING:MapLib:50 - The period specification TS_infrastructure_inst_infrastructure_inst_sys_clk2x_int has been discarded because the group infrastructure_inst_infrastructure_inst_sys_clk2x_int has been optimized away. *ERROR:Xflow - map: application received signal 9 ERROR:Xflow:42 - Aborting flow execution... * gmake: *** [__xps/system_routed] Error 1 ERROR:EDK - Error while running gmake -f system.make bits. Error using gen_xps_files (line 636) XPS failed. -- Atte. Arturo
Re: [casper] ERROR:Xflow - map: application received signal 9
Hi, Now you mention is probably that i ran out of memory. I am going to check out. 2013/2/13 John Ford jf...@nrao.edu Hi. Not sure of your error, but signal 9 is a sigkill by the system. Did someone kill your process or did you run completely out of memory? Running out of memory is a common cause of a spontaneous signal 9. John hi all, I am trying to compile the correlator of tutorial 4 but i changed the adc to the acd083000x1. I have an error in the Starting program map. i went to gen_xps_files (line 636) and there is an error with the system(['xps -nw -scr run_xps.tcl system.xmp']) command. I do not know what this command do, any ideas? this is the matlab log #--# # Starting program map # map -timing -detail -ol high -xe n -register_duplication -o system_map.ncd -w -pr b system.ngd system.pcf #--# Release 14.2 - Map P.28xd (lin64) Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. PMSPEC -- Overriding Xilinx file /home/arturo/xilinx/14.2/ISE_DS/EDK/data/Xdh_PrimTypeLib.xda with local file /home/arturo/xilinx/14.2/ISE_DS/ISE/data/Xdh_PrimTypeLib.xda Using target part 5vsx95tff1136-1. Mapping design into LUTs... WARNING:MapLib:701 - Signal epb_addr_gp5 connected to top level port epb_addr_gp5 has been removed. WARNING:MapLib:701 - Signal epb_addr_gp4 connected to top level port epb_addr_gp4 has been removed. WARNING:MapLib:701 - Signal epb_addr_gp3 connected to top level port epb_addr_gp3 has been removed. WARNING:MapLib:701 - Signal aux0_clk_n connected to top level port aux0_clk_n has been removed. WARNING:MapLib:701 - Signal aux0_clk_p connected to top level port aux0_clk_p has been removed. WARNING:MapLib:701 - Signal aux1_clk_n connected to top level port aux1_clk_n has been removed. WARNING:MapLib:701 - Signal aux1_clk_p connected to top level port aux1_clk_p has been removed. WARNING:MapLib:41 - All members of TNM group infrastructure_inst_infrastructure_inst_sys_clk2x_int have been optimized out of the design. WARNING:MapLib:50 - The period specification TS_infrastructure_inst_infrastructure_inst_sys_clk2x_int has been discarded because the group infrastructure_inst_infrastructure_inst_sys_clk2x_int has been optimized away. *ERROR:Xflow - map: application received signal 9 ERROR:Xflow:42 - Aborting flow execution... * gmake: *** [__xps/system_routed] Error 1 ERROR:EDK - Error while running gmake -f system.make bits. Error using gen_xps_files (line 636) XPS failed. -- Atte. Arturo -- Atte. Arturo
