[clang] [llvm] [RISCV] Add processor definition and scheduling model for XiangShan-KunMingHu (PR #90392)

=?utf-8?b?6YOd5bq36L6+?= Message-ID: In-Reply-To: https://github.com/camel-cdr edited https://github.com/llvm/llvm-project/pull/90392 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add processor definition and scheduling model for XiangShan-KunMingHu (PR #90392)

=?utf-8?b?6YOd5bq36L6+?= Message-ID: In-Reply-To: @@ -0,0 +1,1489 @@ +//==- RISCVSchedXiangShanKunMingHu.td - XiangShanKunMingHu Scheduling Defs -*- tablegen -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See

[clang] [llvm] [RISCV] Add processor definition and scheduling model for XiangShan-KunMingHu (PR #90392)

=?utf-8?b?6YOd5bq36L6+?= Message-ID: In-Reply-To: camel-cdr wrote: The execution unit layout does not match the current XiangShan master. Has the final execution unit layout been decided on? [earlier

[clang] [llvm] [RISCV] Add processor definition for XiangShan-KunMingHu (PR #89359)

camel-cdr wrote: Has the target architecture been finalized? (As in what it should be, not necessarily the rtl) Just yesterday, there was a significant change in vector execution units: