[clang] [llvm] [RISCV] Add processor definition and scheduling model for XiangShan-KunMingHu (PR #90392)

=?utf-8?b?6YOd5bq36L6+?= Message-ID: In-Reply-To: https://github.com/camel-cdr edited https://github.com/llvm/llvm-project/pull/90392 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add processor definition and scheduling model for XiangShan-KunMingHu (PR #90392)

=?utf-8?b?6YOd5bq36L6+?= Message-ID: In-Reply-To: @@ -0,0 +1,1489 @@ +//==- RISCVSchedXiangShanKunMingHu.td - XiangShanKunMingHu Scheduling Defs -*- tablegen -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See

[clang] [llvm] [RISCV] Add processor definition and scheduling model for XiangShan-KunMingHu (PR #90392)

=?utf-8?b?6YOd5bq36L6+?= Message-ID: In-Reply-To: wangpc-pp wrote: I'd like to see the support of KunMingHu, but please hold this PR and wait for the finalization of KunMingHu's architecture. https://github.com/llvm/llvm-project/pull/90392 ___

[clang] [llvm] [RISCV] Add processor definition and scheduling model for XiangShan-KunMingHu (PR #90392)

=?utf-8?b?6YOd5bq36L6+?= Message-ID: In-Reply-To: camel-cdr wrote: The execution unit layout does not match the current XiangShan master. Has the final execution unit layout been decided on? [earlier

[clang] [llvm] [RISCV] Add processor definition and scheduling model for XiangShan-KunMingHu (PR #90392)

=?utf-8?b?6YOd5bq36L6+?= Message-ID: In-Reply-To: @@ -0,0 +1,1489 @@ +//==- RISCVSchedXiangShanKunMingHu.td - XiangShanKunMingHu Scheduling Defs -*- tablegen -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See

[clang] [llvm] [RISCV] Add processor definition and scheduling model for XiangShan-KunMingHu (PR #90392)

=?utf-8?b?6YOd5bq36L6+?= Message-ID: In-Reply-To: @@ -0,0 +1,1489 @@ +//==- RISCVSchedXiangShanKunMingHu.td - XiangShanKunMingHu Scheduling Defs -*- tablegen -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See

[clang] [llvm] [RISCV] Add processor definition and scheduling model for XiangShan-KunMingHu (PR #90392)

=?utf-8?b?6YOd5bq36L6+?= Message-ID: In-Reply-To: @@ -0,0 +1,1489 @@ +//==- RISCVSchedXiangShanKunMingHu.td - XiangShanKunMingHu Scheduling Defs -*- tablegen -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See

[clang] [llvm] [RISCV] Add processor definition and scheduling model for XiangShan-KunMingHu (PR #90392)

=?utf-8?b?6YOd5bq36L6+?= Message-ID: In-Reply-To: @@ -0,0 +1,1489 @@ +//==- RISCVSchedXiangShanKunMingHu.td - XiangShanKunMingHu Scheduling Defs -*- tablegen -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See

[clang] [llvm] [RISCV] Add processor definition and scheduling model for XiangShan-KunMingHu (PR #90392)

=?utf-8?b?6YOd5bq36L6+?= Message-ID: In-Reply-To: @@ -378,3 +378,31 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu", TuneZExtHFusion, TuneZExtWFusion,

[clang] [llvm] [RISCV] Add processor definition and scheduling model for XiangShan-KunMingHu (PR #90392)

=?utf-8?b?6YOd5bq36L6+?= Message-ID: In-Reply-To: llvmbot wrote: @llvm/pr-subscribers-clang Author: None (Bhe6669) Changes The "XiangShan" is a high-performance open-source RISC-V processor project, and The "KunMingHu" architecture is its third generation. Official documentation can

[clang] [llvm] [RISCV] Add processor definition and scheduling model for XiangShan-KunMingHu (PR #90392)

=?utf-8?b?6YOd5bq36L6+?= Message-ID: In-Reply-To: github-actions[bot] wrote: Thank you for submitting a Pull Request (PR) to the LLVM Project! This PR will be automatically labeled and the relevant teams will be notified. If you wish to, you can add reviewers by using the "Reviewers"