Thanks for let us know the result. But the explanation will be the warm
reboot path will modify the GPIO setting? Or the GPIO setting is floating
at the moment?
Lance
Zhiwen Zheng 于2021年11月8日周一 下午7:31写道：
> Add gpio.c from
>
Add gpio.c from
On Mon, 8 Nov 2021 13:18:07 +0530
"Naresh G. Solanki" wrote:
> Since the hang happens in Linux, can you in some way get Linux kernel log
> to understand the cause like soft lockup or panic message.
>
No.
> Also are you saying irrespective of serirq enable/disable, hang is seen?
>
> UART works
I just looked at the patch, it does not reenable continuous mode in ramstage.
So what I do is basically the same with that patch, but that doesn't work after
a warm reset for me.
I am wondering whether the gpio configuration of the soc is related to this
issue, I don't have access
to the BWG
Since the hang happens in Linux, can you in some way get Linux kernel log
to understand the cause like soft lockup or panic message.
Also are you saying irrespective of serirq enable/disable, hang is seen?
UART works properly in coreboot stages?
On Mon, 8 Nov, 2021, 1:02 pm Lance Zhao, wrote:
https://review.coreboot.org/c/coreboot/+/29398
Have similar implementation on braswell, so as long as sc_init get
executed in ramstage the serial irq mode programming shall be working.
Zhiwen Zheng 于2021年11月6日周六 下午6:29写道：
> I add the following code to sc_init() in southcluster.c to enable
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