[coreboot] XHCI device disconnect on S3 standby

Greetings, I'm unable to use any USB devices connected to an XHCI controller to resume from S3 standby, as something causes all connected devices to disconnect just prior to entering standby, as per the output of dmesg. I've traced the relevant sections in the southbridge and ACPI source for

Re: [coreboot] XHCI device disconnect on S3 standby

On 6/4/2014 1:06 PM, Duncan Laurie wrote: On Tue, May 27, 2014 at 3:17 PM, Matt DeVillier matt.devill...@gmail.com wrote: Greetings, I'm unable to use any USB devices connected to an XHCI controller to resume from S3 standby, as something causes all connected devices to disconnect just

Re: [coreboot] Request for Intel Haswell info

While a couple of the Haswell-based ChromeBooks have been added to upstream coreboot, but have not heard of anyone with them actually running yet. I know John Lewis had tried to get the HP ChromeBook 14 (falco) going but was not successful (though he does have the Chromium/falco branch

Re: [coreboot] problem with wake from suspend (asus chromebox 2955u)

As I mentioned on G+, it's almost definitely a kernel/distro config/device issue, as USB wake from suspend is working perfectly well for the Asus/HP ChromeBox (panther/zako) on other setups (OpenELEC, Fedora). Since you're using Ubuntu, ubuntuforums.com would be a good starting point I'd expect.

[coreboot] Unable to log into Jenkins after upgrade

as per subject, I previously logged in using OpenID/Google. Now when I try, I get the error: This OpenID https://www.google.com/accounts/ is new to Jenkins. Would you like to sign up? I can see that my account (matt.devillier) still exists, but have no way to mitigate the above

Re: [coreboot] commit 6b330f2a bricked my x60; a296f9e3 was working.

same issue here on Google/panther (Haswell), reverting the commit fixed things On 10/10/2014 4:09 PM, The Gluglug wrote: -BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Based on advice from Alexander I did: git revert 35382a6e Made my X60 boot, where without the revert I had the same issue

[coreboot] Haswell/panther - GPU memory allocation

Greetings! I'm looking to adjust the amount of system memory allocated to the GPU on panther (Haswell mobile), since certain applications (eg, Steam) report a suboptimal amount of GPU memory. lspci reports the following: 00:02.0 VGA compatible controller: Intel Corporation Haswell-ULT

Re: [coreboot] 'power on after fail' on Panther (Haswell/Lynxpoint)

On 3/26/2015 9:49 AM, Duncan Laurie wrote: On Wed, Mar 25, 2015 at 11:35 PM, Matt DeVillier matt.devill...@gmail.com mailto:matt.devill...@gmail.com wrote: Greetings all! I was wondering if it's possible to have Panther (Asus ChromeBox - Haswell/Lynxpoint) power on when AC power

[coreboot] 'power on after fail' on Panther (Haswell/Lynxpoint)

Greetings all! I was wondering if it's possible to have Panther (Asus ChromeBox - Haswell/Lynxpoint) power on when AC power connected regardless of the previous power state. Currently, the box will power on if AC power is lost and the device was powered on, but not if powered off. I have a

Re: [coreboot] cbmem console broken on Intel hardware since ec5e5e0

On 4/20/2015 3:29 PM, Aaron Durbin wrote: On Mon, Apr 20, 2015 at 9:23 AM, Matt DeVillier matt.devill...@gmail.com wrote: On 4/20/2015 8:51 AM, Aaron Durbin wrote: On Fri, Apr 17, 2015 at 12:32 AM, Matt DeVillier matt.devill...@gmail.com wrote: Greetings! When building upstream master

Re: [coreboot] cbmem console broken on Intel hardware since ec5e5e0

On 4/20/2015 8:51 AM, Aaron Durbin wrote: On Fri, Apr 17, 2015 at 12:32 AM, Matt DeVillier matt.devill...@gmail.com wrote: Greetings! When building upstream master tonight, discovered that cbmem console output is broken for Intel hardware (testing on google/panther). With some help on IRC

Re: [coreboot] Google Panther: coreboot has to wait for Intel’s ME (Management Engine)

On 4/26/2015 3:03 AM, Paul Menzel wrote: Dear coreboot folks, looking at the time stamps of the Intel Haswell device Google Panther, which Matt DeVillier thankfully uploaded to the board status repository [1], it looks odd that it took around a quarter of a second, from after the SeaBIOS

Re: [coreboot] Google Panther: coreboot has to wait for Intel’s ME (Management Engine)

use FSP. 27 apr 2015 kl. 22:42 skrev Duncan Laurie dlau...@chromium.org mailto:dlau...@chromium.org: On Mon, Apr 27, 2015 at 12:29 PM, Matt DeVillier matt.devill...@gmail.com mailto:matt.devill...@gmail.com wrote: On 4/26/2015 3:03 AM, Paul Menzel wrote: Dear coreboot folks

Re: [coreboot] Questions on building a Coreboot ROM for the Dell Chromebook 11

hi Marcos, I'm not a Google dev, just a hobbyist, but I've spent a lot of time over the past year working with coreboot for the Haswell ChromeOS devices (mostly the ChromeBoxes) and can offer some answers, inline below. On 5/8/2015 2:38 PM, Marcos Scriven wrote: I have a Dell Chromebook 11

[coreboot] cbmem console broken on Intel hardware since ec5e5e0

Greetings! When building upstream master tonight, discovered that cbmem console output is broken for Intel hardware (testing on google/panther). With some help on IRC from kmalkki, was able to determine the culprit is commit ec5e5e0 (New mechanism to define SRAM/memory map with automatic

Re: [coreboot] 'power on after fail' on Panther (Haswell/Lynxpoint)

system power state. I'd be happy for someone else to take a look and tell me I'm misreading though :) cheers, Matt On 3/26/2015 5:21 PM, Matt DeVillier wrote: On 3/26/2015 9:49 AM, Duncan Laurie wrote: On Wed, Mar 25, 2015 at 11:35 PM, Matt DeVillier matt.devill...@gmail.com mailto:matt.devill

[coreboot] Power on via USB, WoL from S5 on Panther (Haswell/Lynxpoint)

Greetings again! As a corollary / follow-up to my previous inquiry on automatic power-on when AC power applied, I'm now trying to get Panther (Asus ChromeBox - Haswell/Lynxpoint) to power on from S5 via a connected USB device (keyboard, mouse, IR remote) and via ethernet / wake-on-lan-- all

Re: [coreboot] Issues building a ROM for Toshiba Chromebook 2 (aka Swanky)

I have a Baytrail Chromebox (ninja) and ran into the same issues, but unlike swanky it has an intact debug port. I was supposed to get a servo unit on loan from one of the google coreboot guys but lost track with the holidays. I'll have to follow up on it as it's probably the best bet for

Re: [coreboot] Issues building a ROM for Toshiba Chromebook 2 (aka Swanky)

On 2/26/2016 5:48 PM, Julius Werner wrote: 2) I've also seen mention of Servo, but I don't seen any such header on my board. Looking at a photo of the Acer C720 here, it does look like there's an oblong space with pads there, but that would be a hell of a surface mounting job:

Re: [coreboot] coreboot toolchain update after 4.4 release

LGTM - no issues on google/panther On 4/21/2016 2:19 PM, Stefan Reinauer wrote: Hi folks! We're planning to update the coreboot reference toolchain very soon now, right after the coreboot 4.4 release which will roughly happen at the end of this month. We have fixed a few issues with the new

Re: [coreboot] Upstream coreboot/SeaBIOS on google/ninja -- no emmc, video

out a few things and will commit the board for review cheers, Matt On 5/14/2016 5:19 PM, Matt DeVillier wrote: Greetings all! Currently I'm working on getting upstream coreboot + SeaBIOS working on a Baytrail-based ChromeOS device (NINJA / AOpen Chromebox commerical). After resolving some

Re: [coreboot] Upstream coreboot/SeaBIOS on google/ninja -- no emmc, video

all the other boxes (ie, no built-in display) I've upstreamed, it's not been necessary to have coreboot run the vbios, only SeaBIOS. thanks, Matt On Sun, May 15, 2016 at 12:19 AM, Matt DeVillier <matt.devill...@gmail.com <mailto:matt.devill...@gmail.com>> wrote: Gree

Re: [coreboot] coreboot 4.4 testing / boot time regression on google/panther

bah, nevermind - seems that there was one config difference which was responsible for the problem (CONFIG_DRIVERS_UART_8250IO being set vs unset). Carry on with the 4.4 release :) On 4/18/2016 1:32 AM, Matt DeVillier wrote: Greetings, prompted by another posting on the topic, I also noticed

[coreboot] coreboot 4.4 testing / boot time regression on google/panther

Greetings, prompted by another posting on the topic, I also noticed a significant degradation in boot time on google/panther (Asus Chromebox / Haswell mobile) . I haven't had a chance to bisect commits yet, but did test a few older firmware builds to confirm my suspicion. Below are cbmem

Re: [coreboot] re-enabling boot for ChromeOS

On Thu, Jul 28, 2016 at 7:36 AM, Matthias Apitz <g...@unixarea.de> wrote: > El día Wednesday, July 20, 2016 a las 11:00:28PM -0500, Matt DeVillier > escribió: > > My C720 normally boots via SeaBIOS a FreeBSD operating system and there > are no such tools gbb_utility and f

Re: [coreboot] re-enabling boot for ChromeOS

Julius, wouldn't he also need gbb_utility to set the flags, in addition to (CrOS) flashrom to be able to read/write just the GBB region? That's why I suggested he use my ChromeOS Firmware Utility Script, since it would automatically download the required binaries as well as ensure the flags

Re: [coreboot] Welcome to the new coreboot.org!

looks fantastic, great job by all involved! On 9/7/2016 7:50 PM, Stefan Reinauer wrote: Hi! As some of you might already have noticed, our new web presence has gone live on https://www.coreboot.org/ today! I want to use this chance to send a big shout out to Philipp Deppenwiese and Martin

Re: [coreboot] What problems are there with native RAM initialization on Intel Sandy Bridge?

Hi Paul, I received feedback from a couple of users of my Stumpy firmware that they thought it had bricked the machine, only to realize it wasn't bricked when the either removed one of the sodimms or swapped out the factory modules for another pair. I wanted to compare results with the MRC blob

Re: [coreboot] [RFC] Deciding on style for multi-line comments

agree w/Julius as well. > 2 lines use verbose seems like a reasonable rule. On Fri, Aug 26, 2016 at 10:56 AM, Vadim Bendebury wrote: > I actually tend to agree with Julius that it does not make sense to waste > 4 lines for a two line comment. So, ideally the tool should

Re: [coreboot] using overlayfs to have several coreboot dev envs

On Sun, Nov 20, 2016 at 2:51 PM, ron minnich wrote: > I had the same thought even while writing that note. So option 2 for the >> config file is to create it at the top level: config.${MAINBOARD) or >> somewhere else. Would that work? > > using top level for config files

Re: [coreboot] Official builds for EoL Chromebooks

'm actually the one that started the reproducible builds thread last time > precisely because I could not get the same ROM image as the ones posted > online and I was wondering what I did wrong and if I would brick my laptop > or not. > > > > --emi > > On Thu, Oct 13, 2

Re: [coreboot] Official builds for EoL Chromebooks

Emi, I think this is what you're looking for: https://www.coreboot.org/Supported_Motherboards It contains the commit hash, build config, and a few other logs for each device/commit. It is user submitted though, since there doesn't exist a test setup for every supported device. Right now, I'm

Re: [coreboot] Official builds for EoL Chromebooks

a build on my Acer C710 (which is probably > the only Chromebook with upgradeable RAM and disk). > > > > --emi > > On Thu, Oct 13, 2016 at 6:49 PM, Matt DeVillier <matt.devill...@gmail.com> > wrote: > >> well, in order for that to happen, someone woul

Re: [coreboot] power controller/serial port mux

Ron, I've used one of these on another project for remote power control: http://www.digital-loggers.com/lpc.html -- seems to work reliably, and can be controlled via simply http(s) commands -Matt On Tue, Jan 10, 2017 at 3:56 PM, ron minnich wrote: > I need an

Re: [coreboot] Maintain boot order for multiple EFI based OS

On Fri, Mar 24, 2017 at 6:26 PM, wrote: > > > For your question, takes around 26 seconds from power On till Tianocore > execute completion. Looking at reducing this boot time. > > > Sibi, if you're not using mrc cache for RAM training, that's likely contributing 10s or

Re: [coreboot] Maintain boot order for multiple EFI based OS

Maurice, that seems like the kind of functionality it would make sense to handle in an abstracted way (perhaps using libpayload?) and let coreboot handle the board-specific flash interface. Has anyone looked into that kind of approach? This is something that's actually been on my to-do list for

Re: [coreboot] Power supply and X220

On Tue, Mar 21, 2017 at 8:56 AM, Felix Held wrote: > For a x220 the 3,3V regulator on the BBB likely doesn't supply enough > current, since the Thinkpads usually don't have a diode in the power supply > line of the SPI flash and so you power part of the board when

Re: [coreboot] VGA and Graphics

On Tue, Apr 4, 2017 at 2:23 PM, Zoran Stojsavljevic < zoran.stojsavlje...@gmail.com> wrote: > Furthermore, let me tell you all that this is a mechanism to support ONLY > The Legacy BIOS (UEFI works ONLY with GOP, but this is another > dimension/discussion), and, to all of your knowledge (which I

Re: [coreboot] VGA and Graphics

Linux as Run Time info (via HOB). > Then Linux brings from scratch GFX, using its own, modern I/Fs. And ports > appropriate drivers to existing GFX info from HOB. > > Zoran > > On Tue, Apr 4, 2017 at 11:51 PM, Matt DeVillier <matt.devill...@gmail.com> > wro

Re: [coreboot] Where to get ME image/flash descriptors for the x220?

I have the IFD and ME from an x220 that I recently flashed with coreboot for a customer, extracted from their stock firmware, and verified working with the coreboot ROM I subsequently flashed. Can zip and send via email, or whatever you prefer On Mon, Mar 6, 2017 at 10:23 PM, taii...@gmx.com

Re: [coreboot] Suggestions on shipping ARMv8 Chromebook

On Thu, Mar 2, 2017 at 12:42 PM, wrote: > On 2017-02-17 10:10, Patrick Georgi wrote: > >> The just-released Chromebook Plus comes with an RK3399 SoC, which is >> ARMv8 and fully open at the AP firmware level (GPU is Mali with its >> usual issues, as well as Wifi firmware).

Re: [coreboot] The ECC 2017 web page

I'm seeing ~90MB RAM use and low single digit CPU usage here on Win10/Chrome - what browser/OS you you seeing 25% on? On Thu, Mar 2, 2017 at 11:11 PM, ron minnich wrote: > That one web page, while not even visible, eats up 25% of the cpu on one > core of my osx laptop. > >

Re: [coreboot] How can we get MRC.bin for Intel platform.

Since your board is a Broadwell-U, easiest way will be to extract it (along with the required refcode blob) from the generic/shellball image firmware for a Broadwell-U Chromebook (using cbfstool), which itself can be extracted from a ChromeOS recovery image. John Lewis wrote up some helpful

Re: [coreboot] Broadwell-U hangs at VGA init

- > *From:* Nico Huber <nico.hu...@secunet.com> > *Sent:* Monday, July 31, 2017 10:52 AM > *To:* Zheng Bao; coreboot@coreboot.org; Matt DeVillier; > stefan.reina...@coreboot.org > *Subject:* Re: [coreboot] Broadwell-U hangs at VGA init > > Hi Zheng, >

Re: [coreboot] help with Chromebook linux install

Sean, you can easily change the firmware boot flags using my Firmware Utility Script: https://mrchromebox.tech/#fwscript you'll want option #4, then select the option for '1s + Legacy Boot default.' You can optionally remove the Developer Mode splash screen completely via option 6. cheers,

Re: [coreboot] Anyone got an opinion, technical or otherwise, on this?

On Wed, May 3, 2017 at 4:17 AM, John Lewis wrote: > I think I've answered my own questions by checking out the menuconfig > options, it looks to me as though up to and including Skylake is possible, > and flashing internally *should* be okay? > Since writing to the ME region

Re: [coreboot] Denver conference

On Thu, Jun 1, 2017 at 2:46 PM, Youness Alaoui < kakar...@kakaroto.homelinux.net> wrote: > Then I suppose once they arrive at the conference registration booth > to get their lanyard, they'll be told hat they haven't paid yet and > that they can pay now in cash (and credit cards?). Not that >

Re: [coreboot] Coreboot on X230 and Dualboot / How to make it work

On Sat, Sep 23, 2017 at 3:01 PM, Peter Stuge wrote: > One7two99 via coreboot wrote: > > add which location should I place my extracted vga blob, so that it > > can be found during the Coreboot Build process > > Paths entered during configuration reference the source root

Re: [coreboot] Coreboot on X230 and Dualboot / How to make it work

On Sep 23, 2017 12:35 PM, "One7two99 via coreboot" wrote: Original-Nachricht an 23. Sep. 2017, 16:56, Klemens Nanni schrieb: >> These are 4/8 *mebi*byte in size. Yes of course ;-) just a typo as I am more used working with GB than MB these days... >>

Re: [coreboot] [RFC] Successful build with GCC 7.2 and IASL 20170831 for coreboot 4.7

hi Paul, I took a look at this, and the error appears to be the result of a change in IASL 20170531: "Improved the behavior of the iASL compiler and disassembler to detect improper use of external declarations" According to the ACPI 6.2 spec, "The External directive informs the ASL compiler

Re: [coreboot] USB problem with Haswell+LynxPointLP motherboards

my solution to the flakiness of EHCI on Haswell ChromeOS devices was to route everything to the XHCI controller / use XHCI finalization (CONFIG_FINALIZE_USB_ROUTE_XHCI=y), and to use Broadwell's XHCI init code. Obv doesn't help if you need ECHI debug (eg), but perhaps a a slightly different

Re: [coreboot] Coreboot Purism BIOS is free? open?

On Sun, Dec 17, 2017 at 6:58 PM, taii...@gmx.com wrote: > On 12/17/2017 05:06 PM, Dame Más wrote: > > Hi, >> The Coreboot BIOS of Purism 13 is open? >> > No it isn't, while they do use coreboot the silicon init process is > entirely blobbed. > > Technical merits - is it better

Re: [coreboot] Disabling Intel ME 11 via undocumented mode

On Fri, Dec 15, 2017 at 10:23 AM, Zoran Stojsavljevic < zoran.stojsavlje...@gmail.com> wrote: > IME (I is typo) = ME . > pretty sure the I is for Intel ;-) (or, at least that's how I've seen it referenced elsewhere) > > Zoran > -- coreboot mailing list: coreboot@coreboot.org

Re: [coreboot] 2nd attempt: Coreboot + Windows (with Resume working)

On Sat, Nov 11, 2017 at 4:03 AM, [799] via coreboot wrote: > Hello, > > I had to reflash my stock original BIOS after I couldn't get Sleep > working on my Lenovo X230. > > I am in a situation where I was able to get 2 situations: > > 1) Situation 1: > working sleep+resume

Re: [coreboot] Who has experience with the Intel RVP7 (or RVP15) CRB?

On Sat, Nov 4, 2017 at 7:16 AM, Nico Huber <nic...@gmx.de> wrote: > Hi Matt, Jay, > > On 04.11.2017 03:25, Matt DeVillier wrote: > >> Hi Jay, >> >> the SKL/KBL FSP blob published on Github is compatible with the headers >> currently in coreboot, with

Re: [coreboot] Who has experience with the Intel RVP7 (or RVP15) CRB?

On Sat, Nov 4, 2017 at 11:18 AM, Jay Talbott < jaytalb...@sysproconsulting.com> wrote: > Ok, more details... > > I'm currently building Coreboot off the end of the master branch as of > commit 43a285f983f6c29467d7f30f7e2b402926bd5c6f, but might back up to the > commit where the RVP7 support was

Re: [coreboot] Who has experience with the Intel RVP7 (or RVP15) CRB?

80) 445-9895 (FAX) > jaytalb...@sysproconsulting.com > > http://www.sysproconsulting.com > > > > *From:* Matt DeVillier [mailto:matt.devill...@gmail.com] > *Sent:* Saturday, November 04, 2017 9:59 AM > *To:* Jay Talbott > *Cc:* Nico Huber; coreboot; Stefan Reinauer > &g

Re: [coreboot] Does S3 work on Haswell boards?

On Thu, Nov 2, 2017 at 1:48 PM, Nico Huber wrote: > Hi Aladyshev, > > On 30.10.2017 16:49, Аладышев Константин wrote: > >> Does S3 work on Haswell boards? >> > > It definitely worked at some point. Matt might know a latest revision > where it was tested on Chromebooks or maybe can

Re: [coreboot] Who has experience with the Intel RVP7 (or RVP15) CRB?

Hi Jay, the SKL/KBL FSP blob published on Github is compatible with the headers currently in coreboot, with the exception of the MEMORY_INFO_DATA_HOB - as is, coreboot will not be able to parse the HOB and populate the SMBIOS tables (minor adjustment needed, see: https://pastebin.com/Um9m7X43),

Re: [coreboot] SeaBIOS boot order / can't boot from USB

back with results once I've done some testing. > > Thanks again, > Hal > > On Sat, Dec 2, 2017 at 7:08 PM, Matt DeVillier <matt.devill...@gmail.com> > wrote: > >> >> Hal, >> >> your USB controllers are at 14.0 and 1d.0, so your bootorder file needs

Re: [coreboot] SeaBIOS boot order / can't boot from USB

Hal, your USB controllers are at 14.0 and 1d.0, so your bootorder file needs to enumerate all devices attached to said controllers. I'm not sure how many devices can be attached to each for IvyBridge, but here's the bootorder file Google uses for reference:

Re: [coreboot] lenovo x220, tool to extract binary blobs from BIOS update

On Thu, Apr 26, 2018 at 10:05 AM diffusae via coreboot < coreboot@coreboot.org> wrote: > > Don't know, if gbe.bin or ifd.bin is vulnerable. > they are configuration "blobs" not binary blobs, no executable code -- coreboot mailing list: coreboot@coreboot.org

Re: [coreboot] ACPI error booting Windows

at > your .config? Perhaps I'll be able to spot something > -- > *From:* Matt DeVillier <matt.devill...@gmail.com> > *Sent:* Wednesday, April 25, 2018 4:14 PM > *To:* alexfein...@hotmail.com > *Cc:* coreboot > *Subject:* Re: [coreboot] ACPI erro

Re: [coreboot] Recommended workflow with Chromebook support

On Fri, Jan 5, 2018 at 6:19 PM, wrote: > Folks, > This question is directed at the Coreboot developers who target a > Chromebook device. > > Do you tend to do bulk of development and testing within chromiumos > coreboot tree or directly in coreboot.org tree? > > As we get

Re: [coreboot] smd work

I've replaced SOIC-8 SPI chips with just a 15W soldering iron - the biggest issue is ensuring that the new chip has same voltage requirements as the old chip / board is providing. Many of the 8MB parts are 3.3v and most of the 16MB ones I've seen (at least in Chromebooks) are 1.8v On Thu, Dec

Re: [coreboot] anyone know what happened here?

from what I recall, the driver was trying to be responsible and lock SPI write access by default, but due to the off-by-one, ended up setting the 'inverse' bit on the 2nd status register of some chips, which reversed the RO and RW regions of the chip. This naturally led to the EFI variables not

Re: [coreboot] anyone know what happened here?

EFI firmware (BIOS) can't write to NVRAM to save settings, because the NVRAM region is now RO. Nothing can be changed until the offending bit in SR2 is cleared, which in some cases even prevents booting from USB. Zoran On Fri, Dec 22, 2017 at 4:36 AM, Matt DeVillier <matt.devill...@gmail.com> wro

Re: [coreboot] Reducing the boot time

assuming you've built with CONFIG_COLLECT_TIMESTAMPS=y, you can build/run the cbmem utility and see how long each stage/section of coreboot is taking (up to the point of handing off control to the payload). 30s to boot sounds like either you're not caching the RAM training data (MRC cache) and

Re: [coreboot] REG : GOP Driver

with Intel iGPUs and using Tianocore UEFI payload, Linux is fine regardless if the display is initialized or not by GOP driver. Windows is fine as long as valid VBT data has been loaded into the Intel ACPI OpRegion, and the OpRegion is valid/has been fully populated. On Thu, Aug 30, 2018 at 7:57

Re: [coreboot] REG : GOP Driver

t that sounds correct. I know the Windows installer uses a basic driver of some sort, and likely assumes a working framebuffer exists > > Correct me if I'm wrong. > > //BR > Nagaraj A > > > On Thu, 30 Aug 2018, 8:57 pm Matt DeVillier, > wrote: > >> with Intel iGPU

Re: [coreboot] How to handle vbt.bin

my instinct is to put it in the 3rd party blobs repo, since it's added to the CBFS w/o modification (ie, is treated like a blob), unlike the SPD hex files which are selectively ordered and assembled into the spd.bin (ie, treated as source). For the example case you sited of users building

Re: [coreboot] How to handle vbt.bin

On Thu, Apr 5, 2018 at 11:29 AM, Nico Huber <nic...@gmx.de> wrote: > On 05.04.2018 18:15, Matt DeVillier wrote: > > my instinct is to put it in the 3rd party blobs repo, since it's added to > > the CBFS w/o modification (ie, is treated like a blob), unlike the SPD

Re: [coreboot] how does FSP play its role in Haswell/Broadwell/Skylake

Haswell and Broadwell don't use FSP, they use the MRC blob for RAM init. For Haswell, coreboot does all of the silicon init as well; for Broadwell, coreboot does most of the silicon init, and some bits are handled by another blob (refcode.elf). Skylake uses FSP (1.1 or 2.0, depending on the board

Re: [coreboot] ACPI error booting Windows

I have Windows booting on a KBL CrOS device, and looking at my tree, pretty sure the only change I have that would potentially address that error is adding the pcon value to the IGD ACPI OpRegion header: https://github.com/MattDevo/coreboot/commit/3349065354709c85276168272469797dd3f6 there

Re: [coreboot] [skylake] Can not turn monitor on

On Fri, Oct 5, 2018 at 3:27 PM Nico Huber wrote: > > On 10/5/18 4:43 PM, Zheng Bao wrote: > > I transfer all the GPIO setting to my code. > > What do you mean? did you have wrong GPIO settings before? > > > After this, the linux can turn the monitor on, but in BIOS stage, > > monitor can not be

[coreboot] Watchdog timer (WDT) support on Kabylake w/FSP2.0

greetings! I'm trying to enable WDT support for Kabylake Chromeboxes (google/fizz) but not having any luck. The current SoC code doesn't expose the FSP fields which appear to control this (WdtDisableAndLock, WatchDog, WatchDogTimerOS, WatchDogTimerBIOS), so I added them to chip_fsp20.c and set

[coreboot] Re: Graphics Mode

hello Ranga, what method and setting do you have selected for graphics init? 400x300 would indicate that coreboot is initializing the display in VGA text mode, rather than a VESA framebuffer mode - you likely need to change this in Kconfig. The Tianocore coreboot framebuffer GOP driver can only

Re: [coreboot] Asus Chromebox Panther: no HW RNG?

On Tue, Nov 27, 2018 at 1:15 AM Grant Grundler wrote: Hi! Asus Chromebox (Panther) with Celeron 2995U processor is supposed to have a HW Random Number Generator: https://ark.intel.com/products/75608/Intel-Celeron-Processor-2955U-2M-Cache-1-40-GHz- (Intel calls it Secure Key) But

Re: [coreboot] uefi rootkit (lojax)

On Tue, Nov 20, 2018 at 8:20 AM Ivan Ivanov wrote: > > Thank you for the info! However we are not affected thanks to > coreboot's default payload being SeaBIOS. If anything, these "uefi > rootkit" news could be used to promote the coreboot(+SeaBIOS) project > to wider audiences that's a pretty

[coreboot] Re: VBIOS/VBT in Coreboot

what payload is being used here? If SeaBIOS, you'd ideally want SeaBIOS to run the VGA BIOS, not coreboot (in which case, only the oprom name in cbfs needs to match the PCI ID, not the one in the VBIOS header - only coreboot checks that). You'd set coreboot's display init to none, and simply

[coreboot] Re: VBIOS/VBT in Coreboot

UEFI is a specification; exploits are necessarily against implementations thereof, not the spec itself. Tianocore is a partial reference implementation of the UEFI spec, and the package built for use with coreboot an even smaller subset of that (since it completely skips the PEI phase). So

[coreboot] Re: VBIOS/VBT in Coreboot

do you have any evidence to support that Tianocore is vulnerable to this type of malware (given that it doesn't support module injection/persistence, as implemented), or in any way less secure than a "traditional" payload? If not, then your warning strikes me as nothing more than FUD On Wed, Feb

[coreboot] Re: Intel Braswell uploads

hi Frans, I'm happy to review these patches (and think I have for some already), but as my Braswell-based ChromeOS boards don't require them, a little more explanation in the commit msgs as to what issue they are resolving would be helpful in that regard. Obviously I'd like to test them and

[coreboot] Re: Refactor tianocore payload

On Thu, Feb 14, 2019 at 3:11 PM Nico Huber wrote: > On 14.02.19 09:28, Patrick Rudolph wrote: > > On Wed, 2019-02-13 at 10:15 +0100, Nico Huber wrote: > >> On 13.02.19 09:45, Patrick Rudolph wrote: > >>> With UEFI the defactor standard it seems reasonable to improve the > >>> tianocore payload

[coreboot] Re: VBIOS/VBT in Coreboot

gt; > > From: Matt DeVillier > Sent: Monday, February 18, 2019 10:10 PM > To: Alex Feinman > Cc: Nico Huber; coreboot@coreboot.org > Subject: Re: [coreboot] Re: VBIOS/VBT in Coreboot > > what payload is being used here? If SeaBIOS, you'd ideally want SeaBIOS to > run th

[coreboot] Re: Removal of mainboard Intel/Strago

one thing we don't want to is change however is 'Intel_Strago' as the default mainboard family for google/cyan variants, since at least one Braswell platform kernel driver uses that identifier to enable certain quirks On Sat, Apr 13, 2019 at 2:45 PM Lance Zhao wrote: > I am not sure how many of

[coreboot] Re: New Intel microcode release for migiating ZOMBIELOAD FALLOUT AND OTHERS

On Wed, May 15, 2019 at 9:58 AM Nico Huber wrote: > On 15.05.19 16:43, Kinky Nekoboi wrote: > > Someone should push them to coreboot. > > Agreed, can you do that? > > > > > Debian already has them. > > or alternatively, could you provide an upstream URL, please. >

[coreboot] Re: Starting the coreboot 4.10 release process

nocore master branch build from edk2 will break, but that had been > quite some time. Stable branch is working fine though. > > On Mon, Jun 3, 2019, 3:28 AM Matt DeVillier > wrote: > >> On Sun, Jun 2, 2019 at 1:27 PM Mike Banon wrote: >> >>> >>> Als

[coreboot] Re: Starting the coreboot 4.10 release process

On Sun, Jun 2, 2019 at 1:27 PM Mike Banon wrote: > > Also, regarding the significant changes: " ### Tianocore UEFI > integrated as payload " . I hope it doesn't mean that Tianocore will > become the default payload, since there are ideological/technical > reasons against this ( I think there's a

[coreboot] Re: Starting the coreboot 4.10 release process

I added those devices, all of which I have in my possession and were tested over the weekend with TOT. I'd not yet had a chance to upload board status for them, but figured knowing a good range of platforms/boards were known working just prior to release was useful (and the purpose of the list)

[coreboot] Re: Starting the coreboot 4.10 release process

no point in doing so. If UefiPayloadPkg is functional as-is, then we can certainly switch over to it, but my understanding is that it is not. And I haven't had time to investigate/test myself. > > > On Sun, Jun 2, 2019 at 11:41 PM Matt DeVillier > wrote: > > > > there is no "s

[coreboot] Re: Building ChromeOS from source

https://chromium.googlesource.com/chromiumos/docs/+/master/developer_guide.md On Sat, Jun 15, 2019 at 4:54 PM Gregg Levine wrote: > Hello! > An interesting thought came to me yesterday. And is still ringing a > loud sound today. > > Is it possible to obtain and build ChromeOS from source? > > I

[coreboot] Re: inteltool does not properly dump gpio values for south bridge CM238 chipset

support already exists in intelmetool for several 7th-gen/Kabylake platforms, just not KBL-H. Easiest thing to try would be to add the PCI IDs into inteltool.h next to the existing ones for KBL north/south bridges (ie, add: #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_H 0x5910) then add it everywhere

[coreboot] Re: inteltool does not properly dump gpio values for south bridge CM238 chipset

whoops, I meant inteltool, not intelmetool On Tue, May 21, 2019 at 6:14 PM Matt DeVillier wrote: > support already exists in intelmetool for several 7th-gen/Kabylake > platforms, just not KBL-H. Easiest thing to try would be to add the PCI > IDs into inteltool.h next to the exis

[coreboot] Re: Any live usb for recovery flash coreboot?

On Fri, Nov 1, 2019, 2:32 PM wrote: > Thankyou very much! I followed Nico's method and it works. > I'm wondering does coreboot support "hybrid boot" mode like some > motherboard does? that's not a function of coreboot, but of the payload (Tianocore). It should be possible to. build Tianocore

[coreboot] Re: Any live usb for recovery flash coreboot?

On Thu, Oct 31, 2019 at 1:58 AM Dalao wrote: > Hi, I was using Seabios but recently switched to Tianocore. However, the > tianocore can't boot my Manjaro linux distribution which was installed > using the non-uefi method. So I want to flash back. > why not simply boot your live USB, create a

[coreboot] Re: Any live usb for recovery flash coreboot?

On Thu, Oct 31, 2019 at 8:16 PM Branden Waldner wrote: > I tested Nico's method for you with a Debian bios install, but it > might be different for the Manjaro live usb. > > To stall grub from booting, you can press the left arrow key > repeatedly, assuming that doesn't mess with tianocore

[coreboot] Re: Tianocore: Long time to boot / Menu.

hi Jose, a long boot time in Tianocore usually means that you have serial output enabled to a port that doesn't exist. Is this with a debug build? What board, what serial port config? When I was first testing this years ago, it took 8 mins to boot on one board because of this cheers, Matt On

[coreboot] Re: chromebook acer r11 cb5132t

> Den 14 december 2019 19:58:23 skrev Matt DeVillier < > matt.devill...@gmail.com>: > >> please resubmit your question in plain text format, nobody can read what >> you sent >> > ___ > coreboot mailing list -- coreboo

[coreboot] Re: Tianocore: Long time to boot / Menu.

On Thu, Dec 5, 2019 at 3:24 AM Jose Trujillo wrote: > > Hello Matt. > I also remember when I was working with a baytrail system I had to attach > something to the LPC device in order to prevent this... Once I correctly set > the SIO under LPC the problem was gone. > > In this case I don't have

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