Re: [coreboot] IMB-A180 Real Time Clock is 20-30% slow (coreboot only, not original AMI BIOS)

Hi Mark, First, Linux rarely uses the real time clock - use the 'hwclock' tool to query it repeatedly and compare that against your stop watch to figure out if RTC is involved. If it isn't: Linux keeps its own system clock which is only once synchronized against RTC. I don't know off-hand what

Re: [coreboot] Unifying IO accessor macros

2015-02-18 18:35 GMT+01:00 Aaron Durbin via coreboot coreboot@coreboot.org: coreboot is different than: 1. linux 2. uboot And similar to Solaris, Windows and the BSDs. As for libpayload, I'd rather import code from BSD than Linux for licensing reasons. 3. libpayload 4. Anything using

Re: [coreboot] Automated test system: Nominations wanted

2015-02-19 0:14 GMT+01:00 Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net: I am currently planning to set up a test system with 5 (later up to 10) machines boot testing each new coreboot commit. This test system will be serviced (i.e. recovery from bricking) Mo-Fr during CET/CEST

Re: [coreboot] Unifying IO accessor macros

2015-02-18 17:23 GMT+01:00 Vadim Bendebury vben...@chromium.org: kernel, u-boot, etc. They all have the write(val, addr) semantics. I see no good reason to artificially erect an ever present barrier for integrating code into a coreboot system. Since all imported code requires some rework

Re: [coreboot] Automated test system: Nominations wanted

2015-02-19 17:22 GMT+01:00 Kevin O'Connor ke...@koconnor.net: It would be a bit of work to get the software working and packaged nicely - but if it was, I think it could enable many more users to participate in automated tests and remote development. That already was the hope of many coreboot

Re: [coreboot] questions about google/samus

Hi all, I put the mailing list under emergency moderation for a while because things heated up quickly. This wasn't coordinated with anyone, so please direct complaints about that at me. All incoming emails (to this thread = all of them) in that period were rejected with an explanation (I hope

Re: [coreboot] [Rangeley C2000] Can't step when in romstage main function of MohonPeak

Hi Hook Guo, 2015-03-27 11:11 GMT+01:00 郭佳 yunyua...@gmail.com: At the time this main function has been called, the Cache as RAM has been setup by FSP, and the MTRR_PHYSBASE0 is FEF0_0006. BTW: (1) Using the debugger's memory window, I can see Cache as RAM region of temporary stack are

Re: [coreboot] Long license headers (ANGER WARNING)

2015-03-04 18:32 GMT+01:00 ron minnich rminn...@gmail.com: Peter, per Patrick's note here, and discussions I've had with people who actually are real lawyers, who earn their money doing IP licensing, I think you are quite wrong. We should not change the license text in the files *unless it is

Re: [coreboot] Long license headers (ANGER WARNING)

2015-03-04 14:58 GMT+01:00 Peter Stuge pe...@stuge.se: I haven't gotten the impression that anyone is suggesting to remove or even change any copyright notices. Copyright documents authorship (like git does too) but says nothing about licensing terms. Section 1 of the GPLv2 contains: keep

Re: [coreboot] Coreboot reproducible builds

2015-02-26 16:23 GMT+01:00 Emilian Bold emilian.b...@gmail.com: It seems that Coreboot doesn't have reproducible builds yet. You're right, it doesn't. One of the major items is probably to replace the current build time stamps with something more reasonable. For example, the current commit's time

Re: [coreboot] Building ARM toolchain fails with `cc1: fatal error: .vis: No such file or directory`

2015-02-26 21:56 GMT+01:00 Aaron Durbin adur...@chromium.org: I reproduced the error. I was trying to figure out how to debug it. I entered into the util/crossgcc/build-armv7-a-eabi-gcc directory and typed make. Everything worked... I'm trying again. I'm not really sure why one way would fail

Re: [coreboot] New interface for I2C in coreboot

2015-02-19 21:12 GMT+01:00 Peter Stuge pe...@stuge.se: I think the question is really what we would gain from this. I think it's less about performance and more about an accurate and clean model being available to mainboard code when needed. From discussing things with Werner, one of his

Re: [coreboot] Zako coreboot serial output does not insert 'return caret'

2015-04-21 7:35 GMT+02:00 Anatol Pomozov anatol.pomo...@gmail.com: I use google's servo to deploy FW to the board and I see a weird debug log in my console. The log from coreboot looks like newline is inserted, but return caret is not. SeaBIOS debug looks normal. Here and the log example

[coreboot] Reviving flag days

Hi, some of you might remember the flag days initiative, which led to some useful information on how to keep up with upstream development while maintaining local branches (or repos). If you don't, please look at the marvel that is http://coreboot.org/index.php?title=Flag_Daysoldid=10718 The

[coreboot] gerrit authentication

Hi, To provide more options to contributors, it's now possible to login to our code review system at http://review.coreboot.org using GitHub credentials. On the login screen, simply pick 'GitHub OAuth2'. If you already have an account, you can link your GitHub account to it by logging in on

Re: [coreboot] QEMU x86_64 Q35 Automated Test Failure

2015-04-21 17:31 GMT+02:00 Gregg Levine gregg.drw...@gmail.com: I suspect somehow it was supposed to be internal to hs outfit only. Timothy provides boot testing of coreboot master with QEmu and a AMD board that he maintains as a service to the community. And something changed with regards to

Re: [coreboot] error building coreboot

2015-04-28 8:42 GMT+02:00 c...@posteo.de: after running make im getting the following error and the building process is stopped: - /coreboot/util/cbfstool/cbfs_image.c:451:59: error: comparison between signed and unsigned integer expressions [-Werror=sign-compare]

Re: [coreboot] QEMU build failure in master

2015-05-05 21:49 GMT+02:00 Timothy Pearson tpear...@raptorengineeringinc.com: While working on the test system earlier today I noticed that QEMU builds are currently failing with the following error: coreboot/src/lib/timestamp.c:184: undefined reference to `timer_monotonic_get' Builds using

Re: [coreboot] [poll] device_t

2015-05-07 22:00 GMT+02:00 Stefan Reinauer stefan.reina...@coreboot.org: With our current bootblock concept, it is never going away on x86 (for bootblock usage) Which isn't that much of a problem once we provide separate headers for x86 bootblock code. There's really very tiny overlap. That

Re: [coreboot] [poll] device_t

2015-05-08 17:31 GMT+02:00 Aaron Durbin adur...@google.com: In romstage *both* struct device and device_t are present but are completely different types. It's the romstage, ramstage, and smm overlap that is large and extremely annoying to deal with. History time: Until not too long ago,

Re: [coreboot] coreboot ported to the ASUS KGPE-D16 (Libreboot: blobless, fully functional!)

2015-05-03 23:12 GMT+02:00 Emilian Bold emilian.b...@gmail.com: I'm curious, is there some Coreboot Foundation that would gather this money and purchase the copyright or would Raptor just somehow crowd-fund this money to license their work as GPLv2 while keeping the copyright? With coreboot

Re: [coreboot] force https on review.coreboot.org

2015-04-16 15:57 GMT+02:00 Alexander Couzens lyn...@fe80.eu: than let us change to StartSSL or someother SSL authority. I'll ask CNNIC. I heard they have good offers. PPS. Please write a +1 if you're supporting this opinion. Please don't. Patrick -- Google Germany GmbH, ABC-Str. 19, 20354

[coreboot] Gerrit access rules

Hi, after deliberation to encourage positive feedback, gerrit rules are changed so that 'reviewers' can now give +2 Code-Reviews. Patrick -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg Geschäftsführer: Graham

[coreboot] Server maintenance done. Action Required for users that authenticate with Google accounts

Hi, gerrit maintenance is done, the site is back to normal. What changed: Besides the current OpenID configuration, it's now also possible to log in with OAuth. This change is necessary because Google will retire the OpenID authentication scheme for their users this month. I also considered

[coreboot] server maintenance: review.coreboot.org will be down on 2015-04-09 morning CEST

Hi, I'll do some maintenance on our code review site tomorrow morning (CEST). There's not really a schedule, but it will be quicker than last time. I plan to integrate an authentication module to support Google accounts for authentication beyond April 20th when Google retires the protocol we

[coreboot] License headers

Hi, we had some fun discussion a while back about the license headers we use in our tree. Asking legal experts, they proposed we go for keeping the usual GPL license header intact, only stripping the FSF address (which gave the most churn on licenses in our tree, and as you can see in the commit

Re: [coreboot] x230 - vgabios

2015-05-23 1:06 GMT+02:00 Michael Gerlach n...@terminal21.de: GET_VBIOS: 7b46 3714 8b a2 e9 printk(BIOS_DEBUG, GET_VBIOS: %x %x %x %x %x\n, oprom-signature, pcir-vendor, pcir-classcode[0], pcir-classcode[1], pcir-classcode[2]); But Signature should be

Re: [coreboot] Rebuilding coreboot image generation

2015-11-09 21:47 GMT+01:00 Julius Werner : > If Intel's architectural requirements force us to have a component > that must be linked at an exact spot in the image, I think it would > only be consistent to use the tool that we have which is meant for > these sorts of

Re: [coreboot] Long boot delay with a large CBFS

2015-11-16 19:32 GMT+01:00 Ben Gardner : > What is the purpose behind continuing if a bad entry is encountered? > It appears that a 'bad' entry only occurs at the end of the CBFS. With a properly chained CBFS, there are no such entries (except one at the end, maybe), and

Re: [coreboot] Payload that can do mmio32/pciserial UART on x86

2015-11-19 4:49 GMT+01:00 Alex G. : > So, is there something? FILO. It uses libpayload for drivers which has uart8250_mmio32.c. Patrick -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg

Re: [coreboot] Rebuilding coreboot image generation

Let's extend your example so it becomes somewhat comparable to my proposal: HOST_FIRMWARE@0xff80 8M { SI_ALL 2M { SI_DESC 4K SI_ME 0x1ff000 } SI_BIOS { RW_A 0xf { VBLOCK_A 64K

Re: [coreboot] Rebuilding coreboot image generation

So you think we're better off with one place to store the partition layout, a separate one to store what files belong where, and yet another one for the properties of those files, each with their own syntax and tooling? 2015-11-21 1:08 GMT+01:00 Julius Werner : >> Let's

Re: [coreboot] Rebuilding coreboot image generation

2015-11-21 5:08 GMT+01:00 Peter Stuge : > And it's certainly possible to implement fixed placement. The main drawback of CBFS, pretty much from the start, was that it creates a single chain of files, which makes it hard to implement certain designs safely: You need to be extra

Re: [coreboot] cbfstool: CBFS alignment broken due to FMAP

2016-01-18 21:34 GMT+01:00 Ben Gardner : > Is there a work-around for this? For example, is there an option to > pad the FMAP out to 4 KB? The workaround is indeed to increase the FMAP region's size to 4K. To do this, edit $(top)/Makefile.inc, line 708 (since you're on x86,

Re: [coreboot] RFC: coding style: "standard" defines

2016-02-04 10:35 GMT+01:00 Patrick Georgi : > during the review of some commits that are in the process of being > upstreamed from Chrome OS, people noticed that chipset drivers like to > define their own TRUE/FALSE defines (sometimes prefixed to), and I > have seen a bunch of

[coreboot] Google Summer of Code 2016

Hi all, so Google just announced[0] that they're running their Summer of Code program again. I'm preparing to be the project admin this year, but to make this real we'll need contributors that are willing to step up as mentors. I need to know the number of candidates by Feb 19th, and we're told

[coreboot] RFC: coding style: "standard" defines

Hi all, during the review of some commits that are in the process of being upstreamed from Chrome OS, people noticed that chipset drivers like to define their own TRUE/FALSE defines (sometimes prefixed to), and I have seen a bunch of #define BIT{0-31} ..., too, because that seems to be the house

Re: [coreboot] RFC: coding style: "standard" defines

t; How would people feel about adding something to the coding guide to > avoid magic numbers? Make that a separate thread please :-) Patrick > On Thu, Feb 4, 2016 at 6:05 AM, ron minnich <rminn...@gmail.com> wrote: >> >> >> On Thu, Feb 4, 2016 at 2:29 AM Patrick Geo

Re: [coreboot] Removed boards list.

2016-02-08 23:19 GMT+01:00 Denis 'GNUtoo' Carikli : > The unfortunate downside is that, assuming that coreboot worked fine on > such boards in the past (and may still do), they don't show up in any > list. You're right, thanks for bringing this up! > Would it be possible to get

Re: [coreboot] F2A85-M - Richland CPU support doesn't work.

2016-01-28 14:22 GMT+01:00 Loic : > I have to apply the patch as an attachment for it to work. > I modify the options in Kconfig because coreboot doesn't start quickly > without this... Thank you. I pushed the patch to gerrit, split for CPU and mainboard:

Re: [coreboot] [RFC] Proposal for policy for changing the development guidelines

2016-01-30 15:26 GMT+01:00 Paul Menzel : > But then, I wondered why I was not aware of that section in the > development guidelines [2], and wanted to read up on it. While at it, I > also looked through the history, and there I see, that it was only > added [3]

Re: [coreboot] Linux kernel as payload?

2016-01-21 18:49 GMT+01:00 Kitestramuort : > Can I compile it 64bit? As long as you keep the 32bit entry point around, yes (which I think is the default configuration for x86_64 kernels). In kconfig/menuconfig/..., select a linux payload, and point to the bzImage file.

Re: [coreboot] [RFC] Common license header guideline should prefer GPLv2+ over GPLv2 only

2016-01-22 17:01 GMT+01:00 Alex G. : > so that GPLv3 projects (e.g. SeaBIOS) may take code from coreboot where needed They don't even accept code under BSD type licenses. Patrick -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und -nummer: Hamburg, HRB

Re: [coreboot] [RFC] Common license header guideline should prefer GPLv2+ over GPLv2 only

To add: 2016-01-22 17:01 GMT+01:00 Alex G. : > I think this would be a good move for interoperability, so that GPLv3 > projects (e.g. SeaBIOS) may take code from coreboot where needed (e.g. > device drivers). I'm strictly talking about listing the preferred > license; it's

Re: [coreboot] [RFC] Common license header guideline should prefer GPLv2+ over GPLv2 only

2016-01-22 17:25 GMT+01:00 Alex G. : > I'm not sure if you mean "something I'm uneasy about", or "an example > I'd consider" when you say "project that's based on 'or later'". u-boot > is v2+. Does that count? I'd recommend u-boot to standardize on a v2+ template, yes. (not

Re: [coreboot] Proposal - Fast Boot UEFI addendum to Coreboot

2016-02-14 8:32 GMT+01:00 Zoran Stojsavljevic : > [1] FSP 32 bit as is; That's probably best discussed with some Intel field rep for FSP. > [2] Coreboot to be 64 bit Coreboot, compiled for INTEL x86_64 architecture; The 64bit support was started, but I wouldn't

[coreboot] Summer of code: student application phase until Mar 25

Hi all, since we're accepted to be part of Google's Summer of Code 2016 programme, just a heads-up that students can now (until Mar 25) file their applications in the GSoC system: https://summerofcode.withgoogle.com/ Regards, Patrick -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg

Re: [coreboot] Regarding offset adjustment for building coreboot.

2016-04-08 11:17 GMT+02:00 Nico Huber : > you also stripped: > > fallback/payload 0x1b140payload 769955 > > I guess he means that a fresh build with a bigger (865KiB instead of > 752KiB) payload fails. Of course you're right. I misunderstood the

Re: [coreboot] Regarding offset adjustment for building coreboot.

2016-04-08 9:51 GMT+02:00 rajashaker Goud : > I have build coreboot with release payload. [ stripped to list only the empty regions] > Name Offset Type Size > (empty)0xd8380null 48152 >

Re: [coreboot] Alix 2d13 coreboot breaking source

Just to clarify: Did you rebuild the compilers after applying that commit? It doesn't touch anything that ends up affecting the coreboot binaries with a given toolchain. 2016-04-08 21:47 GMT+02:00 Reto Rayen : > Hi guys > > > > Finally i found out, which git commit broke

Re: [coreboot] Upstream coreboot on Broadwell/samus

2016-03-22 9:35 GMT+01:00 Huimin Zhang : > I was under the impression that coreboot support for the Broadwell > Chromebooks such as the new Chromebook Pixel was upstreamed but I am having > trouble getting it to work. Everything should be upstreamed, yes. However there isn't any

[coreboot] HEADS UP GSoC: students need to publish their proposals in the next ~30 hours

Hi all, if you're considering to apply for a project at this year's GSoC: Proposals need to be pushed into the system (summerofcode.withgoogle.com) within the next day or so ("ends 25 March, 2016 at 19:00 UTC" according to

Re: [coreboot] How to protect binary in flash chip? OTP?

2016-05-06 6:49 GMT+02:00 Persmule : > DRM methods cannot "protect" anything. They can only do harm to end users. That's an interesting statement for a political outreach discussion group (although the relevant activist groups probably beat that particular horse to death

Re: [coreboot] coreboot specific ACPI table

2016-04-18 19:09 GMT+02:00 Vadim Bendebury : > It's been a while since I looked at it, but why not to pass all > information through the coreboot table? (so that just one pointer > needs to be shared through ACPI). One reason for registering these things in ACPI is so that

Re: [coreboot] CBFS_HEADER_PTR_ADDR arch ARM

2016-04-14 19:00 GMT+02:00 daoud yessine : > For arch x86 , we have CBFS_HEADPTR_ADDR = 0xFFFC . > But for ARM systems what's the address of the cbfs header pointer ? > The header pointer is also at the top four bytes of the CBFS space, but note that it's on the

Re: [coreboot] Jenkins started giving Code-Review -1 on gerrit

2016-07-23 15:57 GMT+02:00 Jonathan Neuschäfer : > I noticed that the "build bot (Jenkins)" account on gerrit now gives a > Code-Review -1 mark for patches that don't build cleanly, in addition to > Verified -1. > > Is this intended? I find it confusing, because I thought

Re: [coreboot] How do I build Coreboot with both normal and fallback?

2016-08-05 11:56 GMT+02:00 Yaroslav K. : > Coreboot's bootblock_normal.c supports booting a fallback romstage if > a normal romstage > boot fails. But you can only specify either "fallback" or "normal" in > CONFIG_CBFS_PREFIX. > So how do I build an image with both normal and

Re: [coreboot] New Defects reported by Coverity Scan for coreboot

2016-08-09 11:23 GMT+02:00 : > 421 defect(s), reported by Coverity Scan earlier, were marked fixed in the > recent build analyzed by Coverity Scan. I wish it was that simple. Of those 421, maybe 10 are actually fixed, but the real reason for this steep dive is that our

Re: [coreboot] Passing CFLAGS to coreboot make (and reproducible builds)

Am 02.02.2017 8:39 nachm. schrieb "Trammell Hudson" : Is there a right way to pass additional compiler flags to the coreboot makefiles? Please add them as a test to util/xcompile/xcompile. We've been working on making the Heads firmware reproducible coreboot is normally

Re: [coreboot] Suggestions on shipping ARMv8 Chromebook

The just-released Chromebook Plus comes with an RK3399 SoC, which is ARMv8 and fully open at the AP firmware level (GPU is Mali with its usual issues, as well as Wifi firmware). Patrick 2017-02-17 15:49 GMT+01:00 : > Folks, > As we work on our own implementation we are

Re: [coreboot] Add coreboot storage driver

2017-02-14 17:12 GMT+01:00 Aaron Durbin via coreboot : > For an optimized bootflow > all pieces of work that need to be done pretty much need to be closely > coupled. One needs to globally optimize the full sequence. Like initializing slow hardware even before RAM init (as

Re: [coreboot] Add coreboot storage driver

2017-02-13 8:19 GMT+01:00 Andrey Petrov : > tl;dr: > We are considering adding early parallel code execution in coreboot. We need > to discuss how this can be done. It's reasonable to discuss the "if" first. > Nowadays we see firmware getting more complicated. The

Re: [coreboot] where to put info about linux payload and kgpe-d16

Am 30.09.2016 9:09 vorm. schrieb "Paul Menzel via coreboot" < coreboot@coreboot.org>: > If not, that means, if it’s also related to for example QEMU, I’d > create a page *Linux Payload* or so. Generic information about Linux payloads could also be put in documentation/ in the source tree as

Re: [coreboot] using overlayfs to have several coreboot dev envs

A more portable solution to the "big toolchain" problem is to store the toolchain outside the coreboot tree. Something like $ util/crossgcc/buildgcc -D $HOME/.xgcc Then add $HOME/.xgcc/bin to your PATH. Regards, Patrick 2016-11-13 21:34 GMT+01:00 Charlotte Plusplus

Re: [coreboot] Maintain boot order for multiple EFI based OS

Am 23.03.2017 08:10 schrieb "Matt DeVillier" : that seems like the kind of functionality it would make sense to handle in an abstracted way (perhaps using libpayload?) How about importing flashrom for this purpose? It has drivers for pretty much everything under the sun

Re: [coreboot] success with mecleaner and minnowmax turbot

Ron, thanks for the report. Did you also check if the ethernet port is still functional? 2017-03-23 18:55 GMT+01:00 ron minnich : > just an FYI, I was not sure where else to tell people. But the mecleaner > works! > > what a neat tool :-) > > -- > coreboot mailing list:

Re: [coreboot] Coreboot wiki: what license is the content under?

The wiki is mostly dead, its data mostly useless. Whatever we'll build as its replacement can start with a new, clear license system, and wiki content is either relicensed by its author and then ported over or deleted/rewritten. I'd go with CC-BY for the simple reason that documentation acts as

Re: [coreboot] How come the community meeting is hosted by proprietary software?

2017-03-17 15:50 GMT+01:00 Juliana Rodrigues : > that I know uses jitsi: https://meet.jit.si > It's MIT, but works very well. Thanks for the pointer. We already tried jitsi, but I think without the bridge service (which only seems to exist for about a year). So, something

Re: [coreboot] How come the community meeting is hosted by proprietary software?

2017-03-17 13:17 GMT+01:00 Dumitru Ursu : > Try Mumble - it worked without issues for me, but I never tried the web > interface. We did, it failed us. Patrick -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und -nummer: Hamburg, HRB 86891, Sitz der

[coreboot] Design discussions on gerrit

Hi, I just pushed https://review.coreboot.org/19242, which adds a document discussing mitigations for the ReBAR SMM attack Intel Security presented in January. I think we had a couple of people bringing it up on IRC and on the list, but these were relatively unstructured and nothing happened from

Re: [coreboot] Design discussions on gerrit

2017-04-12 4:17 GMT+02:00 taii...@gmx.com : > I was under the impression that coreboots native init boards disabled SMM > post-init and that this issue only applies to intel's FSP blobbed stuff, am > I incorrect? SMM is used on many boards, FSP or not, for tasks such as preparing

Re: [coreboot] USB HUB depth

2017-03-09 18:53 GMT+01:00 Joshua Pincus : > Enable_port() merely provides power to those ports. It doesn't scan them and > then attach them in any way. That happens on the next usb_poll(), which calls ->poll() for every device. In case of hubs, that's

Re: [coreboot] We need a place to hold the knowledge about the Manageability Engine.

2017-03-08 4:33 GMT+01:00 Persmule : > We believe that the knowledge about the ME has to be improved. Since the > maintenance of me.bios.io seems to be dropped, we may need a new centralized > place to hold such knowledge. > > Is it possible and convenient to set up a place

Re: [coreboot] About Paging, Realmode and what is going on

2017-07-31 10:52 GMT+02:00 Philipp Stanner : > 1. cb switches the CPU immediately to Protected Mode, yet Payloads like > seaBIOS work in Real Mode. Does coreboot switch the CPU always back to RM > before jumping to the payload? No, payloads are started in pmode. > 2. When CB

Re: [coreboot] About Paging, Realmode and what is going on

2017-07-31 14:46 GMT+02:00 Nico Huber : > No idea about the kernel's requirements Windows 7's kernel uses int10 calls for checking out various graphics properties, even when booting with UEFI (and therefore GOP drivers better put some int10 handler in the right place if

Re: [coreboot] About Paging, Realmode and what is going on

2017-08-02 21:08 GMT+02:00 Zoran Stojsavljevic : > And my question is: what for? Or I did not get the idea... Who really needs > to use paging in boot-loaders? Even INTEL, which (on purpose) makes things > way over-dimensioned and over-complicated, does NOT use

Re: [coreboot] x86 : Puzzles about reset code

2017-08-16 5:03 GMT+02:00 王翔 : > What is the meaning of hand coding? In 16-bit mode, the last two bytes are ignored. This is _very_ old code. Back in the day, before we started to strongly encourage people to use our compiler, we had to deal with tons of different versions of the

Re: [coreboot] Why I don't like links in commit messages and comments ...

2017-08-17 13:49 GMT+02:00 Peter Stuge : > Let's agree to disagree. Direct links are, well, direct; eliminating > an undesirable extra search step. Science today uses doi numbers/links, which plan for moves by addint indirection. > I think that broken links are a temporary problem

Re: [coreboot] Gerrit: Can't abandon patch

Hi Denis, there are two accounts of yours in Gerrit. Maybe you're logged in with one, and the CL was created with the other? Patrick 2017-07-13 23:21 GMT+02:00 Denis 'GNUtoo' Carikli : > Hi, > > In the (javascript) web interface, I find no way to abandon a change. > >

Re: [coreboot] Hi-DPI displays and showing text information for kevin in depthcharge

2017-07-16 11:32 GMT+02:00 Paul Kocialkowski : > So I am wondering what the best way to solve this would be. I see a few > options: > * Having larger fonts for hi-dpi displays > I'd go with that. Plus, maybe, a function to select the right font given a few constraints (display

Re: [coreboot] Hi-DPI displays and showing text information for kevin in depthcharge

I wouldn't scale at compile time (as said, storage constrained payloads might not be happy about that). I wouldn't scale each character up on each access though (we won't hardware accelerate the scaling, and yes, that does get slow - framebuffers aren't always the fastest type of memory and that

Re: [coreboot] Coreboot and INT13H

2017-07-19 23:24 GMT+02:00 ingegneriafore...@alice.it < ingegneriafore...@alice.it>: > 1- where (the name of the file) the INT 13H is implemented in the coreboot > source code ? > It's not. coreboot doesn't provide BIOS services. For those, see seabios ( www.seabios.org) > 2- if the INT 13H

Re: [coreboot] question on SMM

2017-06-30 19:46 GMT+02:00 ron minnich : > The only question that has been raised: are we losing an essential > security guarantee since flash is writeable in this kernel-based "SMM"? The > big question is whether we're opening up the possibility of firmware > getting changed,

Re: [coreboot] Intel ME The Way of the Static Analysis

Fun tidbit: The ME is running MINIX3 (confirmed by a file in the Google cache: http://webcache.googleusercontent.com/search?q=cache:tCcU0NRwTnQJ:ftp://ftp.supermicro.com/CDR-X11-UP_1.10_for_Intel_X11_UP_platform/Intel/ME/Other_Licenses/Minix3_License.txt+=1=de=clnk=de=lang_de%7Clang_en)

Re: [coreboot] Anyone got an opinion, technical or otherwise, on this?

Semi-Accurate only claims accuracy according to what's on the box. The official documentation of the issue can be found at https://security-center.intel.com/advisory.aspx?intelid=INTEL-SA-00075 It looks like a software bug in the AMT firmware. Therefore: - No AMT (eg on non-business consumer

[coreboot] Yet another gerrit update (2.14.1)

Hi everybody, I just updated our gerrit instance, which should fix a number of performance related regressions. Since there were requests for supporting ecdsa and ed25519 keys in gerrit's ssh interface, I also want to point out that 2.14 brought support for them. I didn't mention it because it

Re: [coreboot] CONFIG_CBFS_SIZE vs CONFIG_ROM_SIZE

We always add an FMAP now (think of it of a vendor neutral flash partition table), which resides outside CBFS. 2017-05-23 9:49 GMT-07:00 Gailu Singh : > Hi Experts, > > If we use CBFS_SIZE to be same as ROM_SIZE on our apollolake board grub > fails to load grub.cfg located in

[coreboot] Documentation on the website

Hi everybody, to elaborate a bit on what Martin reported from the community meeting: In the last few days I set up our server[0] to regularly render our repositories Documentation/ directory to https://www.coreboot.org/Documentation/, using hugo for formatting and conversion. The old

[coreboot] Gerrit update to 2.14

Hi everybody, I just updated Gerrit to 2.14, which brings some notable and user-visible changes that you might want to deal with: * There's a new UI based on Polymer. This will eventually replace the current GWT based UI but isn't complete yet. There's a "new/old UI" toggle near the end of the

Re: [coreboot] AMDPSP discussion

I hope y'all realize that you're preaching to the choir - and to the choir only? The folks making these weird decisions typically aren't signed onto such mailing lists. Patrick -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und -nummer: Hamburg, HRB 86891, Sitz der

Re: [coreboot] AMD EPYC and PSP

Since these discussions flare up time and time again (without ever being resolved in any productive way because the discussion happens in the wrong forum [0]): Netflix et al are (probably) required by their contracts with the content providers (producers, distributors) to make it reasonably hard

Re: [coreboot] 64 UEFI payload boot fail on Denverton platform but 32 UEFI payload works

2017-09-22 3:33 GMT+02:00 Melissa Yi : >Anyone can give some information? Probably not. 64bit tianocore as payload should work in general (since it still comes with a 32bit entry point, just switches to long mode really early). It's hard to tell what's going on if the

Re: [coreboot] greetings and laptop questions

Hi Youness, 2017-10-10 1:54 GMT+02:00 Youness Alaoui : > it uses FSP, but you fail to mention that anything using coreboot will > use the FSP unless it's 10 year old hardware (Sandybridge is the > latest FSP-free supported CPU). While I understand your

Re: [coreboot] Freedom Inside - certification system

2017-10-11 1:29 GMT+02:00 taii...@gmx.com : > I also propose a hardware-freedom-generic mailinglist be created for > philosophy debates, "should I buy X?", newbie questions etc moreso now that > TALOS 2 is in the picture the hardware freedom world is more than just > coreboot so I

Re: [coreboot] Moving the command line for Linux kernel payloads

2017-09-07 0:09 GMT+02:00 Trammell Hudson : > Is there a current or historical reason for the ordering? The reason for this order is that there had to be _some_ order. So go ahead and push the change for review, it looks reasonable. Thanks, Patrick -- Google Germany GmbH,

Re: [coreboot] [kernel-hardening] ME and PSP

Am 07.09.2017 20:03 schrieb "Timothy Pearson" < tpear...@raptorengineering.com>: -BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 09/07/2017 10:11 AM, Peter Stuge wrote: > ron minnich wrote: >> I don't think we can assume that an open, unlicensed instruction set >> guarantees open, unlicensed,

Re: [coreboot] util/cbfstool in coreboot master

It's used for the hashing features and pulled in by one of the submodules. Use `git submodule update --init` to pull in all of them (except blobs, which is disabled by default). 2017-08-21 10:55 GMT+02:00 John Lewis : > Hi Guys, > > Apparently, in coreboot master,

Re: [coreboot] util/cbfstool in coreboot master

Good call. I amended https://www.coreboot.org/Git to ask users to do `git clone --recurse-submodules` which will checkout the submodules as part of the download. 2017-08-21 11:07 GMT+02:00 John Lewis : > Thanks Patrick - is that written somewhere reasonably obvious that I

Re: [coreboot] util/cbfstool in coreboot master

2017-08-21 11:25 GMT+02:00 John Lewis : > Do you think there's something that could be also be done in > this regard on https://github.com/coreboot/coreboot (like customise the > message in the "clone or download" button? GitHub is not our platform, we're merely guests there

Re: [coreboot] [RFC] Successful build with GCC 7.2 and IASL 20170831 for coreboot 4.7

2017-10-06 9:43 GMT+02:00 Paul Menzel : > Having the code base compatible with future toolchains is quite > important and convenient in my opinion. That's a great argument to switch out the toolchain 4 months before a release. Which means 3.5 months ago. >

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