From: Christoph Müllner
We have two builtins which are undocumented and have no known users.
Further, they don't exist in LLVM (so are no portable).
This means they are in an unclear state of being supported or not.
Let's remove them get them out of this undecided state.
A discussion about
From: Christoph Müllner
stdint.h can be replaced with stdint-gcc.h to resolve some missing
system headers in non-multilib installations.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xtheadmemidx-helpers.h:
Replace stdint.h with stdint-gcc.h.
Signed-off-by: Christoph Müllner
From: Christoph Müllner
The XTheadFMemIdx tests set the required ABI for RV32, but not
for RV64, which has the effect that the tests are expected to
succeed for RV64/LP64. Let's set the ABI to LP64D in these
tests to clarify the requirements.
Signed-off-by: Christoph Müllner
From: Christoph Müllner
The XTheadMemIdx ISA extension provides a additional load and store
instructions with new addressing modes.
The following memory accesses types are supported:
* load: b,bu,h,hu,w,wu,d
* store: b,h,w,d
The following addressing modes are supported:
* immediate offset with
From: Christoph Müllner
The XTheadFMemIdx ISA extension provides additional load and store
instructions for floating-point registers with new addressing modes.
The following memory accesses types are supported:
* load/store: [w,d] (single-precision FP, double-precision FP)
The following
From: Christoph Müllner
The XTheadMemIdx ISA extension provides a additional load and store
instructions with new addressing modes.
The following memory accesses types are supported:
* load: b,bu,h,hu,w,wu,d
* store: b,h,w,d
The following addressing modes are supported:
* immediate offset with
From: Christoph Müllner
The XTheadFMemIdx ISA extension provides additional load and store
instructions for floating-point registers with new addressing modes.
The following memory accesses types are supported:
* load/store: [w,d] (single-precision FP, double-precision FP)
The following
From: Christoph Müllner
This two patches add support for the XTheadMemIdx
and XTheadFMemIdx ISA extensions, that support additional
addressing modes. The extensions are implemented in a range
of T-Head cores (e.g. C906, C910, C920) and are available
on the market for quite some time.
The ISA
From: Christoph Müllner
Fixes: c1bc7513b1d7 ("RISC-V: const: hide mvconst splitter from IRA")
A recent change broke the xtheadcondmov-indirect tests, because the order of
emitted instructions changed. Since the test is too strict when testing for
a fixed instruction order, let's change the
From: Christoph Müllner
Signed-off-by: Christoph Müllner
ChangeLog:
* MAINTAINERS: Add myself.
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index e9154878517..aa441de5332 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -576,6 +576,7 @@
From: Christoph Müllner
Fixes: c1bc7513b1d7 ("RISC-V: const: hide mvconst splitter from IRA")
A recent change broke the xtheadcondmov-indirect tests, because the order of
emitted instructions changed. Since the test is too strict when testing for
a fixed instruction order, let's change the
From: Christoph Müllner
We currently have two identical zero_extendhi2 patterns:
* '*zero_extendhi2_zbb'
* '*zero_extendhi2_bitmanip'
This patch removes the *_zbb pattern and ensures that all sign- and
zero-extensions use the postfix '_bitmanip'.
Signed-off-by: Christoph Müllner
From: Christoph Müllner
The mode attribute of an extension pattern is usually set to the target type.
Let's follow this convention consistently for xtheadbb.
Signed-off-by: Christoph Müllner
gcc/ChangeLog:
* config/riscv/thead.md: Use more appropriate mode attributes
for
From: Christoph Müllner
Recently three SPEC CPU 2017 benchmarks broke when using xtheadbb:
* 500.perlbench_r
* 525.x264_r
* 557.xz_r
Tracing the issue down revealed, that we emit a 'th.ext xN,xN,15,0'
for a extendqi insn, which is obviously wrong.
This patch splits the common 'extend2_th_ext'
From: Christoph Müllner
This patch implements the expansion of the strlen builtin for RV32/RV64
for xlen-aligned aligned strings if Zbb or XTheadBb instructions are available.
The inserted sequences are:
rv32gc_zbb (RV64 is similar):
add a3,a0,4
li a4,-1
.L1: lw
From: Christoph Müllner
This patch implements expansions for the cmpstrsi and cmpstrnsi
builtins for RV32/RV64 for xlen-aligned strings if Zbb or XTheadBb
instructions are available. The expansion basically emits a comparison
sequence which compares XLEN bits per step if possible.
This allows
From: Christoph Müllner
This series introduces strlen/strcmp/strncmp inline expansion for Zbb/XTheadBb.
In the last months, glibc as well as the Linux kernel merged changes for
optimized string processing for RISC-V. The instruction, which enables
optimized string routines is Zbb's orc.b (or
From: Christoph Müllner
The test was introduced recently and tests a RV64-only feature.
However, when testing an RV32 compiler, the test gets executed as well
and fails with "cc1: error: ABI requires '-march=rv32'".
This patch fixes this by adding '-mabi=lp64' (like it is done for
other
From: Christoph Müllner
Some constants can be built up using LI+RORI instructions.
The current implementation requires one of the upper 32-bits
to be a zero bit, which is not neccesary.
Let's drop this requirement in order to be able to synthesize
a constant like 0x00ffL.
The tests
From: Christoph Müllner
Some constants can be built up using rotate-right instructions.
The code that enables this can be found in riscv_build_integer_1().
However, this functionality is only available for Zbb, which
includes the rori instruction. This patch enables this also for
XTheadBb,
From: Christoph Müllner
Recently, these xtheadcondmov tests regressed with -Oz:
* FAIL: gcc.target/riscv/xtheadcondmov-mveqz-imm-eqz.c
* FAIL: gcc.target/riscv/xtheadcondmov-mveqz-imm-not.c
* FAIL: gcc.target/riscv/xtheadcondmov-mvnez-imm-cond.c
* FAIL:
From: Christoph Müllner
The variable `regno` is currently not used in riscv_regno_ok_for_index_p(),
which triggers a compiler warning. Let's address this.
Fixes: 423604278ed5 ("riscv: Prepare backend for index registers")
Reported-by: Juzhe Zhong
Reported-by: Andreas Schwab
Signed-off-by:
From: Christoph Müllner
Recently, two identical XTheadCondMov tests have been added, which both fail.
Let's fix that by changing the following:
* Merge both files into one (no need for separate tests for rv32 and rv64)
* Drop unrelated attribute check test (we already test for `th.mveqz`
and
From: Christoph Müllner
This series adds basic support for the vector crypto extensions:
* Zvbb
* Zvbc
* Zvkg
* Zvkned
* Zvkhn[a,b]
* Zvksed
* Zvksh
* Zvkn
* Zvknc
* Zvkng
* Zvks
* Zvksc
* Zvksg
* Zvkt
This patch is based on the v20230620 version of the Vector Cryptography
specification. The
From: Christoph Müllner
The XTheadMemIdx ISA extension provides a additional load and store
instructions with new addressing modes.
The following memory accesses types are supported:
* ltype = [b,bu,h,hu,w,wu,d]
* stype = [b,h,w,d]
The following addressing modes are supported:
* immediate
From: Christoph Müllner
The XTheadFMemIdx ISA extension provides additional load and store
instructions for floating-point registers with new addressing modes.
The following memory accesses types are supported:
* ftype = [w,d] (single-precision, double-precision)
The following addressing modes
From: Christoph Müllner
RISC-V does currently not support index registers.
However, there are some vendor extensions that specify them.
Let's do the necessary changes in the backend so that we can
add support for such a vendor extension in the future.
This is a non-functional change without any
From: Christoph Müllner
There is an incorrect sentence in the documentation of the function
th_mempair_order_operands(). Let's remove it.
gcc/ChangeLog:
* config/riscv/thead.cc (th_mempair_operands_p):
Fix documentation of th_mempair_order_operands().
Signed-off-by: Christoph
From: Christoph Müllner
This patch moves the XThead*-specific peephole passes
into thead-peephole.md with the intend to keep vendor-specific
code separated from RISC-V standard code.
This patch does not contain any functional changes.
gcc/ChangeLog:
* config/riscv/peephole.md: Remove
From: Christoph Müllner
Define a Xmode macro that specifies the registers size (XLEN)
similar to Pmode. This allows the backend code to write generic
RV32/RV64 C code (under certain circumstances).
gcc/ChangeLog:
* config/riscv/riscv.h (Xmode): New macro.
Signed-off-by: Christoph
From: Christoph Müllner
enum riscv_address_type and struct riscv_address_info are used
to store address classification information. Let's move this types
into our common header file in order to share them with other
compilation units.
This is a non-functional change without any intendet
From: Christoph Müllner
The current implementation triggers an assertion in
dwarf2out_frame_debug_cfa_offset() under certain circumstances.
The standard code uses REG_FRAME_RELATED_EXPR notes instead
of REG_CFA_OFFSET notes when saving registers on the stack.
So let's do this as well.
From: Christoph Müllner
A recent change adjusted the constraints of ZBA's shNadd INSN.
Let's mirror this change here as well.
gcc/ChangeLog:
* config/riscv/thead.md: Adjust constraints of th_addsl.
Signed-off-by: Christoph Müllner
---
gcc/config/riscv/thead.md | 5 ++---
1 file
From: Christoph Müllner
We have the following situation for MEM RTX objects:
* TARGET_PRINT_OPERAND expands to riscv_print_operand()
* This falls into the default case (unknown or on letter) of the outer
switch-case-block and the MEM case of the inner switch-case-block and
calls
From: Christoph Müllner
The current support of the bitfield-extraction instructions
th.ext and th.extu (XTheadBb extension) only covers sign_extract
and zero_extract. This patch add support for sign_extend and
zero_extend to avoid any shifts for sign or zero extensions.
gcc/ChangeLog:
From: Christoph Müllner
This series improves the support for the XThead* ISA extensions
which are available e.g. on the T-Head XuanTie C906.
The ISA spec can be found here:
https://github.com/T-head-Semi/thead-extension-spec
So far the following extension support has been merged in GCC:
*
From: Christoph Müllner
This patch adds missing mode specifiers for XTheadMemPair INSNs.
gcc/ChangeLog:
PR target/109296
* config/riscv/thead.md: Add missing mode specifiers.
Signed-off-by: Christoph Müllner
---
gcc/config/riscv/thead.md | 16
1 file changed,
From: Christoph Müllner
The current support of the bitfield-extraction instructions
th.ext and th.extu (XTheadBb extension) only covers sign_extract
and zero_extract. This patch add support for sign_extend and
zero_extend to avoid any shifts for sign or zero extensions.
gcc/ChangeLog:
From: Christoph Müllner
The XTheadMemPair ISA extension allows to pair two loads or stores:
* th.ldd (2x LD)
* th.lwd (2x LW)
* th.lwud (2x LWU)
* th.sdd (2x SD)
* th.swd (2x SW)
The displacement of these instructions is quite limited:
* Displacement := imm2 << shamt
* imm2 is a 2-bit unsigned
From: Christoph Müllner
The XTheadMac ISA extension provides multiply-accumulate/subtract
instructions:
* mula/mulaw/mulah
* muls/mulsw/mulsh
To benefit from middle-end passes, we expand the following named
patterns in riscv.md (as they are not T-Head-specific):
* maddhisi4
* msubhisi4
From: Christoph Müllner
The XTheadFmv ISA extension provides instructions to move
data between 32-bit GP registers and 64-bit FP registers.
gcc/ChangeLog:
* config/riscv/constraints.md (TARGET_XTHEADFMV ? FP_REGS : NO_REGS)
New constraint "th_f_fmv".
(TARGET_XTHEADFMV ?
From: Christoph Müllner
This patch adds support for XTheadCondMov ISA extension.
The extension brings a one-sided conditional move (no else-assignment).
Given that GCC has a great if-conversion pass, we don't need to do much,
besides properly expanding movcc accordingly and adjust the cost
From: Christoph Müllner
This patch adds support for the XTheadBb ISA extension.
Thus, there is a functional overlap of the new instructions with
existing Bitmanip instruction, which allows a good amount of code
sharing. However, the vendor extensions are cleanly separated from
the standard
From: Christoph Müllner
This patch adds support for the XTheadBa ISA extension.
The new INSN pattern is defined in a new file to separate
this vendor extension from the standard extensions.
gcc/ChangeLog:
* config/riscv/riscv.md: Include thead.md
* config/riscv/thead.md: New
From: Christoph Müllner
This patch adds support for the XTheadBs ISA extension.
The new INSN pattern is defined in a new file to separate
this vendor extension from the standard extensions.
The cost model adjustment reuses the xbs:bext cost.
gcc/ChangeLog:
* config/riscv/riscv.cc
From: Christoph Müllner
This adds T-Head's XuanTie C906 to the list of known cores as "thead-c906".
The C906 is shipped for quite some time (it is the core of the Allwinner D1).
Note, that the tuning struct for the C906 is already part of GCC (it is
also name "thead-c906").
gcc/ChangeLog:
From: Christoph Müllner
This patch add basic support for the following XThead* ISA extensions:
* XTheadBa
* XTheadBb
* XTheadBs
* XTheadCmo
* XTheadCondMov
* XTheadFMemIdx
* XTheadFmv
* XTheadInt
* XTheadMac
* XTheadMemIdx
* XTheadMemPair
* XTheadSync
The extensions are just recognized by the
From: Christoph Müllner
This series introduces support for the T-Head specific RISC-V ISA extensions
which are available e.g. on the T-Head XuanTie C906.
The ISA spec can be found here:
https://github.com/T-head-Semi/thead-extension-spec
This series adds support for the following XThead*
From: Christoph Müllner
This patch documents the new T-Head CPU support for RISC-V.
Signed-off-by: Christoph Müllner
---
htdocs/gcc-13/changes.html | 24 +++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/htdocs/gcc-13/changes.html
From: "moiz.hussain"
The XTheadMemIdx ISA extension provides a additional addressing
modes to load and store instructions:
* increment after
* increment before
* register indexed
gcc/ChangeLog:
* config/riscv/constraints.md (Qmb): New constraint.
(Qma): Likewise.
(Qmr):
From: Christoph Müllner
The XTheadMemPair ISA extension allows to pair two loads or stores:
* th.ldd (2x LD)
* th.lwd (2x LW)
* th.lwud (2x LWU)
* th.sdd (2x SD)
* th.swd (2x SW)
The displacement of these instructions is quite limited:
* Displacement := imm2 << shamt
* imm2 is a 2-bit unsigned
From: Christoph Müllner
The XTheadFmv ISA extension provides instructions to move
data between 32-bit GP registers and 64-bit FP registers.
gcc/ChangeLog:
* config/riscv/constraints.md (TARGET_XTHEADFMV ? FP_REGS : NO_REGS)
New constraint "th_f_fmv".
(TARGET_XTHEADFMV ?
From: "moiz.hussain"
The XTheadFMemIdx ISA extension provides register-indexed
addressing modes to floating-point load and store instructions.
gcc/ChangeLog:
* config/riscv/constraints.md (Qmx): New constraint.
* config/riscv/riscv-protos.h (riscv_output_move_index_float):
From: Christoph Müllner
This patch adds support for the XTheadBa ISA extension.
The new INSN pattern is defined in a new file to separate
this vendor extension from the standard extensions.
gcc/ChangeLog:
* config/riscv/riscv.md: Include thead.md
* config/riscv/thead.md: New
From: Christoph Müllner
This patch adds support for XTheadCondMov ISA extension.
The extension brings a one-sided conditional move (no else-assignment).
Given that GCC has a great if-conversion pass, we don't need to do much,
besides properly expanding movcc accordingly and adjust the cost
From: Christoph Müllner
This patch adds support for the XTheadBb ISA extension.
Thus, there is a functional overlap of the new instructions with
existing Bitmanip instruction, which allows a good amount of code
sharing. However, the vendor extensions are cleanly separated from
the standard
From: Christoph Müllner
The XTheadMac ISA extension provides multiply-accumulate/subtract
instructions:
* mula/mulaw/mulah
* muls/mulsw/mulsh
To benefit from middle-end passes, we expand the following named
patterns in riscv.md (as they are not T-Head-specific):
* maddhisi4
* msubhisi4
From: Christoph Müllner
This series introduces support for the T-Head specific RISC-V ISA extensions
which are available e.g. on the T-Head XuanTie C906.
The ISA spec can be found here:
https://github.com/T-head-Semi/thead-extension-spec
This series adds support for the following XThead*
From: Christoph Müllner
This adds T-Head's XuanTie C906 to the list of known cores as "thead-c906".
The C906 is shipped for quite some time (it is the core of the Allwinner D1).
Note, that the tuning struct for the C906 is already part of GCC (it is
also name "thead-c906").
gcc/ChangeLog:
From: Christoph Müllner
This patch adds support for the XTheadBs ISA extension.
The new INSN pattern is defined in a new file to separate
this vendor extension from the standard extensions.
The cost model adjustment reuses the xbs:bext cost.
gcc/ChangeLog:
* config/riscv/riscv.cc
From: Christoph Müllner
This patch add basic support for the following XThead* ISA extensions:
* XTheadBa
* XTheadBb
* XTheadBs
* XTheadCmo
* XTheadCondMov
* XTheadFMemIdx
* XTheadFmv
* XTheadInt
* XTheadMac
* XTheadMemIdx
* XTheadMemPair
* XTheadSync
The extensions are just recognized by the
From: Christoph Müllner
This series adds basic support for the vector crypto extensions:
* Zvkb
* Zvkg
* Zvkh[a,b]
* Zvkn
* Zvksed
* Zvksh
The implementation follows the version 20221220 of the specification,
which can be found here:
From: "moiz.hussain"
The XTheadMemPair ISA extension provides load/store pair instructions:
* th.ldd
* th.sdd
* th.lwd
* th.lwud
* th.swd
This patch adds the following unnamed patterns to the peephole.md stage,
which take care of reordering loads/stores appropriately:
* load/store pair patterns
From: Christoph Müllner
The XTheadFmv ISA extension provides instructions to move
data between 32-bit GP registers and 64-bit FP registers.
gcc/ChangeLog:
* config/riscv/constraints.md (TARGET_XTHEADFMV ? FP_REGS : NO_REGS)
New constraint "th_f_fmv".
(TARGET_XTHEADFMV ?
From: Christoph Müllner
The XTheadMac ISA extension provides multiply-accumulate/subtract
instructions:
* mula/mulaw/mulah
* muls/mulsw/mulsh
To benefit from middle-end passes, we expand the following named
patterns in riscv.md (as they are not T-Head-specific):
* maddhisi4
* msubhisi4
From: Christoph Müllner
This patch adds support for XTheadCondMov ISA extension.
The extension brings a one-sided conditional move (no else-assignment).
Given that GCC has a great if-conversion pass, we don't need to do much,
besides properly expanding movcc accordingly and adjust the cost
From: Christoph Müllner
This patch adds support for the XTheadBa ISA extension.
The new INSN pattern is defined in a new file to separate
this vendor extension from the standard extensions.
gcc/ChangeLog:
* config/riscv/riscv.md: Include thead.md
* config/riscv/thead.md: New
From: Christoph Müllner
This patch add basic support for the following XThead* ISA extensions:
* XTheadBa
* XTheadBb
* XTheadBs
* XTheadCmo
* XTheadCondMov
* XTheadFMemIdx
* XTheadFmv
* XTheadInt
* XTheadMac
* XTheadMemIdx
* XTheadMemPair
* XTheadSync
The extensions are just recognized by the
From: Christoph Müllner
This patch adds support for the XTheadBb ISA extension.
Thus, there is a functional overlap of the new instructions with
existing Bitmanip instruction, which allows a good amount of code
sharing. However, the vendor extensions are cleanly separated from
the standard
From: Christoph Müllner
This patch adds support for the XTheadBs ISA extension.
The new INSN pattern is defined in a new file to separate
this vendor extension from the standard extensions.
The cost model adjustment reuses the xbs:bext cost.
gcc/ChangeLog:
* config/riscv/riscv.cc
From: Christoph Müllner
This adds T-Head's XuanTie C906 to the list of known cores as "thead-c906".
The C906 is shipped for quite some time (it is the core of the Allwinner D1).
Note, that the tuning struct for the C906 is already part of GCC (it is
also name "thead-c906").
gcc/ChangeLog:
From: Christoph Müllner
This patch restructures the loop over the GP registers
which saves/restores then as part of the prologue/epilogue.
No functional change is intended by this patch, but it
offers the possibility to use load-pair/store-pair instructions.
gcc/ChangeLog:
*
From: Christoph Müllner
This series introduces support for the T-Head specific RISC-V ISA extensions
which are available e.g. on the T-Head XuanTie C906.
The ISA spec can be found here:
https://github.com/T-head-Semi/thead-extension-spec
The series begins with two preparation patches, that
From: Christoph Müllner
The comment above the enumeration of existing attributes got out of
order and a few entries were forgotten.
This patch synchronizes the comments according to the list.
This commit does not include any functional change.
gcc/ChangeLog:
* config/riscv/riscv.md:
From: Christoph Müllner
This patch adds support for the two AIA ISA extensions Ssaia and Smaia.
They are not relelvant for the compiler, but the assembler might want
to validate the CSRs. Therefore, all this patch does is recognize the
extension name, emit a feature macro (incl. a test).
From: Christoph Müllner
This patch adds support for the two AIA ISA extensions Ssaia and Smaia.
They are not relelvant for the compiler, but the assembler might want
to validate the CSRs. Therefore, all this patch does is recognize the
extension name, emit a feature macro (incl. a test).
From: Christoph Müllner
This patch fixes a wrong placed closing bracket in the RISC-V option
list and an unneeded @gol in the PRU option list in invoke.texi.
gcc/ChangeLog:
* doc/invoke.texi: Fix PRU/RISC-V option list formatting.
Signed-off-by: Christoph Müllner
---
From: Christoph Müllner
This patch fixes a wrong placed closing bracket in the RISC-V section of
invoke.texi.
gcc/ChangeLog:
* doc/invoke.texi: Fix closing block bracket
Signed-off-by: Christoph Müllner
---
gcc/doc/invoke.texi | 4 ++--
1 file changed, 2 insertions(+), 2
From: Christoph Müllner
This patch implements expansions for the cmpstrsi and the cmpstrnsi
builtins using Zbb instructions (if available).
This allows to inline calls to strcmp() and strncmp().
The expansion basically emits a peeled comparison sequence (i.e. a peeled
comparison loop) which
From: Christoph Müllner
This patch implements the expansion of the strlen builtin
using Zbb instructions (if available) for aligned strings
using the following sequence:
li a3,-1
addia4,a0,8
.L2: ld a5,0(a0)
addia0,a0,8
orc.b a5,a5
beq
From: Christoph Müllner
Let's try to not accumulate too much functionality in one single file
as this does not really help maintaining or extending the code.
So in order to add more similar functionality like riscv_block_move_loop
let's move this function to a separate file.
This change does
From: Christoph Müllner
INSNs are usually postfixed by a number representing the argument count.
Given the instructions will be used in a later commit, let's make them
visible, but add a "riscv_" prefix to avoid conflicts with standard
INSNs.
gcc/ChangeLog:
* config/riscv/bitmanip.md
From: Philipp Tomsich
As a basis for optimized string functions (e.g., the by-pieces
implementations), we need orc.b available. This adds orc.b as an
unspec, so we can expand to it.
gcc/ChangeLog:
* config/riscv/bitmanip.md (orcb2): Add orc.b as an
unspec.
*
From: Christoph Müllner
This patchset adds includes patches to improve the following builtin
expansions:
* cpymemsi: Allow by-pieces to generate overlapping memory accesses
* cmpstrsi: Add expansion for strcmp and strncmp for aligned strings when
zbb/orc.b is available
* strlen: Add expansion
From: Christoph Müllner
The current implementation of riscv_block_move_straight() emits a couple
of load-store pairs with maximum width (e.g. 8-byte for RV64).
The remainder is handed over to move_by_pieces(), which emits code based
target settings like slow_unaligned_access and
From: Christoph Müllner
This patch adds the field overlap_op_by_pieces to the struct
riscv_tune_param, which allows to enable the overlap_op_by_pieces
infrastructure.
gcc/ChangeLog:
* config/riscv/riscv.c (struct riscv_tune_param): New field.
(riscv_overlap_op_by_pieces): New
From: "moiz.hussain"
The XTheadMacXTheadMemPair ISA extension provides load/store
pair instructions:
* th.ldd
* th.sdd
* th.lwd
* th.lwud
* th.swd
We added the following unnamed patterns to the
peephole.md stage:
* load/store pair patterns for 4 instructions
* load/store pair patterns for 2
From: Christoph Müllner
The XTheadMac ISA extension provides multiply-accumulate/subtract
instructions:
* mula/mulaw/mulah
* muls/mulsw/mulsh
To benefit from middle-end passes, we expand the following named
patterns in riscv.md (as they are not T-Head-specific):
* maddhisi4
* msubhisi4
From: Christoph Müllner
This patch add basic support for the XTheadFmv and XTheadInt
ISA extension. As both extensions only contain instruction,
which are not supposed to be emitted by the compiler, the support
only covers awareness of the extension name in the march string
and the definition of
From: Christoph Müllner
The XTheadBb ISA extension provides instructions similar to Zbb:
* th.srri/th.srriw
* th.ext/th.extu
* th.ff1 (count-leading-zeros)
* th.rev/th.revw
Instructions that are not covered, because they don't fit into a
pattern:
* th.ff0 (count-leading-ones)
* th.tstnbz
For
From: Christoph Müllner
This patch adds support for the following T-Head vendor extensions:
* XTheadBa
* XTheadBs
Both extensions provide just one instruction, that has a counterpart
in the similar named Bitmanip ISA extension.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_rtx_costs):
From: Christoph Müllner
This patch adds support for XTheadCondMov ISA extension.
The extension brings a one-sided conditional move (no else-assignment).
Given that GCC has a great if-conversion pass, we don't need to do much,
besides properly expanding movcc accordingly and adjust the cost
From: Christoph Müllner
This series adds support for the following vendor extensions
from T-Head:
* XTheadCmo, XTheadSync
* XTheadBa, XTheadBb, XTheadBs
* XTheadCondMov
* XTheadMac
* XTheadFmv, XTheadInt
No regressions observed.
Christoph Müllner (7):
riscv: Add basic XThead* vendor
From: Christoph Müllner
This patch add basic support for the following XThead* ISA extensions:
* XTheadCmo, XTheadSync
* XTheadBa, XTheadBb, XTheadBs, XTheadCondMov
* XTheadMac
* XTheadFMemIdx, XTheadMemIdx
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add xthead* extensions.
From: Christoph Müllner
This adds T-Head's XuanTie C906 to the list of known cores as "thead-c906".
The C906 is shipped for quite some time (it is the core of the Allwinner D1).
Note, that the tuning struct for the C906 is already part of GCC (it is
also name "thead-c906").
gcc/ChangeLog:
From: mtsamis
The IPA CP pass offers a wide range of optimizations, where most of them
lead to specialized functions that are called from a call site.
This can lead to multiple specialized function clones, if more than
one call-site allows such an optimization.
If not all call-sites can be
f.cc b/gcc/ipa-guarded-deref.cc
new file mode 100644
index 000..198fb9b33ad
--- /dev/null
+++ b/gcc/ipa-guarded-deref.cc
@@ -0,0 +1,1115 @@
+/* IPA pass to transform indirect calls to guarded direct calls.
+ Copyright (C) 2022 Free Software Foundation, Inc.
+ Contributed by Christop
From: Christoph Müllner
This patch documents the new RISC-V Zawrs support.
Signed-off-by: Christoph Müllner
---
htdocs/gcc-13/changes.html | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html
index 7c6bfa6e..5e6e054b
From: Christoph Muellner
This patch adds support for the Zawrs ISA extension.
The patch depends on the corresponding Binutils patch
to be usable (see [1])
The specification can be found here:
https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc
Note, that the Zawrs extension is not frozen
From: Christoph Müllner
This adds T-Head's XuanTie C906 to the list of known cores as "thead-c906".
The C906 is shipped for quite some time (it is the core of the Allwinner D1).
Note, that the tuning struct for the C906 is already part of GCC (it is
also name "thead-c906").
gcc/ChangeLog:
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