This is continuing on the prev patch in function epilogue expansion.
Broken out of easy of review.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_expand_epilogue): Handle offset
being sum of two S12.
Tested-by: Patrick O'Neill # pre-commit-CI #1569
Signed-off-by: Vineet Gupta
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/riscv-protos.h | 2 +
gcc/config/riscv/riscv.cc | 54 +--
gcc/config/riscv/riscv.h | 7 +++
gcc/testsuite/gcc.target/riscv/pr105733.c | 15 ++
.../riscv/rvv/autovec/vls
On 5/20/24 20:54, Jeff Law wrote:
> On 5/20/24 5:32 PM, Vineet Gupta wrote:
>> This is testsuite clean however there's a dwarf quirk which I want to
>> run by the experts. The test that was tripping CI has following
>> fragment:
>>
>> Before pat
offset 2032 <- #3
The dwarf insn #1 and #3 seem ok, however #2 seems dubious to me.
---
This is continuing on the prev patch in function epilogue expansion.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_expand_epilogue): Handle offset
being sum of two S12.
Signed-off-by: Vin
.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/spill-7.c: Ditto.
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/riscv-protos.h | 2 +
gcc/config/riscv/riscv.cc | 54 +--
gcc/config/riscv/riscv.h | 7 +++
gcc
On 5/14/24 08:44, Jeff Law wrote:
>>> I was able to find the summary info:
>>>
Tests that now fail, but worked before (15 tests):
libgomp: libgomp.fortran/simd7.f90 -O0 execution test
libgomp: libgomp.fortran/task2.f90 -O0 execution test
libgomp: libgomp.fortran/vla2.f90
On 5/15/24 12:32, Jeff Law wrote:
>
> On 5/15/24 12:55 PM, Vineet Gupta wrote:
>> Saw this little room for improvement in current debugging of
>> prologue/epilogue expansion code.
>>
>> ---
>>
>> Use the following pattern consistently
>> `RTX
): Ditto.
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/riscv.cc | 54 ++-
1 file changed, 25 insertions(+), 29 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 4067505270e1..6d95e2d41e87 100644
--- a/gcc/config/riscv
On 5/14/24 15:12, Palmer Dabbelt wrote:
> On Mon, 13 May 2024 16:08:21 PDT (-0700), Vineet Gupta wrote:
>>
>> On 5/13/24 15:47, Jeff Law wrote:
>>>> On 5/13/24 11:49, Vineet Gupta wrote:
>>>>> 500.perlbench_r-0 | 1,214,534,029,025 | 1,2
et/riscv/sum-of-two-s12-const-3.c: New test: should not
ICE.
Tested-by: Edwin Lu # pre-commit-CI #1520
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/constraints.md | 6 +++
gcc/config/riscv/predicates.md| 6 +++
gcc/config/riscv/riscv-protos.h | 1 +
On 5/14/24 08:44, Jeff Law wrote:
> On 5/14/24 8:51 AM, Patrick O'Neill wrote:
>>> I was able to find the summary info:
>>>
Tests that now fail, but worked before (15 tests):
libgomp: libgomp.fortran/simd7.f90 -O0 execution test
libgomp: libgomp.fortran/task2.f90 -O0
On 5/13/24 15:47, Jeff Law wrote:
>> On 5/13/24 11:49, Vineet Gupta wrote:
>>> 500.perlbench_r-0 | 1,214,534,029,025 | 1,212,887,959,387 |
>>> 500.perlbench_r-1 |740,383,419,739 | 739,280,308,163 |
>>> 500.perlbench_r-2 |692,074,638,817 | 69
On 5/13/24 11:49, Vineet Gupta wrote:
> 500.perlbench_r-0 | 1,214,534,029,025 | 1,212,887,959,387 |
> 500.perlbench_r-1 |740,383,419,739 | 739,280,308,163 |
> 500.perlbench_r-2 |692,074,638,817 | 691,118,734,547 |
> 502.gcc_r-0 |190,820,141,435 | 190
On 2/27/24 07:25, Jeff Law wrote:
> On 2/25/24 21:53, Greg McGary wrote:
>> Add option -m(no-)autovec-segment to enable/disable autovectorizer
>> from emitting vector segment load/store instructions. This is useful for
>> performance experiments.
>>
>> gcc/ChangeLog:
>> *
m-of-two-s12-const-3.c: New test: should not
ICE.
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/constraints.md | 6 +++
gcc/config/riscv/predicates.md| 6 +++
gcc/config/riscv/riscv-protos.h | 1 +
gcc/config/riscv/riscv.cc
.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/spill-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/spill-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/spill-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/spill-7.c: Ditto.
Signed-off-by: Vineet Gupta
---
gcc/config
have a few follow-ups which I come back to seperately.
Thx,
-Vineet
[1] https://gcc.gnu.org/pipermail/gcc-patches/2024-March/647874.html
Vineet Gupta (2):
RISC-V: avoid LUI based const materialization ... [part of PR/106265]
RISC-V: avoid LUI based const mat in prologue/epilogue expansion
On 5/6/24 13:40, Christoph Müllner wrote:
> The combiner attempts to optimize a zero-extension of a logical right shift
> using zero_extract. We already utilize this optimization for those cases
> that result in a single instructions. Let's add a insn_and_split
> pattern that also matches the
On 5/3/24 01:26, Segher Boessenkool wrote:
> On Thu, May 02, 2024 at 11:59:24AM -0700, Vineet Gupta wrote:
>> This is no logic change (but technically still a functional change).
> Where are 1/3 and 2/3? Or are those unrelated?
Yes they were unrelated (minor doc fixes) hence
gcc/ChangeLog:
* config/riscv/riscv.cc: Comment updates.
* config/riscv/riscv.h: Ditto.
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/riscv.cc | 6 --
gcc/config/riscv/riscv.h | 2 +-
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv
gcc/ChangeLog
* doc/rtl.texi: Add entry for GET_MODE_INNER.
Signed-off-by: Vineet Gupta
---
gcc/doc/rtl.texi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/gcc/doc/rtl.texi b/gcc/doc/rtl.texi
index 8ea6588cb71f..aa10b5235b53 100644
--- a/gcc/doc/rtl.texi
+++ b/gcc/doc
gcc/ChangeLog
* doc/rtl.texi: Add entry for GET_MODE_INNER.
Signed-off-by: Vineet Gupta
---
gcc/doc/rtl.texi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/gcc/doc/rtl.texi b/gcc/doc/rtl.texi
index 8ea6588cb71f..aa10b5235b53 100644
--- a/gcc/doc/rtl.texi
+++ b/gcc/doc
On 5/2/24 13:38, Jeff Law wrote:
>
> On 5/2/24 12:59 PM, Vineet Gupta wrote:
>> This is no logic change (but technically still a functional change).
>>
>> Ran into this when stepping thru combine code.
>> @newpat has some random garbage for a bit until it is
Hi,
Spring cleaning of a really old branch.
stage1 might be the right time to get them in.
Thx,
-Vineet
Vineet Gupta (3):
docs: rtl: document GET_MODE_INNER
RISC-V: miscll comment fixes [NFC]
combine: initialize a local var
gcc/combine.cc| 2 +-
gcc/config/riscv/riscv.cc | 6
newpat.
CC: Segher Boessenkool
Signed-off-by: Vineet Gupta
---
gcc/combine.cc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/combine.cc b/gcc/combine.cc
index 92b8d98e6c15..0b5fe00c8c5b 100644
--- a/gcc/combine.cc
+++ b/gcc/combine.cc
@@ -2522,7 +2522,7 @@ try_combine
gcc/ChangeLog
* doc/rtl.texi: Add entry for GET_MODE_INNER.
Signed-off-by: Vineet Gupta
---
gcc/doc/rtl.texi | 4
1 file changed, 4 insertions(+)
diff --git a/gcc/doc/rtl.texi b/gcc/doc/rtl.texi
index 8ea6588cb71f..f1643f41dfc6 100644
--- a/gcc/doc/rtl.texi
+++ b/gcc/doc/rtl.texi
gcc/ChangeLog:
* config/riscv/riscv.cc: Comment updates.
* config/riscv/riscv.h: Ditto.
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/riscv.cc | 6 --
gcc/config/riscv/riscv.h | 2 +-
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv
On 4/24/24 12:22, Robin Dapp wrote:
> The dynamic icounts looks sane (vs. Apr 10 snapshot) except for a
>> regression in x264 which is likely independent of the chaos going on.
>>
>> Apr 10 | Apr 23 |
>> 109f1b28fc94 | 6f0a646dd2fc |
>>
Hi,
Per discussion in patchworks call yesterday I gave the trunk snapshot a
spin for SPEC2017 build/runs on QEMU (usual flags -Ofast -flto=auto,
-march=rv64gcv_zba_zbb_zbs_zicond)
2024-04-23 6f0a646dd2fc Remove repeated information in
-ftree-loop-distribute-patterns doc
The dynamic
/ChangeLog:
* gcc.target/riscv/rvv/vtype-call-clobbered.c: New Test.
Signed-off-by: Vineet Gupta
---
.../riscv/rvv/vtype-call-clobbered.c | 47 +++
1 file changed, 47 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vtype-call-clobbered.c
diff --git
/rvv/vtype-call-clobbered.c: New Test.
Signed-off-by: Vineet Gupta
---
.../riscv/rvv/vtype-call-clobbered.c | 47 +++
1 file changed, 47 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vtype-call-clobbered.c
diff --git a/gcc/testsuite/gcc.target
On 3/22/24 05:29, Jeff Law wrote:
>> Another option is to enable -fsched-pressure which should help with
>> this issue.
> In theory we're already using that by default -- it's part of what makes
> me so curious to understand what's going on.
We are actually using it in practice :-)
Its the
On 3/21/24 12:56, Jeff Law wrote:
>
> On 3/21/24 11:19 AM, Vineet Gupta wrote:
>
>>> So if we go back to Robin's observation that scheduling dramatically
>>> increases the instruction count, perhaps we try a run with
>>> -fno-schedule-insns -fno-schedul
On 3/21/24 07:45, Jeff Law wrote:
The first patch is the main change which improves SPEC cactu by 10%.
>>> Just to confirm. Yup, 10% reduction in icounts and about a 3.5%
>>> improvement in cycles on our target. Which is great!
>>>
>>> This also makes me wonder if cactu is the benchmark
On 3/18/24 21:41, Jeff Law wrote:
>
> On 3/16/24 11:35 AM, Vineet Gupta wrote:
>> Hi,
>>
>> This set of patches (for gcc-15) help improve stack/array accesses
>> by improving constant materialization. Details are in respective
>> patches.
>>
>> T
On 3/18/24 21:41, Jeff Law wrote:
>> The first patch is the main change which improves SPEC cactu by 10%.
> Just to confirm. Yup, 10% reduction in icounts and about a 3.5%
> improvement in cycles on our target. Which is great!
Nice.
> This also makes me wonder if cactu is the benchmark
On 3/19/24 06:10, Jeff Law wrote:
> On 3/19/24 12:48 AM, Andrew Waterman wrote:
>> On Mon, Mar 18, 2024 at 5:28 PM Vineet Gupta wrote:
>>> On 3/16/24 13:21, Jeff Law wrote:
>>>> | 59944:add s0,sp,2047 <
>>>> | 59948:m
On 3/16/24 13:21, Jeff Law wrote:
> | 59944:add s0,sp,2047 <
> | 59948:mv a2,a0
> | 5994c:mv a3,a1
> | 59950:mv a0,sp
> | 59954:li a4,1
> | 59958:lui a1,0x1
> | 5995c:add s0,s0,1 <---
> | 59960:jal
On 3/16/24 13:28, Jeff Law wrote:
>> Implementation Details (for posterity)
>> --
>> - basic idea is to have a splitter selected via a new predicate for
>> constant
>> being possible sum of two S12 and provide the transform.
>> This is however a 2
c.target/riscv/sum-of-two-s12-const-1.c: New test: checks for
new patterns output.
* gcc.target/riscv/sum-of-two-s12-const-2.c: New test: should not
ICE.
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/constraints.md | 6 +++
gcc/config/riscv/predic
.
* gcc.target/riscv/rvv/autovec/vls/spill-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/spill-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/spill-7.c: Ditto.
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/riscv-protos.h | 2 +
gcc/config/riscv/riscv.cc
config/riscv/riscv.cc (riscv_reg_frame_related): New helper to
conditionalize the existing and new spitters.
* config/riscv/riscv-protos.h: Add new prototype.
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/constraints.md | 6 ++
gcc/config/riscv/predicates.md | 8 ++-
gcc/
/riscv_legitimize_address) but that is tripping up
and currently being debugged.
Thx,
-Vineet
Vineet Gupta (3):
RISC-V: avoid LUI based const materialization ... [part of PR/106265]
RISC-V: avoid LUI based const mat: keep stack offsets aligned
RISC-V: avoid LUI based const mat in prologue/epilogue
On 3/5/24 23:27, pan2...@intel.com wrote:
> From: Pan Li
>
> Update in v2:
> * Cleanup some unused code.
> * Fix some typo of commit log.
>
> Original log:
>
> This patch would like to introduce one new gcc attribute for RVV.
> This attribute is used to define fixed-length variants of one
>
Hi Pan,
On 2/28/24 17:23, Li, Pan2 wrote:
>
> Personally I prefer to remove --param=riscv-autovec-preference=none
> and only allow
>
> mrvv-vector-bits, to avoid tricky(maybe) sematic of none preference.
> However, let’s
>
> wait for a while in case there are some comments from others.
>
We are
+CC Greg who might also have some bits in flight here.
On 2/23/24 01:23, Li, Pan2 wrote:
>
> > I would prefer to only keep zvl and scalable or zvl only, since I
>
> > don't see too much value in specifying a value which different from
>
> > zvl*b, that's a legacy option used before zvl*b option
: New enum vsetvl_strategy_enum.
* config/riscv/riscv-vsetvl.cc
(pre_vsetvl::pre_global_vsetvl_info): Use vsetvl_strategy.
(pass_vsetvl::execute): Use vsetvl_strategy.
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/riscv-opts.h| 9 +
gcc/config/riscv/riscv
-by: Vineet Gupta
---
gcc/config/riscv/riscv-vsetvl.cc | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 78a2f7b38faf..41d4b80648f6 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc
-by: Vineet Gupta
---
gcc/config/riscv/riscv-vsetvl.cc | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 78a2f7b38faf..41d4b80648f6 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc
: New enum vsetvl_strategy_enum.
* config/riscv/riscv-vsetvl.cc
(pre_vsetvl::pre_global_vsetvl_info): Use vsetvl_strategy.
(pass_vsetvl::execute): Use vsetvl_strategy.
Signed-off-by: Vineet Gupta
---
Changes since v1:
- Dropped OPTIM_NO_DEL
---
gcc/config/riscv/riscv-opts.h
: New enum vsetvl_strategy_enum.
* config/riscv/riscv-vsetvl.cc
(pre_vsetvl::pre_global_vsetvl_info): Use vsetvl_strategy.
(pass_vsetvl::execute): Use vsetvl_strategy.
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/riscv-opts.h| 11 +++
gcc/config/riscv/riscv
On 12/6/23 08:22, Palmer Dabbelt wrote:
>> Ran the test case at 122e7b4f9d0c2d54d865272463a1d812002d0a5c where the xfail
> That's the original port submission, I'm actually kind of surprised it
> still builds/works at all.
Full toolchain build would have been a stretch (matching pairing
gested one.
Tested-by: Patrick O'Neill # pre-commit-CI #679
Co-developed-by: Vineet Gupta
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/riscv-vsetvl.cc | 70
1 file changed, 35 insertions(+), 35 deletions(-)
diff --git a/gcc/config/r
#676
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/riscv.cc | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index e919850fc6cb..e466d4f168af 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config
n.
Commit contientent to pre-commit CI Testing feedback.
PR target/112447
Co-developed-by: Vineet Gupta
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (pre_vsetvl::emit_vsetvl): Insert
local vsetvl info before LCM suggested one.
Signed-off-by: Vineet Gupta
---
gcc/config/r
breg_prom): New.
* (riscv_extend_comparands): Call New function on operands.
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/riscv.cc | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index ecee7eb4727c..3896
Do we have call tomorrow, given some folks are traveling for RV Summit ?
Thx,
-Vineet
v/riscv.cc (riscv_promote_function_mode): Fix mode
returned for libcall case.
Tested-by: Patrick O'Neill # pre-commit-CI #526
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/riscv.cc | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/risc
On 11/1/23 12:11, Jeff Law wrote:
On 10/31/23 12:35, Vineet Gupta wrote:
riscv_promote_function_mode doesn't promote a SI to DI for libcalls
case.
The fix is what generic promote_mode () in explow.cc does. I really
don't understand why the old code didn't work, but stepping thru
On 10/31/23 17:51, Jeff Law wrote:
We also have a non-orthogonality in the ABI sign extension rules
between SI and DI, a few of us were talking about it on the internal
slack (though the specifics were for a different patch, Vineet has a
few in flight).
So the old issue I was thinking
On 10/30/23 13:33, Jeff Law wrote:
+/* Helper function for riscv_extend_comparands to Sign-extend the OP.
+ However if the OP is SI subreg promoted with an inner DI, such as
+ (subreg/s/v:SI (reg/v:DI) 0
+ just peel off the SUBREG to get DI, avoiding extraneous
extension. */
+
On 10/30/23 16:21, Vineet Gupta wrote:
I don't guess you have data on how this impacts dynamic instruction
counts on anything significant do you?
No, haven't run it yet. I can fire one though. I doubt if this is as
significant as the prev one, even if this is the right thing to do.
Very
for libcall case.
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/riscv.cc | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 3e27897d6d30..7b8e9af0a5af 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
On 10/30/23 13:33, Jeff Law wrote:
On 10/29/23 21:21, Vineet Gupta wrote:
RV64 compare and branch instructions only support 64-bit operands.
At Expand time, the backend conservatively zero/sign extends
its operands even if not needed, such as incoming 32-bit function args
which ABI/ISA
ion on operands.
Signed-off-by: Vineet Gupta
---
Changes since v2:
- Fix linting issues flagged by pre-commit CI
Changes since v1:
- Elide sign extension for 32-bit operarnds only
- Apply elison for both arguments
---
gcc/config/riscv/riscv.cc | 23 +--
1 file changed, 21 i
On 10/29/23 19:04, Vineet Gupta wrote:
RV64 compare and branch instructions only support 64-bit operands.
At Expand time, the backend conservatively zero/sign extends
its operands even if not needed, such as incoming 32-bit function args
which ABI/ISA guarantee to be sign-extended already
ion on operands.
Signed-off-by: Vineet Gupta
---
Changes since v1:
- Elide sign extension for 32-bit operarnds only
- Apply elison for both arguments
---
gcc/config/riscv/riscv.cc | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv.
On 10/27/23 10:16, Bernhard Reutner-Fischer wrote:
On Wed, 25 Oct 2023 16:41:07 +0530
Ajit Agarwal wrote:
On 25/10/23 2:19 am, Vineet Gupta wrote:
On 10/24/23 13:36, rep.dot@gmail.com wrote:
As said, I don't see why the below was not cleaned up before the V1 submission.
Iff it breaks
On 10/24/23 22:01, Vineet Gupta wrote:
RV64 comapre and branch instructions only support 64-bit operands.
The backend unconditionally generates zero/sign extend at Expand time
for compare and branch operands even if they are already as such
e.g. function args which ABI guarantees to be sign
On 10/25/23 06:52, Jeff Law wrote:
On 10/25/23 07:47, Robin Dapp wrote:
Well, it doesn't seem like there's a lot of difference between doing
it in the generic expander bits vs target expander bits -- the former
just calls into the latter for the most part. Thus if the
subreg-promoted
On 10/25/23 09:30, Jeff Law wrote:
- Should some common-code part be more suited to handle that?
We already elide redundant sign-zero extensions for other
reasons. Maybe we could add subreg promoted handling there?
Not in the context of this specific issue.
Robin's point (IIUC)
Hey Robin,
On 10/25/23 00:12, Robin Dapp wrote:
Hi Vineet,
I was thinking of two things while skimming the code:
- Couldn't we do this in the expanders directly? Or is the
subreg-promoted info gone until we reach that?
Following is the call stack involved:
expand_gimple_cond
* config/riscv/riscv.cc (riscv_extend_comparands): Don't
sign-extend operand if subreg promoted with inner word size.
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/riscv.cc | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/co
On 10/24/23 13:36, rep.dot@gmail.com wrote:
As said, I don't see why the below was not cleaned up before the V1 submission.
Iff it breaks when manually CSEing, I'm curious why?
The function below looks identical in v12 of the patch.
Why didn't you use common subexpressions?
ba
Using CSE
On 10/24/23 10:03, Ajit Agarwal wrote:
Hello Vineet, Jeff and Bernhard:
This version 14 of the patch uses abi interfaces to remove zero and sign
extension elimination.
This fixes aarch64 regressions failures with aggressive CSE.
Once again, this information belong between the two "---"
nterfaces code identifies
and extension (saw missing a definition, the it is not able to eliminate
any extensions despite the patch.
-Vineet
[1] https://gcc.gnu.org/pipermail/gcc-patches/2023-October/632180.html
On 22/10/23 12:56 am, rep.dot@gmail.com wrote:
On 21 October 2023 01:56:1
On 10/19/23 23:50, Ajit Agarwal wrote:
Hello All:
This version 9 of the patch uses abi interfaces to remove zero and sign
extension elimination.
Bootstrapped and regtested on powerpc-linux-gnu.
In this version (version 9) of the patch following review comments are
incorporated.
a) Removal
W.
Signed-off-by: Vineet Gupta
---
gcc/testsuite/gcc.target/riscv/pr111466.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/pr111466.c
b/gcc/testsuite/gcc.target/riscv/pr111466.c
index 007792466a51..3348d593813d 100644
--- a/gcc/testsuite/
W.
Signed-off-by: Vineet Gupta
---
Changes since v1:
- Changed function return to be unsigned int
---
gcc/testsuite/gcc.target/riscv/pr111466.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/pr111466.c
b/gcc/testsuite/gcc.target/riscv/
gcc/testsuite/ChangeLog:
* gcc.target/riscv/pr111466.c: Change to scan-assembler-not
to not detect sext.w.
Signed-off-by: Vineet Gupta
---
gcc/testsuite/gcc.target/riscv/pr111466.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/riscv
On 10/16/23 21:07, Jeff Law wrote:
On 9/28/23 15:43, Vineet Gupta wrote:
RISC-V suffers from extraneous sign extensions, despite/given the ABI
guarantee that 32-bit quantities are sign-extended into 64-bit
registers,
meaning incoming SI function args need not be explicitly sign extended
/flt-snan.c: Ditto.
* gcc.target/riscv/fltf-ieee.c: Ditto.
* gcc.target/riscv/fltf-snan.c: Ditto.
Signed-off-by: Vineet Gupta
---
gcc/testsuite/gcc.target/riscv/fle-ieee.c | 3 ++-
gcc/testsuite/gcc.target/riscv/fle-snan.c | 3 ++-
gcc/testsuite/gcc.target/riscv/fle.c | 3
/flt-snan.c: Ditto.
* gcc.target/riscv/fltf-ieee.c: Ditto.
* gcc.target/riscv/fltf-snan.c: Ditto.
Signed-off-by: Vineet Gupta
---
gcc/testsuite/gcc.target/riscv/fle-ieee.c | 3 ++-
gcc/testsuite/gcc.target/riscv/fle-snan.c | 3 ++-
gcc/testsuite/gcc.target/riscv/fle.c | 3
Hi Kito, Christoph, Patrick,
I've been trying to test a specific non multilib config
(rv64-zicond_zfa) and seeing noisy output (compared to a similar multlib
build) and it seems there's still a bunch of this header issue (for the
rv32 abi headers) in the non-multlib config.
e.g.
FAIL:
On 10/11/23 19:37, Hans-Peter Nilsson wrote:
```
foo2:
sext.w a6,a1 <-- this goes away
beq a1,zero,.L4
li a5,0
li a0,0
.L3:
addwa4,a2,a5
addwa5,a3,a5
addwa0,a4,a0
bltua5,a6,.L3
On 10/9/23 13:46, Christoph Müllner wrote:
Given that this causes repeated issues, I think that a fall-back to
counting occurrences is the right thing to do. I can do that if that's ok.
Thanks Christoph.
-Vineet
:22, Vineet Gupta wrote:
Vlad recently introduced a new gate @ira_in_progress, similar to
counterparts @{reload,lra}_in_progress.
Use this to hide the constant synthesis splitter from being recog* ()
by IRA register equivalence logic which is eager to undo the splits,
generating worse code
(mvconst_internal): Add !ira_in_progress.
Suggested-by: Jeff Law
Signed-off-by: Vineet Gupta
---
gcc/config/riscv/riscv.md | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 1ebe8f92284d..da84b9357bd3 100644
(mvconst_internal): Add !ira_in_progress.
Suggested-by: Jeff Law
Signed-off-by: Vineet Gupta
---
changes since v1:
- Fix bug: new condition to prevent recognition not splitting itself
---
gcc/config/riscv/riscv.md | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/gcc
On 10/4/23 10:59, Jeff Law wrote:
On 9/28/23 15:43, Vineet Gupta wrote:
RISC-V suffers from extraneous sign extensions, despite/given the ABI
guarantee that 32-bit quantities are sign-extended into 64-bit
registers,
meaning incoming SI function args need not be explicitly sign extended
(so
On 9/29/23 05:14, Jeff Law wrote:
On 9/28/23 21:49, Vineet Gupta wrote:
On 9/28/23 20:17, Jeff Law wrote:
I can bootstrap & regression test alpha using QEMU user mode
emulation. So we might be able to trigger something that way. It'll
take some time, but might prove frui
On 9/28/23 12:52, Vineet Gupta wrote:
On 9/28/23 05:53, Jeff Law wrote:
Vineet -- assuming Vlad's patch goes in, the other obvious candidate
for this would be the mvconst_internal define_insn_and_split where
we'd probably want to reject the insn as a whole once IRA has started.
Good
On 9/11/23 06:12, Jeff Law via Gcc-patches wrote:
On 9/10/23 21:42, juzhe.zh...@rivai.ai wrote:
Ping this patch.
I think it's time to enable scalable vectorization by default and do
the whole regression every time (except vect.exp that we didn't
enable yet)
Update current FAILs
On 9/28/23 20:17, Jeff Law wrote:
I can bootstrap & regression test alpha using QEMU user mode
emulation. So we might be able to trigger something that way. It'll
take some time, but might prove fruitful.
That would be awesome. It's not like this this is burning or anything
and one of the
,0
li a0,0
.L3:
addwa4,a2,a5
addwa5,a3,a5
addwa0,a4,a0
bltua5,a6,.L3
ret
.L4:
li a0,0
ret
```
Signed-off-by: Vineet Gupta
Co-developed-by: Robin Dapp
---
gcc/expr.cc | 7 ---
On 9/27/23 13:14, Jeff Law wrote:
It would help to describe how these patterns were under specified so
that folks don't continue to make the same mistake as new tests get
added.
dg-final scan-assembler, scan-assembler-not, and scan-assembler-times
use a tcl regular expression (often
Hi Jeff,
On 9/19/23 07:59, Jeff Law wrote:
On 9/18/23 21:37, Vineet Gupta wrote:
On 9/18/23 19:41, Jeff Law wrote:
On 9/18/23 13:45, Vineet Gupta wrote:
For the cases which do require sign extends, but not being
eliminated due to "missing definition(s)" I'm working on adapti
+CC Patrick who's been chasing similar issues.
On 9/23/23 00:18, Maciej W. Rozycki wrote:
In non-multilib installations system headers may not be available for
compilation options using a non-default model, causing build errors such
as:
In file included from .../include/features.h:527,
On 9/18/23 19:41, Jeff Law wrote:
On 9/18/23 13:45, Vineet Gupta wrote:
For the cases which do require sign extends, but not being eliminated
due to "missing definition(s)" I'm working on adapting Ajit's REE ABI
interfaces work [2] to work for RISC-V as well.
I wonder if we
On 9/18/23 19:41, Jeff Law wrote:
On 9/18/23 13:45, Vineet Gupta wrote:
For the cases which do require sign extends, but not being eliminated
due to "missing definition(s)" I'm working on adapting Ajit's REE ABI
interfaces work [2] to work for RISC-V as well.
I wonder if we
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