Re: [PATCH v5] RISC-V: Fix register overlap issue for some xtheadvector instructions

2024-01-11 Thread Robin Dapp
LGTM now, thanks. I find it much more readable that way. Regards Robin

Re: [PATCH v5] RISC-V: Fix register overlap issue for some xtheadvector instructions

2024-01-10 Thread juzhe.zh...@rivai.ai
; Xianmiao Qu Subject: [PATCH v5] RISC-V: Fix register overlap issue for some xtheadvector instructions For th.vmadc/th.vmsbc as well as narrowing arithmetic instructions and floating-point compare instructions, an illegal instruction exception will be raised if the destination vector register overlaps

Re:Re: [PATCH v5] RISC-V: Fix register overlap issue for some xtheadvector instructions

2024-01-10 Thread joshua
:43 收件人:"rdapp.gcc"; "cooper.joshua"; "gcc-patches" 抄 送:"rdapp.gcc"; "jim.wilson.gcc"; palmer; andrew; "philipp.tomsich"; Jeff Law; "Christoph Müllner"; jinma; Cooper Qu 主 题:Re: Re: [PATCH v5] RISC-V: Fix register overlap

[PATCH v5] RISC-V: Fix register overlap issue for some xtheadvector instructions

2024-01-10 Thread Jun Sha (Joshua)
For th.vmadc/th.vmsbc as well as narrowing arithmetic instructions and floating-point compare instructions, an illegal instruction exception will be raised if the destination vector register overlaps a source vector register group. To handle this issue, we add an attribute "spec_restriction" to

Re: Re: [PATCH v5] RISC-V: Fix register overlap issue for some xtheadvector instructions

2024-01-10 Thread 钟居哲
So I think it's better to add an attribute to disable alternative for theadvector or RVV1.0. juzhe.zh...@rivai.ai From: Robin Dapp Date: 2024-01-10 21:36 To: Jun Sha (Joshua); gcc-patches CC: rdapp.gcc; jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; christoph.muellner; juzhe.

Re: [PATCH v5] RISC-V: Fix register overlap issue for some xtheadvector instructions

2024-01-10 Thread Robin Dapp
Hi Joshua, > For th.vmadc/th.vmsbc as well as narrowing arithmetic instructions > and floating-point compare instructions, an illegal instruction > exception will be raised if the destination vector register overlaps > a source vector register group. > > To handle this issue, we use

Re: [PATCH v5] RISC-V: Fix register overlap issue for some xtheadvector instructions

2024-01-09 Thread juzhe.zh...@rivai.ai
; Xianmiao Qu Subject: [PATCH v5] RISC-V: Fix register overlap issue for some xtheadvector instructions For th.vmadc/th.vmsbc as well as narrowing arithmetic instructions and floating-point compare instructions, an illegal instruction exception will be raised if the destination vector register overlaps

[PATCH v5] RISC-V: Fix register overlap issue for some xtheadvector instructions

2024-01-09 Thread Jun Sha (Joshua)
For th.vmadc/th.vmsbc as well as narrowing arithmetic instructions and floating-point compare instructions, an illegal instruction exception will be raised if the destination vector register overlaps a source vector register group. To handle this issue, we use "group_overlap" and "enabled"

Re: [PATCH v5] RISC-V: Fix register overlap issue for some xtheadvector instructions

2024-01-09 Thread juzhe.zh...@rivai.ai
_VECTOR && !TARGET_XTHEADVECTOR")) + (const_string "no") + ] juzhe.zh...@rivai.ai From: Jun Sha (Joshua) Date: 2024-01-10 14:02 To: gcc-patches CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; christoph.muellner; juzhe.zhong; Jun Sha (Joshua); J

[PATCH v5] RISC-V: Fix register overlap issue for some xtheadvector instructions

2024-01-09 Thread Jun Sha (Joshua)
For th.vmadc/th.vmsbc as well as narrowing arithmetic instructions and floating-point compare instructions, an illegal instruction exception will be raised if the destination vector register overlaps a source vector register group. To handle this issue, we use "group_overlap" and "enabled"