[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Populate connector->ddc always (rev3)

2023-09-01 Thread Patchwork
== Series Details == Series: drm/i915: Populate connector->ddc always (rev3) URL : https://patchwork.freedesktop.org/series/123006/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13588_full -> Patchwork_123006v3_full

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: VRR, LRR, and M/N stuff (rev2)

2023-09-01 Thread Patchwork
== Series Details == Series: drm/i915: VRR, LRR, and M/N stuff (rev2) URL : https://patchwork.freedesktop.org/series/123171/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13588_full -> Patchwork_123171v2_full Summary

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915: Schedule the HPD poll init work on an unbound workqueue

2023-09-01 Thread Patchwork
== Series Details == Series: series starting with [1/2] drm/i915: Schedule the HPD poll init work on an unbound workqueue URL : https://patchwork.freedesktop.org/series/123173/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13588_full -> Patchwork_123173v1_full

[Intel-gfx] ✗ Fi.CI.IGT: failure for fbc on any plane (rev3)

2023-09-01 Thread Patchwork
== Series Details == Series: fbc on any plane (rev3) URL : https://patchwork.freedesktop.org/series/122958/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13588_full -> Patchwork_122958v3_full Summary --- **FAILURE**

[Intel-gfx] ✗ Fi.CI.IGT: failure for Handle dma fences in dirtyfb ioctl (rev6)

2023-09-01 Thread Patchwork
== Series Details == Series: Handle dma fences in dirtyfb ioctl (rev6) URL : https://patchwork.freedesktop.org/series/116620/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13588_full -> Patchwork_116620v6_full Summary

Re: [Intel-gfx] [PATCH v4 5/6] drm/i915/dp_link_training: Set all downstream MST ports to BAD before retrying

2023-09-01 Thread Gil Dekel
On Fri, Sep 1, 2023 at 5:13 PM Gil Dekel wrote: > > On Fri, Sep 1, 2023 at 2:55 PM Rodrigo Vivi wrote: > > > > On Thu, Aug 24, 2023 at 04:50:20PM -0400, Gil Dekel wrote: > > > Before sending a uevent to userspace in order to trigger a corrective > > > modeset, we change the failing connector's

Re: [Intel-gfx] [PATCH v4 6/6] drm/i915/dp_link_training: Emit a link-status=Bad uevent with trigger property

2023-09-01 Thread Manasi Navare
Thanks Gil for completing the logic here by emitting link status = BAD even for final link failure state. On Thu, Aug 24, 2023 at 1:54 PM Gil Dekel wrote: > > When a link-training attempt fails, emit a uevent to user space that > includes the trigger property, which in this case will be >

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add Wa_14015150844 (rev4)

2023-09-01 Thread Patchwork
== Series Details == Series: drm/i915: Add Wa_14015150844 (rev4) URL : https://patchwork.freedesktop.org/series/123074/ State : success == Summary == CI Bug Log - changes from CI_DRM_13588 -> Patchwork_123074v4 Summary ---

Re: [Intel-gfx] [PATCH v4 1/6] drm/i915/dp_link_training: Add a final failing state to link training fallback

2023-09-01 Thread Gil Dekel
On Fri, Sep 1, 2023 at 2:57 PM Rodrigo Vivi wrote: > > On Thu, Aug 24, 2023 at 04:50:16PM -0400, Gil Dekel wrote: > > Instead of silently giving up when all link-training fallback values are > > exhausted, this patch modifies the fallback's failure branch to reduces > > both max_link_lane_count

Re: [Intel-gfx] [PATCH] drm/i915: Add Wa_14015150844

2023-09-01 Thread Matt Roper
On Fri, Sep 01, 2023 at 10:27:00AM +0530, Shekhar Chauhan wrote: > Disables Atomic-chaining of Typed Writes. > > BSpec: 54040 > Signed-off-by: Shekhar Chauhan Reviewed-by: Matt Roper > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++ > drivers/gpu/drm/i915/gt/intel_workarounds.c | 8

Re: [Intel-gfx] [PATCH v4 5/6] drm/i915/dp_link_training: Set all downstream MST ports to BAD before retrying

2023-09-01 Thread Gil Dekel
On Fri, Sep 1, 2023 at 2:55 PM Rodrigo Vivi wrote: > > On Thu, Aug 24, 2023 at 04:50:20PM -0400, Gil Dekel wrote: > > Before sending a uevent to userspace in order to trigger a corrective > > modeset, we change the failing connector's link-status to BAD. However, > > the downstream MST branch

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Populate connector->ddc always (rev3)

2023-09-01 Thread Patchwork
== Series Details == Series: drm/i915: Populate connector->ddc always (rev3) URL : https://patchwork.freedesktop.org/series/123006/ State : success == Summary == CI Bug Log - changes from CI_DRM_13588 -> Patchwork_123006v3 Summary ---

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Populate connector->ddc always (rev3)

2023-09-01 Thread Patchwork
== Series Details == Series: drm/i915: Populate connector->ddc always (rev3) URL : https://patchwork.freedesktop.org/series/123006/ State : warning == Summary == Error: dim checkpatch failed 8fd33ded9c0a drm: Reorder drm_sysfs_connector_remove() vs. drm_debugfs_connector_remove()

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Populate connector->ddc always (rev3)

2023-09-01 Thread Patchwork
== Series Details == Series: drm/i915: Populate connector->ddc always (rev3) URL : https://patchwork.freedesktop.org/series/123006/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

Re: [Intel-gfx] [PATCH 1/6] drm/edid: add drm_edid_is_digital()

2023-09-01 Thread Alex Deucher
On Thu, Aug 24, 2023 at 9:46 AM Jani Nikula wrote: > > Checking edid->input & DRM_EDID_INPUT_DIGITAL is common enough to > deserve a helper that also lets us abstract the raw EDID a bit better. > > Signed-off-by: Jani Nikula Reviewed-by: Alex Deucher Seems to be a few additional users of this

Re: [Intel-gfx] [PATCH v4 0/6] drm/i915/dp_link_training: Define a final failure state when link training fails

2023-09-01 Thread Gil Dekel
On Fri, Sep 1, 2023 at 3:05 PM Rodrigo Vivi wrote: > > On Fri, Sep 01, 2023 at 02:38:11PM -0400, Rodrigo Vivi wrote: > > On Wed, Aug 30, 2023 at 05:41:37PM -0400, Lyude Paul wrote: > > > Other then the name typo (s/Pual/Paul): > > > > > > Signed-off-by: Lyude Paul (just since I co-authored > > >

Re: [Intel-gfx] [PATCH v4 0/6] drm/i915/dp_link_training: Define a final failure state when link training fails

2023-09-01 Thread Rodrigo Vivi
On Fri, Sep 01, 2023 at 02:38:11PM -0400, Rodrigo Vivi wrote: > On Wed, Aug 30, 2023 at 05:41:37PM -0400, Lyude Paul wrote: > > Other then the name typo (s/Pual/Paul): > > > > Signed-off-by: Lyude Paul (just since I co-authored > > things~) > > I believe having the Co-developed-by: in the

Re: [Intel-gfx] [PATCH 0/4] drm/amd/display: stop using drm_edid_override_connector_update()

2023-09-01 Thread Alex Deucher
On Thu, Aug 31, 2023 at 6:01 PM Alex Hung wrote: > > > > On 2023-08-30 01:29, Jani Nikula wrote: > > On Tue, 29 Aug 2023, Alex Hung wrote: > >> On 2023-08-29 11:03, Jani Nikula wrote: > >>> On Tue, 29 Aug 2023, Jani Nikula wrote: > On Tue, 29 Aug 2023, Alex Deucher wrote: > > On Tue,

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: VRR, LRR, and M/N stuff (rev2)

2023-09-01 Thread Patchwork
== Series Details == Series: drm/i915: VRR, LRR, and M/N stuff (rev2) URL : https://patchwork.freedesktop.org/series/123171/ State : success == Summary == CI Bug Log - changes from CI_DRM_13588 -> Patchwork_123171v2 Summary ---

Re: [Intel-gfx] [PATCH v4 1/6] drm/i915/dp_link_training: Add a final failing state to link training fallback

2023-09-01 Thread Rodrigo Vivi
On Thu, Aug 24, 2023 at 04:50:16PM -0400, Gil Dekel wrote: > Instead of silently giving up when all link-training fallback values are > exhausted, this patch modifies the fallback's failure branch to reduces > both max_link_lane_count and max_link_rate to zero (0) and continues to > emit uevents

Re: [Intel-gfx] [PATCH v4 5/6] drm/i915/dp_link_training: Set all downstream MST ports to BAD before retrying

2023-09-01 Thread Rodrigo Vivi
On Thu, Aug 24, 2023 at 04:50:20PM -0400, Gil Dekel wrote: > Before sending a uevent to userspace in order to trigger a corrective > modeset, we change the failing connector's link-status to BAD. However, > the downstream MST branch ports are left in their original GOOD state. > > This patch

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: VRR, LRR, and M/N stuff (rev2)

2023-09-01 Thread Patchwork
== Series Details == Series: drm/i915: VRR, LRR, and M/N stuff (rev2) URL : https://patchwork.freedesktop.org/series/123171/ State : warning == Summary == Error: dim checkpatch failed c7fffe8e772b drm/i915: Move psr unlock out from the pipe update critical section 0431a7e05f0c drm/i915:

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: VRR, LRR, and M/N stuff (rev2)

2023-09-01 Thread Patchwork
== Series Details == Series: drm/i915: VRR, LRR, and M/N stuff (rev2) URL : https://patchwork.freedesktop.org/series/123171/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

Re: [Intel-gfx] [PATCH v4 0/6] drm/i915/dp_link_training: Define a final failure state when link training fails

2023-09-01 Thread Rodrigo Vivi
On Wed, Aug 30, 2023 at 05:41:37PM -0400, Lyude Paul wrote: > Other then the name typo (s/Pual/Paul): > > Signed-off-by: Lyude Paul (just since I co-authored > things~) I believe having the Co-developed-by: in the patches that you helped out would be nice. > Reviewed-by: Lyude Paul > > I

[Intel-gfx] ✗ Fi.CI.BAT: failure for Apply Wa_16018031267 / Wa_16018063123

2023-09-01 Thread Patchwork
== Series Details == Series: Apply Wa_16018031267 / Wa_16018063123 URL : https://patchwork.freedesktop.org/series/123182/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13588 -> Patchwork_123182v1 Summary ---

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Apply Wa_16018031267 / Wa_16018063123

2023-09-01 Thread Patchwork
== Series Details == Series: Apply Wa_16018031267 / Wa_16018063123 URL : https://patchwork.freedesktop.org/series/123182/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Apply Wa_16018031267 / Wa_16018063123

2023-09-01 Thread Patchwork
== Series Details == Series: Apply Wa_16018031267 / Wa_16018063123 URL : https://patchwork.freedesktop.org/series/123182/ State : warning == Summary == Error: dim checkpatch failed 1d843cfd7a48 drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123 -:10: WARNING:BAD_SIGN_OFF:

[Intel-gfx] ✓ Fi.CI.BAT: success for fbc on any planes

2023-09-01 Thread Patchwork
== Series Details == Series: fbc on any planes URL : https://patchwork.freedesktop.org/series/123180/ State : success == Summary == CI Bug Log - changes from CI_DRM_13588 -> Patchwork_123180v1 Summary --- **SUCCESS** No

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for fbc on any planes

2023-09-01 Thread Patchwork
== Series Details == Series: fbc on any planes URL : https://patchwork.freedesktop.org/series/123180/ State : warning == Summary == Error: dim checkpatch failed 53724ea338ef drm/i915/lnl: possibility to enable FBC on first three planes -:71: WARNING:LONG_LINE: line length of 105 exceeds 100

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for fbc on any planes

2023-09-01 Thread Patchwork
== Series Details == Series: fbc on any planes URL : https://patchwork.freedesktop.org/series/123180/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:117:1: warning:

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Schedule the HPD poll init work on an unbound workqueue

2023-09-01 Thread Patchwork
== Series Details == Series: series starting with [1/2] drm/i915: Schedule the HPD poll init work on an unbound workqueue URL : https://patchwork.freedesktop.org/series/123173/ State : success == Summary == CI Bug Log - changes from CI_DRM_13588 -> Patchwork_123173v1

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915: Schedule the HPD poll init work on an unbound workqueue

2023-09-01 Thread Patchwork
== Series Details == Series: series starting with [1/2] drm/i915: Schedule the HPD poll init work on an unbound workqueue URL : https://patchwork.freedesktop.org/series/123173/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Schedule the HPD poll init work on an unbound workqueue

2023-09-01 Thread Patchwork
== Series Details == Series: series starting with [1/2] drm/i915: Schedule the HPD poll init work on an unbound workqueue URL : https://patchwork.freedesktop.org/series/123173/ State : warning == Summary == Error: dim checkpatch failed 7e899922aaa5 drm/i915: Schedule the HPD poll init work

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: VRR, LRR, and M/N stuff

2023-09-01 Thread Patchwork
== Series Details == Series: drm/i915: VRR, LRR, and M/N stuff URL : https://patchwork.freedesktop.org/series/123171/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13588 -> Patchwork_123171v1 Summary --- **FAILURE**

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: VRR, LRR, and M/N stuff

2023-09-01 Thread Patchwork
== Series Details == Series: drm/i915: VRR, LRR, and M/N stuff URL : https://patchwork.freedesktop.org/series/123171/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: VRR, LRR, and M/N stuff

2023-09-01 Thread Patchwork
== Series Details == Series: drm/i915: VRR, LRR, and M/N stuff URL : https://patchwork.freedesktop.org/series/123171/ State : warning == Summary == Error: dim checkpatch failed ceb5c675ed7d drm/i915: Move psr unlock out from the pipe update critical section bcfae40b96e1 drm/i915: Change

[Intel-gfx] ✓ Fi.CI.BAT: success for fbc on any plane (rev3)

2023-09-01 Thread Patchwork
== Series Details == Series: fbc on any plane (rev3) URL : https://patchwork.freedesktop.org/series/122958/ State : success == Summary == CI Bug Log - changes from CI_DRM_13588 -> Patchwork_122958v3 Summary --- **SUCCESS** No

[Intel-gfx] [PATCH v5 1/2] drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123

2023-09-01 Thread Jonathan Cavitt
Apply WABB blit for Wa_16018031267 / Wa_16018063123. Additionally, update the lrc selftest to exercise the new WABB changes. Co-developed-by: Nirmoy Das Signed-off-by: Jonathan Cavitt --- drivers/gpu/drm/i915/gt/intel_engine_regs.h | 3 + drivers/gpu/drm/i915/gt/intel_gt.h | 4 +

[Intel-gfx] [PATCH v5 0/2] Apply Wa_16018031267 / Wa_16018063123

2023-09-01 Thread Jonathan Cavitt
Apply Wa_16018031267 / Wa_16018063123. This necessitates submitting a fastcolor blit as WABB and setting the copy engine arbitration to round-robin mode. v2: - Rename old platform check in second patch to match declaration in first patch. - Refactor second patch name to match first patch. v3:

[Intel-gfx] [PATCH v5 2/2] drm/i915: Set copy engine arbitration for Wa_16018031267 / Wa_16018063123

2023-09-01 Thread Jonathan Cavitt
Set copy engine arbitration into round robin mode for part of Wa_16018031267 / Wa_16018063123 mitigation. Signed-off-by: Nirmoy Das Signed-off-by: Jonathan Cavitt --- drivers/gpu/drm/i915/gt/intel_engine_regs.h | 3 +++ drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 + 2 files changed, 8

[Intel-gfx] ✓ Fi.CI.BAT: success for Handle dma fences in dirtyfb ioctl (rev6)

2023-09-01 Thread Patchwork
== Series Details == Series: Handle dma fences in dirtyfb ioctl (rev6) URL : https://patchwork.freedesktop.org/series/116620/ State : success == Summary == CI Bug Log - changes from CI_DRM_13588 -> Patchwork_116620v6 Summary ---

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/dsi: let HW maintain HS-TRAIL and CLK_POST

2023-09-01 Thread Patchwork
== Series Details == Series: drm/i915/dsi: let HW maintain HS-TRAIL and CLK_POST URL : https://patchwork.freedesktop.org/series/123157/ State : failure == Summary == Error: make failed CALLscripts/checksyscalls.sh DESCEND objtool INSTALL libsubcmd_headers CC [M]

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Handle dma fences in dirtyfb ioctl (rev6)

2023-09-01 Thread Patchwork
== Series Details == Series: Handle dma fences in dirtyfb ioctl (rev6) URL : https://patchwork.freedesktop.org/series/116620/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

Re: [Intel-gfx] [PATCH v2 1/1] drm/i915/lnl: possibility to enable FBC on first three planes

2023-09-01 Thread Govindapillai, Vinod
Thanks Ville. Updated the patch as per your comments. About the WA, I am planning to send that as two separate patches one were we enabled FBC + PSR2 based on some conditions and the next one this WA BR Vinod On Fri, 2023-09-01 at 16:10 +0300, Ville Syrjälä wrote: > On Fri, Sep 01, 2023 at

[Intel-gfx] [PATCH v3 2/2] drm/i915/lnl: FBC is supported with per pixel alpha

2023-09-01 Thread Vinod Govindapillai
For LNL onwards, FBC can be supported on planes with per pixel alpha Bspec: 69560 Signed-off-by: Vinod Govindapillai --- drivers/gpu/drm/i915/display/intel_fbc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c

[Intel-gfx] [PATCH v3 1/2] drm/i915/lnl: possibility to enable FBC on first three planes

2023-09-01 Thread Vinod Govindapillai
In LNL onwards, FBC can be associated to the first three planes. FBC will be enabled on planes first come first served basis until the userspace can select one of these FBC capable planes explicitly. v2: - avoid fbc->state.plane check in intel_fbc_check_plane (Ville) - simplify plane binding

[Intel-gfx] [PATCH v3 0/2] fbc on any planes

2023-09-01 Thread Vinod Govindapillai
FBC can be supported in first three planes in lnl Vinod Govindapillai (2): drm/i915/lnl: possibility to enable FBC on first three planes drm/i915/lnl: FBC is supported with per pixel alpha drivers/gpu/drm/i915/display/intel_fbc.c | 6 +-

[Intel-gfx] [PATCH 2/2] drm: Schedule the HPD poll work on the system unbound workqueue

2023-09-01 Thread Imre Deak
On some i915 platforms at least the HPD poll work involves I2C bit-banging using udelay()s to probe for monitor EDIDs. This in turn may trigger the workqueue: output_poll_execute [drm_kms_helper] hogged CPU for >1us 4 times, consider switching to WQ_UNBOUND warning. Fix this by scheduling

[Intel-gfx] [PATCH 1/2] drm/i915: Schedule the HPD poll init work on an unbound workqueue

2023-09-01 Thread Imre Deak
Disabling HPD polling from i915_hpd_poll_init_work() involves probing all display connectors explicitly to account for lost hotplug interrupts. On some platforms (mostly pre-ICL) with HDMI connectors the I2C EDID bit-banging using udelay() triggers in turn the workqueue: i915_hpd_poll_init_work

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/display/dp: Add the remaining Square PHY patterns DPCD register definitions

2023-09-01 Thread Patchwork
== Series Details == Series: drm/display/dp: Add the remaining Square PHY patterns DPCD register definitions URL : https://patchwork.freedesktop.org/series/123149/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13587 -> Patchwork_123149v1

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/display/dp: Add the remaining Square PHY patterns DPCD register definitions

2023-09-01 Thread Patchwork
== Series Details == Series: drm/display/dp: Add the remaining Square PHY patterns DPCD register definitions URL : https://patchwork.freedesktop.org/series/123149/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked

Re: [Intel-gfx] [PATCH] drm/i915/dsi: let HW maintain HS-TRAIL and CLK_POST

2023-09-01 Thread kernel test robot
Hi William, kernel test robot noticed the following build errors: [auto build test ERROR on drm-tip/drm-tip] url: https://github.com/intel-lab-lkp/linux/commits/William-Tseng/drm-i915-dsi-let-HW-maintain-HS-TRAIL-and-CLK_POST/20230901-175307 base: git://anongit.freedesktop.org/drm/drm-tip

Re: [Intel-gfx] [PATCH v2 1/1] drm/i915/lnl: possibility to enable FBC on first three planes

2023-09-01 Thread Ville Syrjälä
On Fri, Sep 01, 2023 at 03:59:50PM +0300, Vinod Govindapillai wrote: > In LNL onwards, FBC can be associated to the first three planes. > FBC will be enabled on planes first come first served basis > until the userspace can select one of these FBC capable plane > explicitly. FBC can be supported

Re: [Intel-gfx] [PATCH] drm/i915/dsi: let HW maintain HS-TRAIL and CLK_POST

2023-09-01 Thread kernel test robot
Hi William, kernel test robot noticed the following build errors: [auto build test ERROR on drm-tip/drm-tip] url: https://github.com/intel-lab-lkp/linux/commits/William-Tseng/drm-i915-dsi-let-HW-maintain-HS-TRAIL-and-CLK_POST/20230901-175307 base: git://anongit.freedesktop.org/drm/drm-tip

[Intel-gfx] [PATCH 12/12] drm/i915: Implement transcoder LRR for TGL+

2023-09-01 Thread Ville Syrjala
From: Ville Syrjälä Implement low refresh rate (LRR) where we change the vblank length by hand as requested, but otherwise keep the timing generator running in non-VRR mode (ie. fixed refresh rate). The panel itself must support VRR for this to work, and only TGL+ has the double buffred

[Intel-gfx] [PATCH 11/12] drm/i915: Assert that VRR is off during vblank evasion if necessary

2023-09-01 Thread Ville Syrjala
From: Ville Syrjälä Whenever we change the actual transcoder timings (clock via seamless M/N, full modeset, (or soon) vtotal via LRR) we want the timing generator to be in non-VRR during the commit. Warn if we forgot to turn VRR off prior to vblank evasion. Cc: Manasi Navare Signed-off-by:

[Intel-gfx] [PATCH 10/12] drm/i915: Update VRR parameters in fastset

2023-09-01 Thread Ville Syrjala
From: Ville Syrjälä We should be able to change any of the VRR parameters during fastsets as long as we toggle VRR off at the start and then back on at the end. The transcoder will be running in non-VRR mode during the transition. Co-developed-by: Manasi Navare Signed-off-by: Manasi Navare

[Intel-gfx] [PATCH 08/12] drm/i915: Validate that the timings are within the VRR range

2023-09-01 Thread Ville Syrjala
From: Ville Syrjälä Let's assume there are some crazy displays where the high end of the VRR range ends up being lower than the refresh rate as determined by the actual timings. In that case when we toggle VRR on/off we would step outside the VRR range when toggling VRR on/off. Let's just make

[Intel-gfx] [PATCH 09/12] drm/i915: Disable VRR during seamless M/N changes

2023-09-01 Thread Ville Syrjala
From: Ville Syrjälä Make life less confusing by making sure VRR is disabled whenever we do any drastic changes to the display timings, such as seamless M/N changes. Cc: Manasi Navare Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 6 -- 1 file changed, 4

[Intel-gfx] [PATCH 07/12] drm/i915: Relocate is_in_vrr_range()

2023-09-01 Thread Ville Syrjala
From: Ville Syrjälä Move is_in_vrr_range() into intel_vrr.c in anticipation of more users, and rename it accordingly. Cc: Manasi Navare Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_panel.c | 17 - drivers/gpu/drm/i915/display/intel_vrr.c | 9

[Intel-gfx] [PATCH 04/12] drm/i915: Enable VRR later during fastsets

2023-09-01 Thread Ville Syrjala
From: Ville Syrjälä In order to reconcile seamless M/N updates with VRR we'll need to defer the fastset VRR enable to happen after the seamless M/N update (which happens during the vblank evade critical section). So just push the VRR enable to be the last thing during the update. This will also

[Intel-gfx] [PATCH 05/12] drm/i915: Adjust seamless_m_n flag behaviour

2023-09-01 Thread Ville Syrjala
From: Ville Syrjälä Make the seamless_m_n flag more like the update_pipe fastset flag, ie. the flag will only be set if we need to do the seamless M/N update, and in all other cases the flag is cleared. Also rename the flag to update_m_n to make it more clear it's similar to update_pipe. I

[Intel-gfx] [PATCH 06/12] drm/i915: Optimize out redundant M/N updates

2023-09-01 Thread Ville Syrjala
From: Ville Syrjälä Don't perform a seamless M/N update if the values aren't actually changing. This avoids doing extra shenanigans during vblank evasion needlessly. Cc: Manasi Navare Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 4 +++- 1 file changed, 3

[Intel-gfx] [PATCH 03/12] drm/i915: Extract intel_crtc_vblank_evade_scanlines()

2023-09-01 Thread Ville Syrjala
From: Ville Syrjälä Pull the vblank evasion scanline calculations into their own helper to declutter intel_pipe_update_start() a bit. Reviewed-by: Manasi Navare Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_crtc.c | 53 +-- 1 file changed, 31

[Intel-gfx] [PATCH 02/12] drm/i915: Change intel_pipe_update_{start, end}() calling convention

2023-09-01 Thread Ville Syrjala
From: Ville Syrjälä We'll need to also look at the old crtc state in intel_pipe_update_start() so change the calling convention to just plumb in the full atomic state instead. Cc: Manasi Navare Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_crtc.c| 18

[Intel-gfx] [PATCH 01/12] drm/i915: Move psr unlock out from the pipe update critical section

2023-09-01 Thread Ville Syrjala
From: Ville Syrjälä Do the PSR unlock after the vblank evade critcal section is fully over, not before. Cc: Manasi Navare Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_crtc.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git

[Intel-gfx] [PATCH 00/12] drm/i915: VRR, LRR, and M/N stuff

2023-09-01 Thread Ville Syrjala
From: Ville Syrjälä Attempt to make VRR, LRR, and M/N updates coexist nicely, allowing fastsets whenever feasible. Lightly smoke tested on my adl. Cc: Manasi Navare Ville Syrjälä (12): drm/i915: Move psr unlock out

[Intel-gfx] [PATCH v2 0/1] fbc on any plane

2023-09-01 Thread Vinod Govindapillai
FBC can be supported in first three planes in lnl Matt pointed out that FBC + PSR2 combination require few more condition checks and also a WA also need to be impleteds. So patch to enabled FBC in case of PSR2 is removed from this version. Also per pizel alpha condition is removed for FBC in

[Intel-gfx] [PATCH v2 1/1] drm/i915/lnl: possibility to enable FBC on first three planes

2023-09-01 Thread Vinod Govindapillai
In LNL onwards, FBC can be associated to the first three planes. FBC will be enabled on planes first come first served basis until the userspace can select one of these FBC capable plane explicitly. FBC can be supported in planes with per pixel alpha v2: - avoid fbc->state.plane check in

[Intel-gfx] [PATCH v2 1/1] drm/i915/lnl: possibility to enable FBC on first three planes

2023-09-01 Thread Vinod Govindapillai
In LNL onwards, FBC can be associated to the first three planes. FBC will be enabled on planes first come first served basis until the userspace can select one of these FBC capable plane explicitly. FBC can be supported in planes with per pixel alpha v2: - avoid fbc->state.plane check in

[Intel-gfx] [PATCH v2 0/1] fbc on any plane

2023-09-01 Thread Vinod Govindapillai
FBC can be supported in first three planes in lnl Matt pointed out that FBC + PSR2 combination require few more condition checks and also a WA also need to be impleteds. So patch to enabled FBC in case of PSR2 is removed from this version. Also per pizel alpha condition is removed for FBC in

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Add Wa_14015150844 (rev3)

2023-09-01 Thread Patchwork
== Series Details == Series: drm/i915: Add Wa_14015150844 (rev3) URL : https://patchwork.freedesktop.org/series/123074/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13587 -> Patchwork_123074v3 Summary ---

Re: [Intel-gfx] [PATCH 0/4] drm/amd/display: stop using drm_edid_override_connector_update()

2023-09-01 Thread Jani Nikula
On Thu, 31 Aug 2023, Alex Hung wrote: > On 2023-08-30 01:29, Jani Nikula wrote: >> On Tue, 29 Aug 2023, Alex Hung wrote: >>> There is a patch under internal reviews. It removes calls edid_override >>> and drm_edid_override_connector_update as intended in this patchset but >>> does not remove the

Re: [Intel-gfx] [PATCH v4 0/4] Handle dma fences in dirtyfb ioctl

2023-09-01 Thread Ville Syrjälä
On Fri, Sep 01, 2023 at 12:34:56PM +0300, Jouni Högander wrote: > Currently i915 dirtyfb ioctl is not taking dma fences into > account. This works with features like FBC, PSR, DRRS because our gem > code is triggering flush again when rendering completes. We are > targeting in getting rid of

Re: [Intel-gfx] [PATCH] drm/i915: Use vblank worker to unpin old legacy cursor fb safely

2023-09-01 Thread Ville Syrjälä
On Fri, Sep 01, 2023 at 12:16:21PM +0200, Maarten Lankhorst wrote: > Hey, > > > Den 2023-08-31 kl. 18:26, skrev Ville Syrjala: > > From: Ville Syrjälä > > > > The cursor hardware only does sync updates, and thus the hardware > > will be scanning out from the old fb until the next start of

Re: [Intel-gfx] [PATCH] drm/i915/dsi: let HW maintain HS-TRAIL and CLK_POST

2023-09-01 Thread Ville Syrjälä
On Fri, Sep 01, 2023 at 05:51:00PM +0800, William Tseng wrote: > This change is to adjust TEOT timing and TCLK-POST timing so DSI > signaling can meet CTS specification. > > For clock lane, the measured TEOT may be changed from 142.64 ns to > 107.36 ns, which is less than (105 ns+12*UI) and is

Re: [Intel-gfx] [PATCH] drm/i915/dsi: let HW maintain HS-TRAIL and CLK_POST

2023-09-01 Thread Jani Nikula
On Fri, 01 Sep 2023, William Tseng wrote: > This change is to adjust TEOT timing and TCLK-POST timing so DSI > signaling can meet CTS specification. > > For clock lane, the measured TEOT may be changed from 142.64 ns to > 107.36 ns, which is less than (105 ns+12*UI) and is conformed to > mipi

Re: [Intel-gfx] [PATCH] drm/i915: Use vblank worker to unpin old legacy cursor fb safely

2023-09-01 Thread Maarten Lankhorst
Hey, Den 2023-08-31 kl. 18:26, skrev Ville Syrjala: From: Ville Syrjälä The cursor hardware only does sync updates, and thus the hardware will be scanning out from the old fb until the next start of vblank. So in order to make the legacy cursor fastpath actually safe we should not unpin the

[Intel-gfx] [PATCH] drm/i915/dsi: let HW maintain HS-TRAIL and CLK_POST

2023-09-01 Thread William Tseng
This change is to adjust TEOT timing and TCLK-POST timing so DSI signaling can meet CTS specification. For clock lane, the measured TEOT may be changed from 142.64 ns to 107.36 ns, which is less than (105 ns+12*UI) and is conformed to mipi D-PHY v1.2 CTS v1.0. As to TCLK-POST, it may be changed

[Intel-gfx] [PATCH v4 4/4] drm/i915: Handle dma fences in dirtyfb callback

2023-09-01 Thread Jouni Högander
Take into account dma fences in dirtyfb callback. If there is no unsignaled dma fences perform flush immediately. If there are unsignaled dma fences perform invalidate and add callback which will queue flush when the fence gets signaled. v4: - Move invalidate before callback is added v3: -

[Intel-gfx] [PATCH v4 3/4] drm/i915: Add new frontbuffer tracking interface to queue flush

2023-09-01 Thread Jouni Högander
We want to wait dma fences in dirtyfb ioctl. As we don't want to make dirtyfb ioctl as blocking call we need to use dma_fence_add_callback. Callback used for dma_fence_add_callback is called from atomic context. Due to this we need to add a new frontbuffer tracking interface to queue flush. v3:

[Intel-gfx] [PATCH v4 2/4] drm/i915/psr: Clear frontbuffer busy bits on flip

2023-09-01 Thread Jouni Högander
We are planning to move flush performed from work queue. This means it is possible to have invalidate -> flip -> flush sequence. Handle this by clearing possible busy bits on flip. Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_psr.c | 6 ++ 1 file changed, 6

[Intel-gfx] [PATCH v4 1/4] drm/i915/fbc: Clear frontbuffer busy bits on flip

2023-09-01 Thread Jouni Högander
We are planning to move flush performed from work queue. This means it is possible to have invalidate -> flip -> flush sequence. Handle this by clearing possible busy bits on flip. Signed-off-by: Ville Syrjälä Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_fbc.c | 6

[Intel-gfx] [PATCH v4 0/4] Handle dma fences in dirtyfb ioctl

2023-09-01 Thread Jouni Högander
Currently i915 dirtyfb ioctl is not taking dma fences into account. This works with features like FBC, PSR, DRRS because our gem code is triggering flush again when rendering completes. We are targeting in getting rid of frontbuffer tracking code: Flusing hook from gem code will be removed as

Re: [Intel-gfx] [PATCH 0/6] drm, cec and edid updates

2023-09-01 Thread Jani Nikula
On Fri, 01 Sep 2023, Maxime Ripard wrote: > On Thu, Aug 31, 2023 at 09:51:24PM +0300, Jani Nikula wrote: >> On Thu, 24 Aug 2023, Jani Nikula wrote: >> > Avoid accessing the raw edid directly. Pre-parse the source physical >> > address during normal EDID parsing and use that for CEC. >> > >> >

Re: [Intel-gfx] [PATCH v5 4/9] drm/i915: Eliminate IS_MTL_GRAPHICS_STEP

2023-09-01 Thread Jani Nikula
On Thu, 31 Aug 2023, Matt Roper wrote: > On Thu, Aug 31, 2023 at 07:16:55PM +0300, Jani Nikula wrote: >> On Mon, 21 Aug 2023, Matt Roper wrote: >> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c >> > b/drivers/gpu/drm/i915/display/skl_universal_plane.c >> > index

[Intel-gfx] ✓ Fi.CI.IGT: success for WQ_UNBOUND warning since recent workqueue refactoring

2023-09-01 Thread Patchwork
== Series Details == Series: WQ_UNBOUND warning since recent workqueue refactoring URL : https://patchwork.freedesktop.org/series/123134/ State : success == Summary == CI Bug Log - changes from CI_DRM_13583_full -> Patchwork_123134v1_full

Re: [Intel-gfx] [PATCH 0/2] Fix HDCP2 capability check

2023-09-01 Thread Shankar, Uma
> -Original Message- > From: Kandpal, Suraj > Sent: Wednesday, August 30, 2023 1:05 PM > To: intel-gfx@lists.freedesktop.org > Cc: Nautiyal, Ankit K ; Shankar, Uma > ; Murthy, Arun R ; Kandpal, > Suraj > Subject: [PATCH 0/2] Fix HDCP2 capability check > > In DP MST scenarios we

Re: [Intel-gfx] [PATCH 0/6] drm, cec and edid updates

2023-09-01 Thread Maxime Ripard
On Thu, Aug 31, 2023 at 09:51:24PM +0300, Jani Nikula wrote: > On Thu, 24 Aug 2023, Jani Nikula wrote: > > Avoid accessing the raw edid directly. Pre-parse the source physical > > address during normal EDID parsing and use that for CEC. > > > > Jani Nikula (6): > > drm/edid: add

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gvt: Use list_for_each_entry() helper

2023-09-01 Thread Patchwork
== Series Details == Series: drm/i915/gvt: Use list_for_each_entry() helper URL : https://patchwork.freedesktop.org/series/123133/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13583_full -> Patchwork_123133v1_full Summary

[Intel-gfx] [PULL] drm-misc-next-fixes

2023-09-01 Thread Thomas Zimmermann
Hi Dave and Daniel, here are two more fixes that have been sitting in drm-misc-next-fixes. Best regards Thomas drm-misc-next-fixes-2023-09-01: Short summary of fixes pull: * ivpu: Replace strncpy * nouveau: Fix fence state in nouveau_fence_emit() The following changes since commit

[Intel-gfx] [PATCH] drm/display/dp: Add the remaining Square PHY patterns DPCD register definitions

2023-09-01 Thread Khaled Almahallawy
DP Scope may send requests for all Square PHY pattern configuration during automation. Add them instead of failing these tests. Cc: Jani Nikula Cc: Lee Shawn C Signed-off-by: Khaled Almahallawy --- include/drm/display/drm_dp.h | 3 +++ 1 file changed, 3 insertions(+) diff --git

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/guc: Update GUC_KLV_0_KEY definition

2023-09-01 Thread Patchwork
== Series Details == Series: drm/i915/guc: Update GUC_KLV_0_KEY definition URL : https://patchwork.freedesktop.org/series/123130/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13583_full -> Patchwork_123130v1_full Summary