John Beard kirjoitti 26/06/18 klo 01:35:
> Ideally, there would be tests on that interface to ensure the parser catches
> malformed data, particularly when that data is shown to cause defects though
> bug reports.
Considering this is a vector for polluting design files with anything
unless one
Hey Andrzej,
This makes sense now. SnapEDA should have already resolved this issue.
They contacted me at the end of April about this problem and I explained
the problem with their NPTH generation. If they are still producing
footprints with NPTHs that do not have any layers defined, I will ping
Hi,
I think with this kind of thing, KiCad should be strict with what it will
accept. Otherwise you might find people rely on broken or undefined behaviour
and de facto defaults and it all goes wrong when it's fixed or changed on
KiCad's end in future. That's how you get "quirks modes".
Hi,
if by submitter you mean me, then this is a board I found on Github, I
don't know if it was manually edited.
But I have done a little investigation, and I think I've found the
source of this problem.
The problematic footprint is identical to the one that can be downloaded
from SnapEDA:
Hey Seth,
I would agree with you if this was our error. If I'm reading JP's
analysis correctly, he could not create this board error using KiCad so
I'm working on the assumption that this was not our board file output
formatter causing the problem. Using defensive measures such as
assertions
Hi Wayne-
I would view this patch more as defensive coding than trying to fix others'
errors. The alternatives are to refuse to parse the file or (as we
currently do) parse as written and encounter errors in display and
routing. JP's approach provides a clear and predictable response to a
On 6/25/2018 8:12 AM, jp charras wrote:
> Le 24/06/2018 à 21:52, Wayne Stambaugh a écrit :
>> Are we planning on fixing this for rc3? If so, what is required. I'm fine
>> with waiting a day or
>> two to tag rc3.
>>
>
> Attached a possible fix.
>
> The board test file shows really broken layer
Le 24/06/2018 à 21:52, Wayne Stambaugh a écrit :
> Are we planning on fixing this for rc3? If so, what is required. I'm fine
> with waiting a day or
> two to tag rc3.
>
Attached a possible fix.
The board test file shows really broken layer set in a few pads:
- no layers for some pads (the
Are we planning on fixing this for rc3? If so, what is required. I'm
fine with waiting a day or two to tag rc3.
On 06/23/2018 04:42 PM, Seth Hillbrand wrote:
Andrzej-
I would prefer that this be fixed when reading the malformed file, not
displaying. We fix it there, the display issue
Andrzej-
I would prefer that this be fixed when reading the malformed file, not
displaying. We fix it there, the display issue goes away. This also
protects from unintended side effects rather than trying to code work
arounds for a malformed board in multiple parts of the code.
-S
Am Sa.,
When you generate gerbers from a valid NPTH pad with hole size = pad
size, there will be no shape plotted on copper layers, so in my opinion,
this pad does not exist on copper layers. But this is more philosophical
discussion :)
Regarding clearance for router, you could just take the merged
Is this malformed pad actually caused by KiCad or is it possible this
was cause by a script or manual editing? If it was caused by KiCad then
we need to figure out how this was allowed to happen and fix it.
Wayne
On 06/23/2018 02:54 AM, jp charras wrote:
> Le 22/06/2018 à 21:54, Andrzej Wolski
Le 22/06/2018 à 21:54, Andrzej Wolski a écrit :
> No, this IS an error in the board :)
> If you open pad properties and click OK, it won't let you save it as is, you
> will have to enable
> copper layers.
> NPTH pads also HAVE TO exists on copper layers (I don't understand why, but
> they do).
OK, thank you. You are right. I see the difference now. I was deleting
the layer tag to test it. The board has the layer tag but it is empty. I
also confirm the error you mention.
But I'm still not sure about the patch's approach. I think I am in
agreement with JP here that the correct way
Ah. This is not an error in the board. This is just an NPTH. If you
click on it in GAL, you will see it.
I think the correct patch to this should check the pad type instead of
drawing one with no layers.
-S
Am Fr., 22. Juni 2018 um 12:33 Uhr schrieb Andrzej Wolski <
awolski.ki...@gmail.com>:
No, this IS an error in the board :)
If you open pad properties and click OK, it won't let you save it as is,
you will have to enable copper layers.
NPTH pads also HAVE TO exists on copper layers (I don't understand why,
but they do).
Also, as I already mentioned, current GAL behavior is
IIRC you have to leave (layers) to reproduce this.
This is a board where I found the issue:
https://github.com/mntmn/reform/blob/master/electronics/reform-motherboard.kicad_pcb
There are two mPCIE connectors in the center, they have NPTH alignment
holes, you can see them in legacy mode.
Those pads are shown in 4.0 GAL and in 5.0 legacy, only 5.0 GAL has this
problem, so to me this is a regression fix rather than workaround.
Fixing those pads may be a good idea, but that is another matter.
Andrzej
W dniu 2018-06-22 o 20:03, jp charras pisze:
Le 22/06/2018 à 19:51, Andrzej
Andrzej-
I just tested this, editing a file to remove the layers from a pad and
KiCad automatically adds the pad back to all copper layers. I see the pad
in pcbnew and can edit it.
Can you provide a board that demonstrates the issue? Maybe it was only the
test board I used?
-S
Am Fr., 22.
Le 22/06/2018 à 19:51, Andrzej Wolski a écrit :
> Hi Seth,
>
> current behavior is that malformed pad holes are always hidden, so you can't
> see on the screen
> something that exists on your PCB and will be plotted in drill files. This
> patch makes those holes
> visible.
>
> Andrzej
OK,
Hi Seth,
current behavior is that malformed pad holes are always hidden, so you
can't see on the screen something that exists on your PCB and will be
plotted in drill files. This patch makes those holes visible.
Andrzej
W dniu 2018-06-22 o 17:46, Seth Hillbrand pisze:
Andrzej-
Can you
Andrzej-
Can you explain the issue that this patch addresses? I read the commit
message but it looks like malformed pads (GetLayerSet().any() == 0) are no
longer hidden. This seems counter-intuitive but maybe I'm just not seeing
the problem.
Thanks!
Seth
Am Fr., 22. Juni 2018 um 03:57 Uhr
From d82e05f3328c95cb4443af7a2c0040ff1766fc96 Mon Sep 17 00:00:00 2001
From: Andrzej Wolski
Date: Fri, 22 Jun 2018 12:07:56 +0200
Subject: [PATCH] GAL: Draw hole even if pad has no layer
While pcbnew does not allow to create THT pad without a copper layer,
there are boards that somehow have
23 matches
Mail list logo
