Il 30/04/24 03:15, Olivia Wen ha scritto:
Add an IPI command definition for communication with IMGSYS through
SCP mailbox.
Signed-off-by: Olivia Wen
Reviewed-by: AngeloGioacchino Del Regno
Il 24/04/24 12:02, AngeloGioacchino Del Regno ha scritto:
Il 24/04/24 05:03, Olivia Wen ha scritto:
Integrate the imgsys core architecture driver for image processing on
the MT8188 platform.
Signed-off-by: Olivia Wen
This should be reordered before introducing the 8188 scp core 1 support
.
With that reordered,
Reviewed-by: AngeloGioacchino Del Regno
---
include/linux/remoteproc/mtk_scp.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/remoteproc/mtk_scp.h
b/include/linux/remoteproc/mtk_scp.h
index 7c2b7cc9..344ff41 100644
--- a/include/linux/remoteproc
Il 24/04/24 05:03, Olivia Wen ha scritto:
The SCP on different chips will require different DRAM sizes and IPI
shared buffer sizes based on varying requirements.
Signed-off-by: Olivia Wen
Reviewed-by: AngeloGioacchino Del Regno
Il 24/04/24 05:03, Olivia Wen ha scritto:
MT8188 SCP has two RISC-V cores which is similar to MT8195 but without
L1TCM. We've added MT8188-specific functions to configure L1TCM in
multicore setups.
Signed-off-by: Olivia Wen
Reviewed-by: AngeloGioacchino Del Regno
erent code and IPI share buffer sizes.
Introducing a structure mtk_scp_sizes_data to handle them.
Signed-off-by: olivia.wen
Reviewed-by: AngeloGioacchino Del Regno
Il 19/04/24 10:42, Olivia Wen ha scritto:
From: "olivia.wen"
Under different applications, the MT8188 SCP can be used as single-core
or dual-core.
Signed-off-by: olivia.wen
Reviewed-by: AngeloGioacchino Del Regno
Il 19/04/24 10:42, Olivia Wen ha scritto:
From: "olivia.wen"
Under different applications, the MT8188 SCP can be used as single-core
or dual-core.
Signed-off-by: olivia.wen
Reviewed-by: AngeloGioacchino Del Regno
Il 11/04/24 09:34, AngeloGioacchino Del Regno ha scritto:
Il 11/04/24 05:37, olivia.wen ha scritto:
Under different applications, the MT8188 SCP can be used as single-core
or dual-core.
Signed-off-by: olivia.wen
---
Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml | 3 ++-
1 file
:
- mediatek,mt8192-scp
- mediatek,mt8195-scp
- mediatek,mt8195-scp-dual
-
Don't remove the blank line, it's there for readability.
+ - mediatek,mt8188-scp-dual
After addressing that comment,
Reviewed-by: AngeloGioacchino Del Regno
reg:
description
Il 11/04/24 05:37, olivia.wen ha scritto:
To Support MT8188 SCP core 1 for ISP driver.
The SCP on different chips will require different code sizes
and IPI buffer sizes based on varying requirements.
Signed-off-by: olivia.wen
---
drivers/remoteproc/mtk_common.h| 5 +--
Il 08/04/24 21:32, Luca Weiss ha scritto:
Add compatible for the Qualcomm MSM8974 APCS block.
Signed-off-by: Luca Weiss
Reviewed-by: AngeloGioacchino Del Regno
-io-ctrl',
'ti,am654-serdes-ctrl', 'ti,j784s4-pcie-ctrl']
from schema $id: http://devicetree.org/schemas/mfd/syscon.yaml#
Signed-off-by: Luca Weiss
Reviewed-by: AngeloGioacchino Del Regno
Il 02/04/24 16:23, Mathieu Poirier ha scritto:
On Tue, 2 Apr 2024 at 03:56, AngeloGioacchino Del Regno
wrote:
Il 28/03/24 15:38, Mathieu Poirier ha scritto:
On Wed, Mar 27, 2024 at 01:49:58PM +0100, AngeloGioacchino Del Regno wrote:
Il 21/03/24 16:27, Mathieu Poirier ha scritto:
On Thu
Il 28/03/24 15:38, Mathieu Poirier ha scritto:
On Wed, Mar 27, 2024 at 01:49:58PM +0100, AngeloGioacchino Del Regno wrote:
Il 21/03/24 16:27, Mathieu Poirier ha scritto:
On Thu, Mar 21, 2024 at 09:46:14AM +0100, AngeloGioacchino Del Regno wrote:
When probing multi-core SCP, this driver
Il 21/03/24 16:27, Mathieu Poirier ha scritto:
On Thu, Mar 21, 2024 at 09:46:14AM +0100, AngeloGioacchino Del Regno wrote:
When probing multi-core SCP, this driver is parsing all sub-nodes of
the scp-cluster node, but one of those could be not an actual SCP core
and that would make the entire
Il 21/03/24 16:25, Mathieu Poirier ha scritto:
Good day,
On Thu, Mar 21, 2024 at 09:46:13AM +0100, AngeloGioacchino Del Regno wrote:
The IPI buffer location is read from the firmware that we load to the
System Companion Processor, and it's not granted that both the SRAM
(L2TCM) size
only available subnodes having compatible "mediatek,scp-core".
Fixes: 1fdbf0cdde98 ("remoteproc: mediatek: Probe SCP cluster on multi-core
SCP")
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/remoteproc/mtk_scp.c | 3 +++
1 file changed, 3 insertions(+)
diff --git
at
all, if this is single core).
Fixes: 3efa0ea743b7 ("remoteproc/mediatek: read IPI buffer offset from FW")
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/remoteproc/mtk_scp.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/remoteproc/m
risks which I believe I really don't need to
describe, leaving it to the reader's imagination :-)
Please note that the first fix is URGENT.
P.S.: Of course, this was tested OK on multiple MTK platforms.
AngeloGioacchino Del Regno (2):
remoteproc: mediatek: Make sure IPI buffer fits in L2TCM
:
The devicetree schema core defines firmware-name as a string-array:
remove the override and narrow the number of expected file names to 1.
Besides,
Reviewed-by: AngeloGioacchino Del Regno
---
Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml | 4 ++--
.../devicetree/bindings
Il 10/01/24 20:16, Konrad Dybcio ha scritto:
On 1/9/24 12:24, Luca Weiss wrote:
On Tue Jan 9, 2024 at 11:09 AM CET, Konrad Dybcio wrote:
On 1/5/24 15:54, Luca Weiss wrote:
Configure the thermals for the PA_THERM1, MSM_THERM, PA_THERM0,
RFC_CAM_THERM, CAM_FLASH_THERM and QUIET_THERM
Reviewed-by: AngeloGioacchino Del Regno
Il 20/09/23 17:03, Laura Nao ha scritto:
On 9/19/23 11:23, AngeloGioacchino Del Regno wrote:
In older devicetrees we had the ChromeOS EC in a node called "cros-ec"
instead of the newer "cros-ec-rpmsg", but this driver is now checking
only for the latter, breaking comp
Il 19/09/23 07:03, Chen-Yu Tsai ha scritto:
In the just landed multi-core SCP work, detection of single/multi core
SCP is done by checking the immediate child node of the SCP complex
device node. In the original work this was done by matching the child
node's name. However the name wasn't
through the children of the main SCP node and checking if
if there's more than one "mediatek,scp-core" compatible node.
Fixes: 1fdbf0cdde98 ("remoteproc: mediatek: Probe SCP cluster on multi-core
SCP")
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/remoteproc/mtk_scp.c |
Il 19/04/21 20:52, Bjorn Andersson ha scritto:
On Tue 19 Jan 11:45 CST 2021, AngeloGioacchino Del Regno wrote:
On new SoCs (SDM845 onwards) the Operating State Manager (OSM) is
being programmed in the bootloader and write-protected by the
hypervisor, leaving to the OS read-only access to some
Il 12/04/21 10:36, Arend van Spriel ha scritto:
On 07-03-2021 12:35, Konrad Dybcio wrote:
Add support for BCM43596 dual-band AC chip, found in
SONY Xperia X Performance, XZ and XZs smartphones (and
*possibly* other devices from other manufacturers).
The chip doesn't require any special handling
e block really needs
recovery, this "trick" won't save anyone and the recovery will anyway be
triggered, as the PP-done will anyway timeout.
Suggested-by: AngeloGioacchino Del Regno
Signed-off-by: Marijn Suijten
Reviewed-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/dis
Il 02/04/21 08:59, Manaf Meethalavalappu Pallikunhi ha scritto:
Add SDPM clock monitor driver, which will register for clock rate
change notification and write the clock rate into SDPM CSR register.
Signed-off-by: Ram Chandrasekar
Signed-off-by: Manaf Meethalavalappu Pallikunhi
---
Il 12/02/21 10:24, Amit Pundir ha scritto:
Hi,
On Thu, 11 Feb 2021 at 00:25, AngeloGioacchino Del Regno
wrote:
Il 10/02/21 09:18, Amit Pundir ha scritto:
From: Sumit Semwal
Enabling the Display panel for beryllium requires DSI
labibb regulators and panel dts nodes to be added.
It is also
Il 11/02/21 21:27, Alex Elder ha scritto:
On 2/11/21 11:50 AM, AngeloGioacchino Del Regno wrote:
Hey all!
This time around I thought that it would be nice to get some modem
action going on. We have it, it's working (ish), so just.. why not.
Thank you for the patches!
I would like to review
Il 11/02/21 21:19, Stephen Boyd ha scritto:
Quoting AngeloGioacchino Del Regno (2021-01-13 10:38:13)
The function clk_gfx3d_determine_rate is selecting different PLLs
to manage the GFX3D clock source in a special way: this one needs
to be ping-pong'ed on different PLLs to ensure stability
MSM8998 features IPA v3.1 (GSI v1.0): add the required configuration
data for it.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/net/ipa/Makefile | 3 +-
drivers/net/ipa/ipa_data-msm8998.c | 407 +
drivers/net/ipa/ipa_data.h | 5
On IPAv3.1 there is no such FLAVOR_0 register so it is impossible
to read tx/rx channel masks and we have to rely on the correctness
on the provided configuration.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/net/ipa/ipa_endpoint.c | 9 +
1 file changed, 9 insertions(+)
diff
interrupts.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/net/ipa/gsi.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ipa/gsi.c b/drivers/net/ipa/gsi.c
index 6315336b3ca8..b5460cbb085c 100644
--- a/drivers/net/ipa/gsi.c
+++ b/drivers/net/ipa/gsi.c
is up.
This was tested on the F(x)Tec Pro 1 (MSM8998) smartphone.
AngeloGioacchino Del Regno (7):
net: ipa: Add support for IPA v3.1 with GSI v1.0
net: ipa: endpoint: Don't read unexistant register on IPAv3.1
net: ipa: gsi: Avoid some writes during irq setup for older IPA
net: ipa: gsi: Use
In preparation for adding support for the MSM8998 SoC's IPA,
add the necessary bits for IPA version 3.1 featuring GSI 1.0,
found on at least MSM8998.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/net/ipa/gsi.c | 8
drivers/net/ipa/ipa_endpoint.c | 17
MSM8998 support has been added: document the new compatible.
Signed-off-by: AngeloGioacchino Del Regno
---
Documentation/devicetree/bindings/net/qcom,ipa.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/net/qcom,ipa.yaml
b/Documentation/devicetree
In GSI v1.0 the register GSI_HW_PARAM_2_OFFSET has different layout
so the number of channels and events per EE are, of course, laid out
in 8 bits each (0-7, 8-15 respectively).
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/net/ipa/gsi.c | 16 +---
drivers/net/ipa
The driver supports SC7180, but the binding was not documented.
Just add it.
Signed-off-by: AngeloGioacchino Del Regno
---
Documentation/devicetree/bindings/net/qcom,ipa.yaml | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/net/qcom
Il 10/02/21 09:18, Amit Pundir ha scritto:
From: Sumit Semwal
Enabling the Display panel for beryllium requires DSI
labibb regulators and panel dts nodes to be added.
It is also required to keep some of the regulators as
always-on.
Signed-off-by: Sumit Semwal
Signed-off-by: Amit Pundir
---
Il 08/02/21 19:18, Stephen Boyd ha scritto:
Quoting AngeloGioacchino Del Regno (2021-01-14 14:10:53)
The GPU IOMMU depends on this clock and the hypervisor will crash
the SoC if this clock gets disabled because the secure contexts
that have been set on this IOMMU by the bootloader will become
Il 08/02/21 19:21, Stephen Boyd ha scritto:
Quoting AngeloGioacchino Del Regno (2021-01-14 14:10:55)
The pixel and byte clocks rate should not be cached, as a VCO shutdown
may clear the frequency setup and this may not be set again due to the
cached rate being present.
This will also be useful
Il 08/02/21 19:24, Stephen Boyd ha scritto:
Quoting AngeloGioacchino Del Regno (2021-01-14 14:10:59)
The GPU PLL0 is not a fixed PLL and the rate can be set on it:
this is necessary especially on boards which bootloader is setting
a very low rate on this PLL before booting Linux, which would
Il 05/02/21 22:51, Rob Herring ha scritto:
On Thu, Jan 21, 2021 at 08:52:50PM +0100, AngeloGioacchino Del Regno wrote:
The OSM programming addition has been done under the
qcom,cpufreq-hw-8998 compatible name: specify the requirement
of two additional register spaces for this functionality
Il 05/02/21 22:46, Rob Herring ha scritto:
On Thu, Jan 21, 2021 at 08:52:46PM +0100, AngeloGioacchino Del Regno wrote:
From: Manivannan Sadhasivam
Add devicetree documentation for 'qcom,freq-domain' property specific
to Qualcomm CPUs. This property is used to reference the CPUFREQ node
along
Il 02/02/21 19:45, Rob Clark ha scritto:
On Tue, Feb 2, 2021 at 6:32 AM AngeloGioacchino Del Regno
wrote:
Il 01/02/21 18:31, Rob Clark ha scritto:
On Mon, Feb 1, 2021 at 9:18 AM Rob Clark wrote:
On Mon, Feb 1, 2021 at 9:05 AM Rob Clark wrote:
On Mon, Feb 1, 2021 at 7:47 AM Rob Clark
Il 02/02/21 08:36, Matti Vaittinen ha scritto:
If a spurious OCP IRQ occurs the isr schedules delayed work
but does not disable the IRQ. The delayed work assumes IRQ was
disabled in handler and attempts enabling it again causing
unbalanced enable.
You break the logic like this. Though, I also
.
It didn't deadlock, but looking at it again -- oh my, I agree with you.
Reviewed-by: AngeloGioacchino Del Regno
Fixes: 390af53e04114 ("regulator: qcom-labibb: Implement short-circuit and
over-current IRQs")
Signed-off-by: Matti Vaittinen
---
This fix is done purely based on co
Il 01/02/21 18:31, Rob Clark ha scritto:
On Mon, Feb 1, 2021 at 9:18 AM Rob Clark wrote:
On Mon, Feb 1, 2021 at 9:05 AM Rob Clark wrote:
On Mon, Feb 1, 2021 at 7:47 AM Rob Clark wrote:
On Mon, Feb 1, 2021 at 2:11 AM AngeloGioacchino Del Regno
wrote:
Il 31/01/21 20:50, Rob Clark ha
Il 31/01/21 20:50, Rob Clark ha scritto:
On Sat, Jan 9, 2021 at 5:51 AM AngeloGioacchino Del Regno
wrote:
The VCO rate was being miscalculated due to a big overlook during
the process of porting this driver from downstream to upstream:
here we are really recalculating the rate of the VCO
Il 29/01/21 10:14, Matti Vaittinen ha scritto:
On Thu, 2021-01-28 at 12:10 +, Mark Brown wrote:
On Thu, Jan 28, 2021 at 09:23:08AM +, Vaittinen, Matti wrote:
On Wed, 2021-01-27 at 16:32 +, Mark Brown wrote:
Note that the events the API currently has are expected to be for
the
Il 28/01/21 10:13, Wolfram Sang ha scritto:
+ qcom,noise-reject-sda:
+$ref: /schemas/types.yaml#/definitions/uint32
+description: Noise rejection level for the SDA line.
+minimum: 0
+maximum: 3
+default: 0
What does this u32 describe? I wonder if we can introduce a
Il 27/01/21 13:56, Matti Vaittinen ha scritto:
Hello Mark,
Hey Matti, hey Mark!
Nice to hear from you. :)
On Wed, 2021-01-27 at 12:27 +, Mark Brown wrote:
On Wed, Jan 27, 2021 at 12:01:55PM +, Vaittinen, Matti wrote:
Anyways - I was wondering if this is common thing amongst many
Il 26/01/21 14:39, Stanimir Varbanov ha scritto:
On 1/13/21 8:38 PM, AngeloGioacchino Del Regno wrote:
From: Martin Botka
Add a driver for the multimedia clock controller found on SDM660
based devices. This should allow most multimedia device drivers
to probe and control their clocks
->fwname;
+
+ ret = venus_load_fw(core, fwpath, _phys, _size);
if (ret) {
dev_err(dev, "fail to load video firmware\n");
return -EINVAL;
Super! As you surely know, I totally agree.
It may not have huge value, but:
Reviewed-By: AngeloGioacchino Del Regno
Add bindings for the Awinic AW9523/AW9523B I2C GPIO Expander driver.
Signed-off-by: AngeloGioacchino Del Regno
---
.../pinctrl/awinic,aw9523-pinctrl.yaml| 139 ++
1 file changed, 139 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/awinic
Add bindings for the Awinic AW9523/AW9523B I2C GPIO Expander driver.
Signed-off-by: AngeloGioacchino Del Regno
---
.../pinctrl/awinic,aw9523-pinctrl.yaml| 139 ++
1 file changed, 139 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/awinic
to
advertise this to an external interrupt controller.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/pinctrl/Kconfig | 17 +
drivers/pinctrl/Makefile |1 +
drivers/pinctrl/pinctrl-aw9523.c | 1122 ++
3 files changed, 1140 insertions(+)
create
to
advertise this to an external interrupt controller.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/pinctrl/Kconfig | 17 +
drivers/pinctrl/Makefile |1 +
drivers/pinctrl/pinctrl-aw9523.c | 1122 ++
3 files changed, 1140 insertions(+)
create
Il 25/01/21 11:40, Hans Verkuil ha scritto:
On 18/01/2021 18:45, AngeloGioacchino Del Regno wrote:
Il 18/01/21 18:21, Stanimir Varbanov ha scritto:
Hi Angelo,
Thanks for the patch!
On 1/15/21 8:52 PM, AngeloGioacchino Del Regno wrote:
Add the SDM660 DT compatible and its resource structure
Il 22/01/21 10:46, Viresh Kumar ha scritto:
On 21-01-21, 20:52, AngeloGioacchino Del Regno wrote:
**
** NOTE: To "view the full picture", please look at the following
** patch series:
** https://patchwork.kernel.org/project/linux-arm-msm/list/?ser
Il 22/01/21 10:59, Linus Walleij ha scritto:
On Mon, Jan 18, 2021 at 3:38 PM AngeloGioacchino Del Regno
wrote:
By the way, this is really LEVEL irq, not EDGE... To avoid any
misunderstanding, I think that the best way to show you what I
am seeing is to just copy-paste the relevant piece from
From: Manivannan Sadhasivam
Add devicetree documentation for 'qcom,freq-domain' property specific
to Qualcomm CPUs. This property is used to reference the CPUFREQ node
along with Domain ID (0/1).
Signed-off-by: Manivannan Sadhasivam
Signed-off-by: AngeloGioacchino Del Regno
zle pieces, and they're also (basically) fully
accessible, which means that the OS must do it in order to get in the
same state as the newer ones and to get the entire scaling hardware to
start rolling.
AngeloGioacchino Del Regno (5):
cpufreq: blacklist SDM630/636/660 in cpufreq-dt-platdev
cpu
The OSM programming addition has been done under the
qcom,cpufreq-hw-8998 compatible name: specify the requirement
of two additional register spaces for this functionality.
This implementation, with the same compatible, has been
tested on MSM8998 and SDM630.
Signed-off-by: AngeloGioacchino Del
In order to fine-tune the frequency scaling from various governors,
allow to set a maximum transition latency from OPPs, which may be
different depending on the SoC.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/cpufreq/qcom-cpufreq-hw.c | 7 +++
1 file changed, 7 insertions
From: Manivannan Sadhasivam
Convert Qualcomm cpufreq devicetree binding to YAML.
Signed-off-by: Manivannan Sadhasivam
Signed-off-by: AngeloGioacchino Del Regno
---
.../bindings/cpufreq/cpufreq-qcom-hw.txt | 172 ---
.../bindings/cpufreq/cpufreq-qcom-hw.yaml | 204
support CPU scaling on SDM630
and MSM8998.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/cpufreq/qcom-cpufreq-hw.c | 1244 -
1 file changed, 1212 insertions(+), 32 deletions(-)
diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c
b/drivers/cpufreq/qcom-c
Add the MSM8998 to the blacklist since the CPU scaling is handled
out of this.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c
b/drivers/cpufreq/cpufreq-dt-platdev.c
Add the SDM630, SDM636 and SDM660 to the blacklist since the CPU
scaling is handled out of this.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/cpufreq/cpufreq-dt-platdev.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c
b/drivers/cpufreq
Add the bindings for the CPR3 driver to the documentation.
Signed-off-by: AngeloGioacchino Del Regno
---
.../bindings/soc/qcom/qcom,cpr3.yaml | 241 ++
1 file changed, 241 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml
diff
Add maintainers entry for the Qualcomm CPR3/CPR4/CPRh driver.
Signed-off-by: AngeloGioacchino Del Regno
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 3f50d126dfcc..5c458052dbf4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14684,6
range of SoCs,
from the mid-range to the high end ones including, but not limited
to, MSM8953/8996/8998, SDM630/636/660/845.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/soc/qcom/Kconfig | 17 +
drivers/soc/qcom/Makefile |1 +
drivers/soc/qcom/cpr-common.c | 35
30)
- Sony Xperia 10 (SDM630)
- Sony Xperia XZ Premium (MSM8998)
- F(x)Tec Pro 1 (MSM8998)
AngeloGioacchino Del Regno (3):
soc: qcom: Add support for Core Power Reduction v3, v4 and Hardened
MAINTAINERS: Add entry for Qualcomm CPRv3/v4/Hardened driver
dt-bindings: soc: qcom:
2.039337] msm_fbdev_init+0x80/0xe0
[2.039735] msm_drm_bind+0x4d8/0x6d0
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/drm_modes.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index 33fb2f05ce66..dd
t is "special" while, in reality... it's.. not.
It's just the same HW, after all.
On 1/19/2021 11:15 PM, AngeloGioacchino Del Regno wrote:
On new SoCs (SDM845 onwards) the Operating State Manager (OSM) is
being programmed in the bootloader and write-protected by the
hypervisor,
; +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/media/qcom,sdm660-camss.yaml#;
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#;
> +
> +title: Qualcomm CAMSS ISP
> +
> +maintainers:
If you wa
Il 11/01/21 13:04, Sai Prakash Ranjan ha scritto:
A6XX GPUs have support for last level cache(LLC) also known
as system cache and need to set the bus attributes to
use it. Currently we use a generic adreno iommu address space
implementation which are also used by older GPU generations
which do
Il 20/01/21 08:47, Taniya Das ha scritto:
There are intermittent GDSC power-up failures observed for titan top
gdsc, which requires the XO clock. Thus mark all the MM XO clocks always
enabled from probe.
Hello Tanya,
Fixes: 8d4025943e13 ("clk: qcom: camcc-sc7180: Use runtime PM ops instead
Il 20/01/21 00:17, Rob Herring ha scritto:
On Fri, Jan 15, 2021 at 07:52:52PM +0100, AngeloGioacchino Del Regno wrote:
Add new qcom,sdm660-venus DT binding schema.
Signed-off-by: AngeloGioacchino Del Regno
---
.../bindings/media/qcom,sdm660-venus.yaml | 164 ++
1 file
Document properties to configure soft start and discharge resistor
for LAB and IBB respectively.
Signed-off-by: AngeloGioacchino Del Regno
Reviewed-by: Bjorn Andersson
---
.../bindings/regulator/qcom-labibb-regulator.yaml | 10 ++
1 file changed, 10 insertions(+)
diff --git
The LAB and IBB regulator have just one range and it is useless
to use linear_range ops, as these are used to express multiple
linear ranges.
Switch list_voltage and map_voltage callbacks to *_linear instead.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/regulator/qcom-labibb
less check for ocp_irq_requested
- Fixed issues with YAML documentation
AngeloGioacchino Del Regno (7):
regulator: qcom-labibb: Switch voltage ops from linear_range to linear
regulator: qcom-labibb: Implement current limiting
regulator: qcom-labibb: Implement pull-down, softstart, active
disc
when the regulators are disabled (random voltage spikes etc).
Signed-off-by: AngeloGioacchino Del Regno
Reviewed-by: Bjorn Andersson
---
drivers/regulator/qcom-labibb-regulator.c | 94 +++
1 file changed, 94 insertions(+)
diff --git a/drivers/regulator/qcom-labibb-regulator.c
b/dr
-by: AngeloGioacchino Del Regno
---
drivers/regulator/qcom-labibb-regulator.c | 92 +++
1 file changed, 92 insertions(+)
diff --git a/drivers/regulator/qcom-labibb-regulator.c
b/drivers/regulator/qcom-labibb-regulator.c
index 0fe0f6bce4cf..0643713d6aad 100644
--- a/drivers/regulator
Short-Circuit Protection (SCP) and Over-Current Protection (OCP) are
now implemented in the driver: document the interrupts.
This also fixes wrong documentation about the SCP interrupt for LAB.
Signed-off-by: AngeloGioacchino Del Regno
Reviewed-by: Bjorn Andersson
---
.../regulator/qcom
map *regmap,
const struct alpha_pll_config *config);
void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
Thanks for following my suggestion!
Reviewed-by: AngeloGioacchino Del Regno
Il 19/01/21 16:07, Vinod Koul ha scritto:
Patch 2 had two blank lines getting inserted, I have fixed that up while
applying.. so:
Applied all, thanks
Thank you!
Add maintainers entry for the Qualcomm CPR3/CPR4/CPRh driver.
Signed-off-by: AngeloGioacchino Del Regno
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 66052be495fb..3d9f9037f1c7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14766,6
The OSM programming addition has been done under the
qcom,cpufreq-hw-8998 compatible name: specify the requirement
of two additional register spaces for this functionality.
This implementation, with the same compatible, has been
tested on MSM8998 and SDM630.
Signed-off-by: AngeloGioacchino Del
From: Manivannan Sadhasivam
Add devicetree documentation for 'qcom,freq-domain' property specific
to Qualcomm CPUs. This property is used to reference the CPUFREQ node
along with Domain ID (0/1).
Signed-off-by: Manivannan Sadhasivam
Signed-off-by: AngeloGioacchino Del Regno
Add the MSM8998 to the blacklist since the CPU scaling is handled
out of this.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c
b/drivers/cpufreq/cpufreq-dt-platdev.c
In preparation for implementing a new driver that will be handling
CPRv3, CPRv4 and CPR-Hardened, format out common functions to a new
file.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/soc/qcom/Makefile | 2 +-
drivers/soc/qcom/cpr-common.c | 382
Signed-off-by: AngeloGioacchino Del Regno
---
.../bindings/power/avs/qcom,cpr.txt | 131 +-
.../bindings/soc/qcom/qcom,cpr.yaml | 167 ++
MAINTAINERS | 2 +-
3 files changed, 169 insertions(+), 131 deletions(-)
create m
rder to get in the
same state as the newer ones and to get the entire scaling hardware to
start rolling.
AngeloGioacchino Del Regno (5):
cpufreq: blacklist SDM630/636/660 in cpufreq-dt-platdev
cpufreq: blacklist MSM8998 in cpufreq-dt-platdev
cpufreq: qcom-hw: Implement CPRh aware OSM program
In order to fine-tune the frequency scaling from various governors,
allow to set a maximum transition latency from OPPs, which may be
different depending on the SoC.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/cpufreq/qcom-cpufreq-hw.c | 7 +++
1 file changed, 7 insertions
Add the bindings for the CPR3 driver to the documentation.
Signed-off-by: AngeloGioacchino Del Regno
---
.../bindings/soc/qcom/qcom,cpr3.yaml | 241 ++
1 file changed, 241 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml
diff
support CPU scaling on SDM630
and MSM8998.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/cpufreq/qcom-cpufreq-hw.c | 1240 -
1 file changed, 1208 insertions(+), 32 deletions(-)
diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c
b/drivers/cpufreq/qcom-c
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