On Tue, Apr 6, 2021 at 6:39 PM Pavan Kondeti wrote:
>
> On Tue, Apr 06, 2021 at 12:15:24PM -0400, Tejun Heo wrote:
> > Hello,
> >
> > On Tue, Apr 06, 2021 at 08:57:15PM +0530, Pavan Kondeti wrote:
> > > Yeah. The workqueue attrs comes in handy to reduce the nice/prio of a
> > > background
The LPC controller has no concept of the BMC and the Host partitions.
This patch fixes the documentation by removing the description on LPC
partitions. The register offsets illustrated in the DTS node examples
are also fixed to adapt to the LPC DTS change.
Signed-off-by: Chia-Wei, Wang
Add check against LPC device v2 compatible string to
ensure that the fixed device tree layout is adopted.
The LPC register offsets are also fixed accordingly.
Signed-off-by: Chia-Wei, Wang
---
drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 17 +++--
1 file changed, 11 insertions(+), 6
Add check against LPC device v2 compatible string to
ensure that the fixed device tree layout is adopted.
The LPC register offsets are also fixed accordingly.
Signed-off-by: Chia-Wei, Wang
---
drivers/soc/aspeed/aspeed-lpc-ctrl.c | 20 ++--
drivers/soc/aspeed/aspeed-lpc-snoop.c
Add check against LPC device v2 compatible string to
ensure that the fixed device tree layout is adopted.
The LPC register offsets are also fixed accordingly.
Signed-off-by: Chia-Wei, Wang
Acked-by: Haiyue Wang
---
drivers/char/ipmi/kcs_bmc_aspeed.c | 27 ---
1 file
check as suggested by Haiyue Wang.
Changes since v2:
- Add v2 binding check to ensure the synchronization between the
device tree change and the driver register offset fix.
Changes since v1:
- Add the fix to the aspeed-lpc binding documentation.
Chia-Wei, Wang (5):
dt
,ast2500-lpc-v2"
"aspeed,ast2600-lpc-v2"
Signed-off-by: Chia-Wei, Wang
---
arch/arm/boot/dts/aspeed-g4.dtsi | 74 +++--
arch/arm/boot/dts/aspeed-g5.dtsi | 135 ++-
arch/arm/boot/dts/aspeed-g6.dtsi | 135 ++-
3 files c
Add bit field definition for the eSPI reset control.
Signed-off-by: Chia-Wei, Wang
---
include/dt-bindings/clock/ast2600-clock.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/ast2600-clock.h
b/include/dt-bindings/clock/ast2600-clock.h
index 62b9520a00fd
, and flash, and operates at max frequency of 66MHz.
Chia-Wei, Wang (6):
dt-bindings: aspeed: Add eSPI controller
MAINTAINER: Add ASPEED eSPI driver entry
clk: ast2600: Add eSPI reset bit
irqchip/aspeed: Add Aspeed eSPI interrupt controller
soc: aspeed: Add eSPI driver
ARM: dts: aspeed: Add
Add eSPI nodes for the device tree of Aspeed 6th generation SoCs.
Signed-off-by: Chia-Wei, Wang
---
arch/arm/boot/dts/aspeed-g6.dtsi | 57
1 file changed, 57 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index
The Aspeed eSPI controller is slave device to communicate with
the master through the Enhanced Serial Peripheral Interface (eSPI).
All of the four eSPI channels, namely peripheral, virtual wire,
out-of-band, and flash are supported.
Signed-off-by: Chia-Wei, Wang
---
drivers/soc/aspeed/Kconfig
Add dt-bindings and the inclusion header for Aspeed eSPI controller.
Signed-off-by: Chia-Wei, Wang
---
.../devicetree/bindings/soc/aspeed/espi.yaml | 252 ++
.../interrupt-controller/aspeed-espi-ic.h | 15 ++
2 files changed, 267 insertions(+)
create mode 100644
The eSPI interrupt controller acts as a SW IRQ number
decoder to correctly control/dispatch interrupts of
the eSPI peripheral, virtual wire, out-of-band, and
flash channels.
Signed-off-by: Chia-Wei, Wang
---
drivers/irqchip/Makefile | 2 +-
drivers/irqchip/irq-aspeed-espi-ic.c
Add myself and Ryan Chen as maintainer of the Aspeed eSPI
driver and the associated eSPI interrupt controller.
Joel Stanley is also added as the reviewer.
Signed-off-by: Chia-Wei, Wang
---
MAINTAINERS | 14 ++
1 file changed, 14 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
Add check against LPC device v2 compatible string to
ensure that the fixed device tree layout is adopted.
The LPC register offsets are also fixed accordingly.
Signed-off-by: Chia-Wei, Wang
---
drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 17 +++--
1 file changed, 11 insertions(+), 6
The LPC controller has no concept of the BMC and the Host partitions.
This patch fixes the documentation by removing the description on LPC
partitions. The register offsets illustrated in the DTS node examples
are also fixed to adapt to the LPC DTS change.
Signed-off-by: Chia-Wei, Wang
Add check against LPC device v2 compatible string to
ensure that the fixed device tree layout is adopted.
The LPC register offsets are also fixed accordingly.
Signed-off-by: Chia-Wei, Wang
---
drivers/soc/aspeed/aspeed-lpc-ctrl.c | 20 ++--
drivers/soc/aspeed/aspeed-lpc-snoop.c
Add check against LPC device v2 compatible string to
ensure that the fixed device tree layout is adopted.
The LPC register offsets are also fixed accordingly.
Signed-off-by: Chia-Wei, Wang
---
drivers/char/ipmi/kcs_bmc_aspeed.c | 27 ---
1 file changed, 16 insertions
,ast2500-lpc-v2"
"aspeed,ast2600-lpc-v2"
Signed-off-by: Chia-Wei, Wang
---
arch/arm/boot/dts/aspeed-g4.dtsi | 74 +++--
arch/arm/boot/dts/aspeed-g5.dtsi | 135 ++-
arch/arm/boot/dts/aspeed-g6.dtsi | 135 ++-
3 files c
binding check to ensure the synchronization between the
device tree change and the driver register offset fix.
Changes since v1:
- Add the fix to the aspeed-lpc binding documentation.
Chia-Wei, Wang (5):
dt-bindings: aspeed-lpc: Remove LPC partitioning
ARM: dts: Remove LPC
Add check against LPC device v2 compatible string to
ensure that the fixed device tree layout is adopted.
The LPC register offsets are also fixed accordingly.
Signed-off-by: Chia-Wei, Wang
---
drivers/soc/aspeed/aspeed-lpc-ctrl.c | 20 ++--
drivers/soc/aspeed/aspeed-lpc-snoop.c
Add check against LPC device v2 compatible string to
ensure that the fixed device tree layout is adopted.
The LPC register offsets are also fixed accordingly.
Signed-off-by: Chia-Wei, Wang
---
drivers/char/ipmi/kcs_bmc_aspeed.c | 35 ++
1 file changed, 21 insertions
Add check against LPC device v2 compatible string to
ensure that the fixed device tree layout is adopted.
The LPC register offsets are also fixed accordingly.
Signed-off-by: Chia-Wei, Wang
---
drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 19 +--
1 file changed, 13 insertions
The LPC controller has no concept of the BMC and the Host partitions.
This patch fixes the documentation by removing the description on LPC
partitions. The register offsets illustrated in the DTS node examples
are also fixed to adapt to the LPC DTS change.
Signed-off-by: Chia-Wei, Wang
,ast2500-lpc-v2"
"aspeed,ast2600-lpc-v2"
Signed-off-by: Chia-Wei, Wang
---
arch/arm/boot/dts/aspeed-g4.dtsi | 74 +++--
arch/arm/boot/dts/aspeed-g5.dtsi | 135 ++-
arch/arm/boot/dts/aspeed-g6.dtsi | 135 ++-
3 files c
change and the driver register offset fix.
Changes since v1:
- Add the fix to the aspeed-lpc binding documentation.
Chia-Wei, Wang (5):
dt-bindings: aspeed-lpc: Remove LPC partitioning
ARM: dts: Remove LPC BMC and Host partitions
ipmi: kcs: aspeed: Adapt to new LPC DTS layout
of the cached value.
This is adapted from https://android-review.googlesource.com/1352810/
Signed-off-by: Wei Wang
---
kernel/sched/cpufreq_schedutil.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/kernel/sched/cpufreq_schedutil.c b/kernel/sched/cpufreq_schedutil.c
On Fri, Oct 16, 2020 at 10:36 AM Rafael J. Wysocki wrote:
>
> On Fri, Oct 16, 2020 at 7:18 PM Wei Wang wrote:
> >
> > On Fri, Oct 16, 2020 at 10:01 AM Rafael J. Wysocki
> > wrote:
> > >
> > > On Fri, Oct 16, 2020 at 6:36 PM Wei Wang wrote:
> >
On Fri, Oct 16, 2020 at 10:01 AM Rafael J. Wysocki wrote:
>
> On Fri, Oct 16, 2020 at 6:36 PM Wei Wang wrote:
> >
> > Currently, raw cache will be reset when next_f is changed after
> > get_next_freq for correctness. However, it may introduce more
> > cycles. Thi
-by: Wei Wang
---
kernel/sched/cpufreq_schedutil.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/kernel/sched/cpufreq_schedutil.c b/kernel/sched/cpufreq_schedutil.c
index 5ae7b4e6e8d6..ae3ae7fcd027 100644
--- a/kernel/sched/cpufreq_schedutil.c
+++ b/kernel/sched
to
the parition boundary. (i.e. offset 80h)
In addition, to be backward compatible, the newly added HW control bits
could be located at any reserved bits over the LPC addressing space.
Thereby, this patch removes the lpc-bmc and lpc-host child node and thus
the LPC partitioning.
Signed-off-by: Chia-Wei, Wang
The LPC register offsets are fixed to adapt to the LPC DTS change,
where the LPC partitioning is removed.
Signed-off-by: Chia-Wei, Wang
---
drivers/char/ipmi/kcs_bmc_aspeed.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/drivers/char/ipmi/kcs_bmc_aspeed.c
b
The LPC register offsets are fixed to adapt to the LPC DTS change,
where the LPC partitioning is removed.
Signed-off-by: Chia-Wei, Wang
---
drivers/soc/aspeed/aspeed-lpc-ctrl.c | 6 +++---
drivers/soc/aspeed/aspeed-lpc-snoop.c | 11 +--
2 files changed, 8 insertions(+), 9 deletions
The LPC controller has no concept of the BMC and the Host partitions.
This patch fixes the documentation by removing the description on LPC
partitions. The register offsets illustrated in the DTS node examples
are also fixed to adapt to the LPC DTS change.
Signed-off-by: Chia-Wei, Wang
The LPC register offsets are fixed to adapt to the LPC DTS change,
where the LPC partitioning is removed.
Signed-off-by: Chia-Wei, Wang
---
drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
development and maintenance.
Changes since v1:
- Add the fix to the aspeed-lpc binding documentation.
Chia-Wei, Wang (5):
ARM: dts: Remove LPC BMC and Host partitions
soc: aspeed: Fix LPC register offsets
ipmi: kcs: aspeed: Fix LPC register offsets
pinctrl: aspeed-g5: Fix LPC
On Tue, Sep 22, 2020 at 12:04 PM Daniel Bristot de Oliveira
wrote:
>
> On 9/22/20 7:14 PM, Wei Wang wrote:
> > On Mon, Sep 21, 2020 at 7:40 AM Daniel Bristot de Oliveira
> > wrote:
> >>
> >> The RT_RUNTIME_SHARE sched feature enables the sharing of rt_runti
On Mon, Sep 21, 2020 at 7:40 AM Daniel Bristot de Oliveira
wrote:
>
> The RT_RUNTIME_SHARE sched feature enables the sharing of rt_runtime
> between CPUs, allowing a CPU to run a real-time task up to 100% of the
> time while leaving more space for non-real-time tasks to run on the CPU
> that lend
The LPC register offsets are fixed to adapt to the LPC DTS change,
where the LPC partitioning is removed.
Signed-off-by: Chia-Wei, Wang
---
drivers/soc/aspeed/aspeed-lpc-ctrl.c | 6 +++---
drivers/soc/aspeed/aspeed-lpc-snoop.c | 11 +--
2 files changed, 8 insertions(+), 9 deletions
development and maintenance.
Chia-Wei, Wang (4):
ARM: dts: Remove LPC BMC and Host partitions
soc: aspeed: Fix LPC register offsets
ipmi: kcs: aspeed: Fix LPC register offsets
pinctrl: aspeed-g5: Fix LPC register offsets
arch/arm/boot/dts/aspeed-g4.dtsi | 74 +--
arch
The LPC register offsets are fixed to adapt to the LPC DTS change,
where the LPC partitioning is removed.
Signed-off-by: Chia-Wei, Wang
---
drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
The LPC register offsets are fixed to adapt to the LPC DTS change,
where the LPC partitioning is removed.
Signed-off-by: Chia-Wei, Wang
---
drivers/char/ipmi/kcs_bmc_aspeed.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/drivers/char/ipmi/kcs_bmc_aspeed.c
b
and maintenance.
Signed-off-by: Chia-Wei, Wang
---
arch/arm/boot/dts/aspeed-g4.dtsi | 74 +++--
arch/arm/boot/dts/aspeed-g5.dtsi | 135 ++-
arch/arm/boot/dts/aspeed-g6.dtsi | 135 ++-
3 files changed, 148 insertions(+), 196
o_has_feature(vb->vdev, VIRTIO_F_VERSION_1))
+ vb->cmd_id_received_cache = le32_to_cpu((__force
__le32)vb->cmd_id_received_cache);
Seems it exceeds 80 character length.
Reviewed-by: Wei Wang
Best,
Wei
The following commit has been merged into the perf/core branch of tip:
Commit-ID: 3cb9d5464c1ceea86f6225089b2f7965989cf316
Gitweb:
https://git.kernel.org/tip/3cb9d5464c1ceea86f6225089b2f7965989cf316
Author:Wei Wang
AuthorDate:Sat, 13 Jun 2020 16:09:46 +08:00
Committer
On Thu, Jun 25, 2020 at 7:32 PM Viresh Kumar wrote:
>
> On 26-06-20, 07:44, Viresh Kumar wrote:
> > On 25-06-20, 13:47, Wei Wang wrote:
> > > On Thu, Jun 25, 2020 at 3:23 AM Viresh Kumar
> > > wrote:
> > > > I am sorry but I am not fully sure of wha
On Thu, Jun 25, 2020 at 3:23 AM Viresh Kumar wrote:
>
> On 24-06-20, 23:46, Wei Wang wrote:
> > To avoid reducing the frequency of a CPU prematurely, we skip reducing
> > the frequency if the CPU had been busy recently.
> >
> > This should not be done when the li
this case. The second flag was kept as the limits_change flag could be
updated in thermal kworker from another CPU.
Fixes: ecd288429126 ("cpufreq: schedutil: Don't set next_freq to UINT_MAX")
Signed-off-by: Wei Wang
---
kernel/sched/cpufreq_schedutil.c | 4 ++--
1 file changed, 2 insert
On Wed, Oct 16, 2019 at 10:16 AM Amit Kucheria
wrote:
>
> On Wed, Oct 16, 2019 at 10:20 PM Amit Kucheria
> wrote:
> >
> > On Tue, Oct 15, 2019 at 11:43 AM Wei Wang wrote:
> > >
> > > The paths thermal_zone%d and cooling_device%d are not intuitive and the
-by: Wei Wang
---
drivers/thermal/thermal_core.c | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/thermal/thermal_core.c b/drivers/thermal/thermal_core.c
index d4481cc8958f..0ff8fb1d7b0a 100644
--- a/drivers/thermal/thermal_core.c
+++ b/drivers
Document the AST2600 PECI controller compatible string.
Signed-off-by: Chia-Wei, Wang
---
Documentation/devicetree/bindings/peci/peci-aspeed.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/peci/peci-aspeed.txt
b/Documentation/devicetree/bindings/peci
Update the Aspeed PECI driver with the AST2600 compatible string.
A new comptabile string is needed for the extended HW feature of
AST2600.
Chia-Wei, Wang (2):
peci: aspeed: Add AST2600 compatible string
dt-bindings: peci: aspeed: Add AST2600 compatible
Documentation/devicetree/bindings
The AST2600 SoC contains the same register set as AST25xx.
Signed-off-by: Chia-Wei, Wang
---
drivers/peci/peci-aspeed.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/peci/peci-aspeed.c b/drivers/peci/peci-aspeed.c
index 51cb2563ceb6..4eed119dc83b 100644
--- a/drivers/peci/peci
422150 ("ipv6: convert major tx path to use
> RT6_LOOKUP_F_DST_NOREF")
> Signed-off-by: Jason A. Donenfeld
> ---
Acked-by: Wei Wang
Good catch. Thanks for the fix.
> net/ipv6/fib6_rules.c| 3 ++-
> tools/testing/selftests/net/fib_tests.sh | 17 +++
On 08/06/2019 03:16 PM, Wei Wang wrote:
The guest can access the lbr related msrs only when the vcpu's lbr event
has been assigned the lbr feature. A cpu pinned lbr event (though no such
event usages in the current upstream kernel) could reclaim the lbr feature
from the vcpu's lbr event (task
to not assign a counter for a perf event
which doesn't need a counter. Define a macro, X86_PMC_IDX_NA, to replace
"-1", which represents a never assigned counter id.
Cc: Andi Kleen
Cc: Peter Zijlstra
Signed-off-by: Wei Wang
https://lkml.kernel.org/r/20180920162407.ga24...@hirez.programming.kic
t need a pmu counter.
So move the event->owner assignment into perf_event_alloc to have it
set before event_init is called.
Signed-off-by: Wei Wang
---
kernel/events/core.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/kernel/events/core.c b/kernel/events/cor
switching, and the config won't be written to the
LBR_SELECT, as the LBR_SELECT is configured by the guest, which might
not be the same as the user callstack mode. So don't allow the vcpu's
lbr event to share lbr with other host lbr events.
Signed-off-by: Wei Wang
---
arch/x86/events/intel/lbr.c | 27
jlstra
Co-developed-by: Like Xu
Signed-off-by: Like Xu
Signed-off-by: Wei Wang
---
arch/x86/events/intel/lbr.c | 38 ++--
arch/x86/events/perf_event.h| 1 +
arch/x86/include/asm/kvm_host.h | 1 +
arch/x86/kvm/vmx/pmu_intel
: Andi Kleen
Cc: Peter Zijlstra
Signed-off-by: Wei Wang
---
arch/x86/kvm/x86.c | 13 -
1 file changed, 13 deletions(-)
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index efaf0e8..3839ebd 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -2528,18 +2528,6 @@ int
get lost during the vcpu context
switching.
Cc: Peter Zijlstra
Cc: Andi Kleen
Cc: Kan Liang
Signed-off-by: Wei Wang
---
arch/x86/events/intel/lbr.c | 7 +++
arch/x86/events/perf_event.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/in
ugh of the lbr related msrs will be cancelled if the lbr is
reclaimed, and the following guest accesses to the lbr related msrs will
vm-exit to the related msr emulation handler in kvm, which will prevent
the accesses.
Signed-off-by: Wei Wang
---
arch/x86/kvm/pmu.c | 6 ++
arch/x86/kvm/pm
msrs during an entire vcpu time
slice.
Cc: Paolo Bonzini
Cc: Andi Kleen
Cc: Peter Zijlstra
Suggested-by: Andi Kleen
Signed-off-by: Wei Wang
---
arch/x86/include/asm/kvm_host.h | 2 +
arch/x86/kvm/pmu.c | 6 ++
arch/x86/kvm/pmu.h | 2 +
arch/x86/kvm/vmx
Bits [0, 5] of MSR_IA32_PERF_CAPABILITIES tell about the format of
the addresses stored in the lbr stack. Expose those bits to the guest
when the guest lbr feature is enabled.
Cc: Paolo Bonzini
Cc: Andi Kleen
Signed-off-by: Wei Wang
---
arch/x86/include/asm/perf_event.h | 2 ++
arch/x86/kvm
see different lbr stack msr indices.
Cc: Paolo Bonzini
Cc: Andi Kleen
Cc: Peter Zijlstra
Cc: Kan Liang
Signed-off-by: Wei Wang
---
arch/x86/kvm/pmu.c | 8 +++
arch/x86/kvm/pmu.h | 2 +
arch/x86/kvm/vmx/pmu_intel.c | 136 +++
arch
Change kvm_pmu_get_msr to get the msr_data struct, as the host_initiated
field from the struct could be used by get_msr. This also makes this API
consistent with kvm_pmu_set_msr.
Cc: Paolo Bonzini
Cc: Andi Kleen
Signed-off-by: Wei Wang
---
arch/x86/kvm/pmu.c | 4 ++--
arch/x86/kvm
The msr variable type can be "unsigned int", which uses less memory than
the longer unsigned long. The lbr nr won't be a negative number, so make
it "unsigned int" as well.
Cc: Peter Zijlstra
Cc: Andi Kleen
Suggested-by: Peter Zijlstra
Signed-off-by: Wei Wang
---
arch/x86
Introduce KVM_CAP_X86_GUEST_LBR to allow per-VM enabling of the guest
lbr feature.
Signed-off-by: Wei Wang
---
Documentation/virt/kvm/api.txt | 26 ++
arch/x86/include/asm/kvm_host.h | 2 ++
arch/x86/kvm/x86.c | 16
include/uapi/linux
for the guest.
Cc: Paolo Bonzini
Cc: Andi Kleen
Cc: Peter Zijlstra
Signed-off-by: Wei Wang
---
arch/x86/events/intel/lbr.c | 23 +++
arch/x86/include/asm/perf_event.h | 14 ++
2 files changed, 37 insertions(+)
diff --git a/arch/x86/events/intel/lbr.c b/arch/x86
lkml.kernel.org/r/1562548999-37095-1-git-send-email-wei.w.w...@intel.com
Wei Wang (14):
perf/x86: fix the variable type of the lbr msrs
perf/x86: add a function to get the addresses of the lbr stack msrs
KVM/x86: KVM_CAP_X86_GUEST_LBR
KVM/x86: intel_pmu_lbr_enable
KVM/x86/vPMU: tweak k
hite space here, other part looks good to me.
Reviewed-by: Wei Wang
Best,
Wei
calls "list_del" to do the removal.
This is necessary when it's used from balloon_page_enqueue_list, but
not from balloon_page_enqueue_one.
So remove the list_del balloon_page_enqueue_one, and update some
comments as a reminder.
Signed-off-by: Wei Wang
---
ChangeLong:
v1->v2:
On 07/18/2019 02:47 PM, Michael S. Tsirkin wrote:
On Thu, Jul 18, 2019 at 02:30:01PM +0800, Wei Wang wrote:
On 07/18/2019 01:58 PM, Michael S. Tsirkin wrote:
what if it does not fail?
Shrinker is called on system memory pressure. On memory pressure
get_free_page_and_send will fail memory
On 07/18/2019 12:31 PM, Michael S. Tsirkin wrote:
On Thu, Jul 18, 2019 at 10:23:30AM +0800, Wei Wang wrote:
Fixes: 418a3ab1e778 (mm/balloon_compaction: List interfaces)
A #GP is reported in the guest when requesting balloon inflation via
virtio-balloon. The reason is that the virtio-balloon
On 07/18/2019 01:58 PM, Michael S. Tsirkin wrote:
what if it does not fail?
Shrinker is called on system memory pressure. On memory pressure
get_free_page_and_send will fail memory allocation, so it stops allocating
more.
Memory pressure could be triggered by an unrelated allocation
e.g.
On 07/18/2019 12:13 PM, Michael S. Tsirkin wrote:
It makes sense for pages in the balloon (requested by hypervisor).
However free page hinting can freeze up lots of memory for its own
internal reasons. It does not make sense to ask hypervisor
to set flags in order to fix internal guest issues.
calls "list_del" to do the removal.
So remove the list_del in balloon_page_enqueue_one, and have the callers
do the page removal from their own page lists.
Signed-off-by: Wei Wang
---
mm/balloon_compaction.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff
On 07/16/2019 08:10 AM, Eric Hankland wrote:
I think just disabling guest cpuid might not be enough, since guest
could write to the msr without checking the cpuid.
Why not just add a bitmap for fixed counter?
e.g. fixed_counter_reject_bitmap
At the beginning of reprogram_fixed_counter, we
On 07/11/2019 09:25 AM, Eric Hankland wrote:
- Add a VM ioctl that can control which events the guest can monitor.
Signed-off-by: ehankland
---
Changes since v1:
-Moved to a vm ioctl rather than a vcpu one
-Changed from a whitelist to a configurable filter which can either be
white or black
On 07/09/2019 07:35 PM, Peter Zijlstra wrote:
Yeah; although I'm not sure if its an implementation or specification
problem. But as it exists it is of very limited use.
Fundamentally our events (with exception of event groups) are
independent. Events should always count, except when the PMI is
On 07/09/2019 07:45 PM, Peter Zijlstra wrote:
+* config:Actually this field won't be used by the perf core
+*as this event doesn't have a perf counter.
+* sample_period: Same as above.
If it's unused; why do we need to set it at all?
OK, we'll
On 07/09/2019 08:19 PM, Peter Zijlstra wrote:
For the lbr feature, could we thought of it as first come, first served?
For example, if we have 2 host threads who want to use lbr at the same time,
I think one of them would simply fail to use.
So if guest first gets the lbr, host wouldn't take
On 07/09/2019 05:43 PM, Peter Zijlstra wrote:
That's almost a year ago; I really can't remember that and you didn't
put any of that in your Changelog to help me remember.
(also please use: https://lkml.kernel.org/r/$msgid style links)
OK, I'll put this link in the cover letter or commit log
On 07/09/2019 05:39 PM, Peter Zijlstra wrote:
On Tue, Jul 09, 2019 at 11:04:21AM +0800, Wei Wang wrote:
On 07/08/2019 10:48 PM, Peter Zijlstra wrote:
*WHY* does the host need to save/restore? Why not make VMENTER/VMEXIT do
this?
Because the VMX transition is much more frequent than the vCPU
On 07/08/2019 11:09 PM, Peter Zijlstra wrote:
On Mon, Jul 08, 2019 at 09:23:19AM +0800, Wei Wang wrote:
This patch enables the LBR related features in Arch v4 in advance,
though the current vPMU only has v2 support. Other arch v4 related
support will be enabled later in another series.
Arch v4
On 07/08/2019 10:53 PM, Peter Zijlstra wrote:
On Mon, Jul 08, 2019 at 09:23:17AM +0800, Wei Wang wrote:
When the vCPU is scheduled in:
- if the lbr feature was used in the last vCPU time slice, set the lbr
stack to be interceptible, so that the host can capture whether the
lbr feature
On 07/08/2019 10:48 PM, Peter Zijlstra wrote:
On Mon, Jul 08, 2019 at 09:23:15AM +0800, Wei Wang wrote:
From: Like Xu
This patch adds support to enable/disable the host side save/restore
This patch should be disqualified on Changelog alone...
Documentation/process/submitting
On 07/08/2019 10:29 PM, Peter Zijlstra wrote:
Thanks for the comments.
diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
index 0ab99c7..19e6593 100644
--- a/include/linux/perf_event.h
+++ b/include/linux/perf_event.h
@@ -528,6 +528,7 @@ typedef void
and guest see different lbr stack msr indices.
Signed-off-by: Wei Wang
Cc: Paolo Bonzini
Cc: Andi Kleen
Cc: Peter Zijlstra
---
arch/x86/kvm/pmu.c | 8 +++
arch/x86/kvm/pmu.h | 2 +
arch/x86/kvm/vmx/pmu_intel.c | 136 +++
arch/x86
debugctl.freeze_lbr_on_pmi
has been set and a PMI is generated. The CTR_FRZ bit is set when
debugctl.freeze_perfmon_on_pmi is set and a PMI is generated.
Signed-off-by: Wei Wang
Cc: Andi Kleen
Cc: Paolo Bonzini
Cc: Kan Liang
---
arch/x86/kvm/pmu.c | 11 +--
arch/x86/kvm
for the guest.
Signed-off-by: Wei Wang
Cc: Paolo Bonzini
Cc: Andi Kleen
Cc: Peter Zijlstra
---
arch/x86/events/intel/lbr.c | 23 +++
arch/x86/include/asm/perf_event.h | 14 ++
2 files changed, 37 insertions(+)
diff --git a/arch/x86/events/intel/lbr.c b/arch/x86
Bits [0, 5] of MSR_IA32_PERF_CAPABILITIES tell about the format of
the addresses stored in the LBR stack. Expose those bits to the guest
when the guest lbr feature is enabled.
Signed-off-by: Wei Wang
Cc: Paolo Bonzini
Cc: Andi Kleen
---
arch/x86/include/asm/perf_event.h | 2 ++
arch/x86/kvm
The debugctl msr is not completely identical on AMD and Intel CPUs, for
example, FREEZE_LBRS_ON_PMI is supported by Intel CPUs only. Now, this
msr is handled separatedly in svm.c and intel_pmu.c. So remove the
common debugctl msr handling code in kvm_get/set_msr_common.
Signed-off-by: Wei Wang
Kleen
Signed-off-by: Wei Wang
Cc: Paolo Bonzini
Cc: Andi Kleen
Cc: Peter Zijlstra
---
arch/x86/include/asm/kvm_host.h | 2 +
arch/x86/kvm/pmu.c | 6 ++
arch/x86/kvm/pmu.h | 2 +
arch/x86/kvm/vmx/pmu_intel.c| 141
arch
The vCPU lbr event relies on the host to save/restore all the lbr
related MSRs. So add the LBR_SELECT save/restore to the related
functions for the vCPU case.
Signed-off-by: Wei Wang
Cc: Peter Zijlstra
Cc: Andi Kleen
---
arch/x86/events/intel/lbr.c | 7 +++
arch/x86/events/perf_event.h
of counter assignment.
Signed-off-by: Wei Wang
Cc: Andi Kleen
Cc: Peter Zijlstra
---
arch/x86/events/core.c | 12
include/linux/perf_event.h | 13 +
kernel/events/core.c | 37 +
3 files changed, 50 insertions(+), 12 deletions
The MSR variable type can be "unsigned int", which uses less memory than
the longer unsigned long. The lbr nr won't be a negative number, so make
it "unsigned int" as well.
Suggested-by: Peter Zijlstra
Signed-off-by: Wei Wang
Cc: Peter Zijlstra
Cc: Andi Kleen
---
arch/x86
) and finds
it's non-zero, it simply returns.
Signed-off-by: Like Xu
Signed-off-by: Wei Wang
Cc: Paolo Bonzini
Cc: Andi Kleen
Cc: Peter Zijlstra
---
arch/x86/events/intel/lbr.c | 13 +++--
arch/x86/events/perf_event.h| 1 +
arch/x86/include/asm/kvm_host.h | 1 +
arch/x86/kvm/pmu.h
Introduce KVM_CAP_X86_GUEST_LBR to allow per-VM enabling of the guest
lbr feature.
Signed-off-by: Wei Wang
Cc: Paolo Bonzini
Cc: Andi Kleen
Cc: Peter Zijlstra
---
arch/x86/include/asm/kvm_host.h | 2 ++
arch/x86/kvm/x86.c | 14 ++
include/uapi/linux/kvm.h
PIs to support host save/restore the guest lbr
stack
Wei Wang (11):
perf/x86: fix the variable type of the LBR MSRs
perf/x86: add a function to get the lbr stack
KVM/x86: KVM_CAP_X86_GUEST_LBR
KVM/x86: intel_pmu_lbr_enable
KVM/x86/vPMU: tweak kvm_pmu_get_msr
KVM/x86: exp
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