[llvm-branch-commits] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

https://github.com/asb approved this pull request. https://github.com/llvm/llvm-project/pull/92143 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

asb wrote: My thoughts: * Thanks to @negge and others for clarifying who this is affecting and how * It's very unfortunate we've broken some use cases here. Though as, by my understand, this is affecting people using internal flags as opposed to documented top-level flags I feel there's not a

[llvm-branch-commits] [RISCV] Generate profiles from RISCVProfiles.td (PR #90187)

https://github.com/asb commented: Probably best reviewed by someone who has more familiarity with RISCVTargetDefEmitter, but I took a look anyway. I think this direction is OK, though I can't help but feel moving from the ISA naming strings to the more verbose listing of features is a bit of

[llvm-branch-commits] [RISCV] Generate profiles from RISCVProfiles.td (PR #90187)

@@ -51,6 +51,14 @@ def Feature64Bit def FeatureDummy : SubtargetFeature<"dummy", "Dummy", "true", "Dummy">; +class RISCVProfile features> +: SubtargetFeature; + +def RVI20U32 : RISCVProfile<"rvi20u32", [Feature32Bit, FeatureStdExtI]>; +def RVI20U64 :

[llvm-branch-commits] [RISCV] Generate profiles from RISCVProfiles.td (PR #90187)

https://github.com/asb edited https://github.com/llvm/llvm-project/pull/90187 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm][RISCV] Enable trailing fences for seq-cst stores by default (PR #87376)

https://github.com/asb approved this pull request. LGTM, thanks. https://github.com/llvm/llvm-project/pull/87376 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org

[llvm-branch-commits] [llvm][RISCV] Enable trailing fences for seq-cst stores by default (PR #87376)

asb wrote: Thanks for splitting this out. The changes look good to me, but could you please add a brief release note to llvm/docs/ReleaseNotes? Perhaps something like "The default [atomics mapping](https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-atomic.adoc) was

[llvm-branch-commits] [llvm] [RISCV] Support llvm.readsteadycounter intrinsic (PR #82322)

https://github.com/asb approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/82322 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [RISCV] Check type is legal before combining mgather to vlse intrinsic (#81107) (PR #81568)

https://github.com/asb approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/81568 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [RISCV] Use APInt in useInversedSetcc to prevent crashes when mask is larger than UINT64_MAX. (#81888) (PR #81905)

https://github.com/asb approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/81905 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] Revert "[RISCV] Recurse on first operand of two operand shuffles (#79180)" (PR #80238)

https://github.com/asb approved this pull request. In case it's helpful, explicit LGTM from me on backporting this. @preames looks like you need to rebase https://github.com/llvm/llvm-project/pull/80238 ___ llvm-branch-commits mailing list

[llvm-branch-commits] [clang] [llvm] Backport [RISCV] Graduate Zicond to non-experimental (#79811) (PR #80018)

asb wrote: The proposed formatting change is undesired. `main` has this section of code bracketed by `// clang-format off` and on. It doesn't seem worth cherry-picking that too for this backport, but I can if wanted. https://github.com/llvm/llvm-project/pull/80018

[llvm-branch-commits] [llvm] [clang] Backport [RISCV] Graduate Zicond to non-experimental (#79811) (PR #80018)

asb wrote: This patch came after the branch, but really it's cleaning up something we should have done a while ago once the extension was ratified at the end of last year. https://github.com/llvm/llvm-project/pull/80018 ___ llvm-branch-commits

[llvm-branch-commits] [llvm] [clang] Backport [RISCV] Graduate Zicond to non-experimental (#79811) (PR #80018)

https://github.com/asb edited https://github.com/llvm/llvm-project/pull/80018 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [clang] Backport [RISCV] Graduate Zicond to non-experimental (#79811) (PR #80018)

https://github.com/asb created https://github.com/llvm/llvm-project/pull/80018 The Zicond extension was ratified in the last few months, with no changes that affect the LLVM implementation. Although there's surely more tuning that could be done about when to select Zicond or not, there are no

[llvm-branch-commits] [llvm] [clang] Backport [RISCV] Graduate Zicond to non-experimental (#79811) (PR #80018)

https://github.com/asb milestoned https://github.com/llvm/llvm-project/pull/80018 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] ae37edf - [ReleaseNotes] Expand RISC-V release notes

Author: Alex Bradbury Date: 2023-03-06T20:41:28Z New Revision: ae37edf1486d35ac6f441c5ff489ab46a94e125e URL: https://github.com/llvm/llvm-project/commit/ae37edf1486d35ac6f441c5ff489ab46a94e125e DIFF: https://github.com/llvm/llvm-project/commit/ae37edf1486d35ac6f441c5ff489ab46a94e125e.diff

[llvm-branch-commits] [llvm] 4ba6a9c - [RISCV][ReleaseNotes] Added LLVM and Clang release notes for RISC-V 15.0.0

Author: Alex Bradbury Date: 2022-09-05T10:48:03+01:00 New Revision: 4ba6a9c9f65bbc8bd06e3652cb20fd4dfc846137 URL: https://github.com/llvm/llvm-project/commit/4ba6a9c9f65bbc8bd06e3652cb20fd4dfc846137 DIFF: https://github.com/llvm/llvm-project/commit/4ba6a9c9f65bbc8bd06e3652cb20fd4dfc846137.diff

[llvm-branch-commits] [llvm] 9d54fe2 - [docs] Add RISC-V release notes for LLVM 14

Author: Alex Bradbury Date: 2022-03-07T10:58:20Z New Revision: 9d54fe21c67fdb76bfd95c329a31bda2cb91c520 URL: https://github.com/llvm/llvm-project/commit/9d54fe21c67fdb76bfd95c329a31bda2cb91c520 DIFF: https://github.com/llvm/llvm-project/commit/9d54fe21c67fdb76bfd95c329a31bda2cb91c520.diff

[llvm-branch-commits] [llvm] 7030fc5 - ReleaseNotes: Add RISC-V updates

Author: Alex Bradbury Date: 2020-09-05T13:26:44+01:00 New Revision: 7030fc50d93e5b08bde9743fb54f24c4a44a8e4a URL: https://github.com/llvm/llvm-project/commit/7030fc50d93e5b08bde9743fb54f24c4a44a8e4a DIFF: https://github.com/llvm/llvm-project/commit/7030fc50d93e5b08bde9743fb54f24c4a44a8e4a.diff