[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

2024-04-26 Thread Kito Cheng via llvm-branch-commits
@@ -65,10 +65,27 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo { VentanaVeyron, }; // clang-format on + + enum RISCVProfileEnum : uint8_t { +Unspecified, +RVI20U32, +RVI20U64, +RVA20U64, +RVA20S64, +RVA22U64, +RVA22S64, +

[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

2024-04-26 Thread Kito Cheng via llvm-branch-commits
@@ -65,10 +65,27 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo { VentanaVeyron, }; // clang-format on + + enum RISCVProfileEnum : uint8_t { kito-cheng wrote: This can remove https://github.com/llvm/llvm-project/pull/84877

[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

2024-04-26 Thread Kito Cheng via llvm-branch-commits
@@ -138,6 +155,8 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo { /// initializeProperties(). RISCVProcFamilyEnum getProcFamily() const { return RISCVProcFamily; } + RISCVProfileEnum getRISCVProfile() const { return RISCVProfile; } + kito-cheng

[llvm-branch-commits] [compiler-rt] release/18.x: [RISCV] Support rv{32, 64}e in the compiler builtins (#88252) (PR #88525)

2024-04-15 Thread Kito Cheng via llvm-branch-commits
https://github.com/kito-cheng approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/88525 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] 5b6216d - [RISCV] Lazily add RVV C intrinsics.

2022-05-11 Thread Kito Cheng via llvm-branch-commits
Author: Kito Cheng Date: 2022-05-11T17:56:59+08:00 New Revision: 5b6216d6aa45c91bd348393eba8952f34735b736 URL: https://github.com/llvm/llvm-project/commit/5b6216d6aa45c91bd348393eba8952f34735b736 DIFF: https://github.com/llvm/llvm-project/commit/5b6216d6aa45c91bd348393eba8952f34735b736.diff

[llvm-branch-commits] [clang] 08dbbaf - [RISCV][NFC] Refactor RISC-V vector intrinsic utils.

2022-05-11 Thread Kito Cheng via llvm-branch-commits
Author: Kito Cheng Date: 2022-05-11T17:56:59+08:00 New Revision: 08dbbaf68d88a57e977d0674bddd0142e5d1e0b9 URL: https://github.com/llvm/llvm-project/commit/08dbbaf68d88a57e977d0674bddd0142e5d1e0b9 DIFF: https://github.com/llvm/llvm-project/commit/08dbbaf68d88a57e977d0674bddd0142e5d1e0b9.diff