[llvm-branch-commits] [AArch64] Remove usage of PostRAScheduler (PR #92871)

wangpc-pp wrote: These branches are created by `spr`, which is out of my control, and we can merge it into `main` branch via `spr land`. These branches are just magics behind `spr`, please don't obsess over this. `spr` is a tool that the community suggests, I have used it for a long time and

[llvm-branch-commits] [AArch64] Remove usage of PostRAScheduler (PR #92871)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/92871 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [AArch64] Remove usage of PostRAScheduler (PR #92871)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/92871 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [AArch64] Remove usage of PostRAScheduler (PR #92871)

wangpc-pp wrote: > > > Submit your PRs to `main` branch > > > > > > I used [spr](https://getcord.github.io/spr/) to create this PR, so I think > > it's OK. > > No, your target branch is wrong. Either you should want to merge into `main` > or into a branch for another PR created by `spr`.

[llvm-branch-commits] [AArch64] Remove usage of PostRAScheduler (PR #92871)

wangpc-pp wrote: > Submit your PRs to `main` branch I used [spr](https://getcord.github.io/spr/) to create this PR, so I think it's OK. https://github.com/llvm/llvm-project/pull/92871 ___ llvm-branch-commits mailing list

[llvm-branch-commits] [AArch64] Remove usage of PostRAScheduler (PR #92871)

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/92871 This doesn't take effect as we have overrided `enablePostRAScheduler` and we should use the `FeaturePostRAScheduler` feature in processor definitions. ___

[llvm-branch-commits] [RISCV] Remove hasSideEffects=1 for saturating/fault-only-first instructions (PR #90049)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/90049 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV] Remove hasSideEffects=1 for saturating/fault-only-first instructions (PR #90049)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/90049 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV] Remove hasSideEffects=1 for saturating/fault-only-first instructions (PR #90049)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/90049 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV] Make fixed-point instructions commutable (PR #90372)

https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/90372 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV] Make fixed-point instructions commutable (PR #90372)

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/90372 This PR includes: * vsadd.vv/vsaddu.vv * vaadd.vv/vaaddu.vv * vsmul.vv ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org

[llvm-branch-commits] [RISCV] Generate profiles from RISCVProfiles.td (PR #90187)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/90187 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV] Generate profiles from RISCVProfiles.td (PR #90187)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/90187 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84877 >From ec68548a470d6d9032a900a725e95b92691657b2 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 12 Mar 2024 14:28:09 +0800 Subject: [PATCH 1/7] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=

[llvm-branch-commits] [RISCV] Generate profiles from RISCVProfiles.td (PR #90187)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/90187 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV] Generate profiles from RISCVProfiles.td (PR #90187)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/90187 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84877 >From ec68548a470d6d9032a900a725e95b92691657b2 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 12 Mar 2024 14:28:09 +0800 Subject: [PATCH 1/6] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=

[llvm-branch-commits] [RISCV] Generate profiles from RISCVProfiles.td (PR #90187)

@@ -51,6 +51,14 @@ def Feature64Bit def FeatureDummy : SubtargetFeature<"dummy", "Dummy", "true", "Dummy">; +class RISCVProfile features> +: SubtargetFeature; + +def RVI20U32 : RISCVProfile<"rvi20u32", [Feature32Bit, FeatureStdExtI]>; +def RVI20U64 :

[llvm-branch-commits] [RISCV] Generate profiles from RISCVProfiles.td (PR #90187)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/90187 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV] Generate profiles from RISCVProfiles.td (PR #90187)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/90187 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84877 >From ec68548a470d6d9032a900a725e95b92691657b2 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 12 Mar 2024 14:28:09 +0800 Subject: [PATCH 1/5] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=

[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84877 >From ec68548a470d6d9032a900a725e95b92691657b2 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 12 Mar 2024 14:28:09 +0800 Subject: [PATCH 1/4] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=

[llvm-branch-commits] [RISCV] Generate profiles from RISCVProfiles.td (PR #90187)

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/90187 So we can only mantain one place. ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org

[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84877 >From ec68548a470d6d9032a900a725e95b92691657b2 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 12 Mar 2024 14:28:09 +0800 Subject: [PATCH 1/3] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=

[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/84877 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV] Remove hasSideEffects=1 for saturating/fault-only-first instructions (PR #90049)

wangpc-pp wrote: According to `Target.td`: ```c // Does the instruction have side effects that are not captured by any // operands of the instruction or other flags? bit hasSideEffects = ?; ``` It seems we don't need to set `hasSideEffects` for vleNff since we have modelled `vl` as an output

[llvm-branch-commits] [RISCV] Remove hasSideEffects=1 for saturating/fault-only-first instructions (PR #90049)

wangpc-pp wrote: > > For saturating instructions, they may write vxsat. This is like > > floating-point instructions that may write fflags, but we don't > > model floating-point instructions as hasSideEffects=1. > > That's because floating point instructions use mayRaiseFPExceptions=1. And >

[llvm-branch-commits] [RISCV] Make fixed-point instructions commutable (PR #90053)

wangpc-pp wrote: Sorry for bothering, I just ran spr on a non-spr branch. https://github.com/llvm/llvm-project/pull/90053 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org

[llvm-branch-commits] [RISCV] Make fixed-point instructions commutable (PR #90053)

https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/90053 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV] Make fixed-point instructions commutable (PR #90053)

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/90053 This PR includes: * vsadd.vv/vsaddu.vv * vaadd.vv/vaaddu.vv * vsmul.vv ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org

[llvm-branch-commits] [RISCV] Remove hasSideEffects=1 for saturating/fault-only-first instructions (PR #90049)

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/90049 Masking them as `hasSideEffects=1` stops some optimizations. For saturating instructions, they may write `vxsat`. This is like floating-point instructions that may write `fflags`, but we don't model

[llvm-branch-commits] [llvm] [RISCV] Don't use V0 directly in patterns (PR #88496)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/88496 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Don't use V0 directly in patterns (PR #88496)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/88496 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [compiler-rt] release/18.x: [RISCV] Support rv{32, 64}e in the compiler builtins (#88252) (PR #88525)

wangpc-pp wrote: > Hi @wangpc-pp (or anyone else). If you would like to add a note about this > fix in the release notes (completely optional). Please reply to this comment > with a one or two sentence description of the fix. Yeah, the description can be: ``` Save/restore routines for

[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84894 >From 951478b16d8aa834bff4494dc6d05c5f1175d59f Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 12 Mar 2024 18:41:50 +0800 Subject: [PATCH 1/2] Fix wrong arguments Created using spr 1.3.4 ---

[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84894 >From 951478b16d8aa834bff4494dc6d05c5f1175d59f Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 12 Mar 2024 18:41:50 +0800 Subject: [PATCH 1/2] Fix wrong arguments Created using spr 1.3.4 ---

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84455 >From 35d0ea085b43a67c092e6263e6ec9d34e66e1453 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 12 Mar 2024 17:31:47 +0800 Subject: [PATCH 01/10] Reduce copies Created using spr 1.3.4 ---

[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84894 >From 951478b16d8aa834bff4494dc6d05c5f1175d59f Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 12 Mar 2024 18:41:50 +0800 Subject: [PATCH 1/2] Fix wrong arguments Created using spr 1.3.4 ---

[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84894 >From 951478b16d8aa834bff4494dc6d05c5f1175d59f Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 12 Mar 2024 18:41:50 +0800 Subject: [PATCH 1/2] Fix wrong arguments Created using spr 1.3.4 ---

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84455 >From 35d0ea085b43a67c092e6263e6ec9d34e66e1453 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 12 Mar 2024 17:31:47 +0800 Subject: [PATCH 1/9] Reduce copies Created using spr 1.3.4 ---

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84455 >From 35d0ea085b43a67c092e6263e6ec9d34e66e1453 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 12 Mar 2024 17:31:47 +0800 Subject: [PATCH 1/9] Reduce copies Created using spr 1.3.4 ---

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

@@ -212,19 +185,13 @@ body: | ; CHECK-NEXT: $v7 = VMV1R_V $v14 ; CHECK-NEXT: $v8 = VMV1R_V $v15 ; CHECK-NEXT: $v9 = VMV1R_V $v16 -; CHECK-NEXT: $v4 = VMV1R_V $v10 -; CHECK-NEXT: $v5 = VMV1R_V $v11 -; CHECK-NEXT: $v6 = VMV1R_V $v12 -;

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84455 >From 35d0ea085b43a67c092e6263e6ec9d34e66e1453 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 12 Mar 2024 17:31:47 +0800 Subject: [PATCH 1/6] Reduce copies Created using spr 1.3.4 ---

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

wangpc-pp wrote: Ping. Are there any more comments? https://github.com/llvm/llvm-project/pull/84455 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits