Since we support QueryVariableInfo at runtime now add the relevant
tests. Since we want those to be reusable at bootime, add them
in a separate file
Add tests for
- Test QueryVariableInfo returns EFI_SUCCESS
- Test null pointers for the function arguments
- Test invalid combination of attributes
Previous patches added QueryVariableInfo at runtime tests and
split a common function that can be used at boottime. Weire it
up and run a similar set of tets. While at it move a test which is
checiking for 0 available storage in the common code
Add tests for
- Test QueryVariableInfo returns
Since commit c28d32f946f0 ("efi_loader: conditionally enable SetvariableRT")
we are enabling the last bits of missing runtime services.
Add support for QueryVariableInfo which we already support at boottime
and we just need to mark some fucntions available at runtime and move
some checks around.
From: Takahiro Kuwano
The Infineon SEMPER NOR flash family uses 2-bit ECC by default with each
ECC block being 16 bytes. Under this scheme multi-pass programming to an
ECC block is not allowed. Set the writesize to make sure multi-pass
programming is not attempted on the flash.
Signed-off-by:
From: Takahiro Kuwano
spi_nor_post_sfdp_fixups() was called regardless of if
spi_nor_parse_sfdp() had been called or not. late_init() should be
instead used to initialize the parameters that are not defined in SFDP.
Ideally spi_nor_post_sfdp_fixups() is called only after successful parse
of
From: Takahiro Kuwano
default_init() is wrong, it contributes to the maze of initializing
flash parameters. We'd like to get rid of it because the flash
parameters that it initializes are not really used at SFDP parsing time,
thus they can be initialized later.
Ideally we want SFDP to
From: Takahiro Kuwano
The macronix_octal_fixups should be set only when mfr and flags match.
Fixes: df3d5f9e41 ("mtd: spi-nor: add support for Macronix Octal flash")
Signed-off-by: Takahiro Kuwano
Cc: JaimeLiao
---
drivers/mtd/spi/spi-nor-core.c | 4 +++-
1 file changed, 3 insertions(+), 1
From: Takahiro Kuwano
Some flashes like the Infineon SEMPER NOR flash family use ECC. Under
this ECC scheme, multi-pass writes to an ECC block is not allowed.
In other words, once data is programmed to an ECC block, it can't be
programmed again without erasing it first.
Upper layers like file
From: Takahiro Kuwano
For NOR flashes EC and VID are zeroed out before an erase is issued to
make sure UBI does not mistakenly treat the PEB as used and associate it
with an LEB.
But on some flashes, like the Infineon Semper NOR flash family,
multi-pass page programming is not allowed on the
From: Takahiro Kuwano
This series is equivalent to the one for Linux MTD submitted by
Pratyush Yadav.
https://patchwork.ozlabs.org/project/linux-mtd/list/?series=217759=*
Changes in v2:
- Fix an issue in setting macronix_octal_fixups
- Rework fixup hooks
Takahiro Kuwano (6):
mtd: ubi:
Hello Caleb,
On 23.04.24 13:43, Caleb Connolly wrote:
On Mon, 22 Apr 2024 11:33:51 +0200, Neil Armstrong wrote:
Add Support for the Qualcomm Generic Interface (GENI) I2C interface
found on newer Qualcomm SoCs.
The Generic Interface (GENI) is a firmware based Qualcomm Universal
Peripherals
Hi Caleb,
Thanks for this interesting feedback. I saw these patches were already merged
since you sent this but I added a few thoughts below anyway.
On Friday, April 12th, 2024 at 11:50 AM, Caleb Connolly
wrote:
> Hi Phaedrus,
>
> On 07/04/2024 03:47, mwle...@mailtundra.com wrote:
>
> >
From: Nathan Barrett-Morrison
Add support for the SC5xx machine type from Analog Devices. This
includes support for the SC57x, SC58x, SC59x, and SC59x-64 SoCs, which
have many common features such as common ADI IP blocks, and SHARC DSP
cores. This commit introduces core functionality required
This series adds support for the ADI SC5xx machine type and includes two
core drivers that are required for being able to boot any board--a UART
driver, the gptimer driver which is used as a clock reference (CNTVCNT
is not supported on the armv7 sc5xx SoCs) and the clock tree driver. Our
From: Nathan Barrett-Morrison
This adds support for the SC5XX clock trees which are required for reading
clock speeds on the SoCs. This is largely a port of the same support for
Linux, which has not yet been submitted upstream.
Co-developed-by: Greg Malysa
Signed-off-by: Greg Malysa
From: Nathan Barrett-Morrison
Co-developed-by: Greg Malysa
Signed-off-by: Greg Malysa
Co-developed-by: Ian Roberts
Signed-off-by: Ian Roberts
Signed-off-by: Vasileios Bimpikas
Signed-off-by: Utsav Agarwal
Signed-off-by: Arturs Artamonovs
Signed-off-by: Nathan Barrett-Morrison
---
(no
Co-developed-by: Nathan Barrett-Morrison
Signed-off-by: Nathan Barrett-Morrison
Co-developed-by: Angelo Dureghello
Signed-off-by: Angelo Dureghello
Co-developed-by: Ian Roberts
Signed-off-by: Ian Roberts
Signed-off-by: Greg Malysa
---
Changes in v2:
- Added gptimer driver to this series
Currently we have the option to tell the console code that we should
ignore the SPL banner. We also have an option to say that we can see it
a second time, and ignore it. However, some platforms such as TI AM64x
will have us see the SPL banner three times. Rather than add an
"spl3_skipped" option,
On Tue, 23 Apr 2024 19:01:44 -0600
Tom Rini wrote:
Hi Tom,
> On Wed, Apr 24, 2024 at 12:46:04AM +0100, Andre Przywara wrote:
> > At the moment enabling CONFIG_SYSRESET_PSCI *selects* SPL_ARM_PSCI_FW,
> > even though this is a platform design property, so nothing any driver
> > should enforce.
Thanks, Jonathan
We also plan on adding a Kconfig option that will autogenerate GUIDs
for such cases, but this is useful
On Fri, 19 Apr 2024 at 23:57, Jonathan Humphreys wrote:
>
> Created a capsule update porting section in the documentation that outlines
> the
> steps a board developer must
Reviewed-by: Otavio Salvador
Tested-by: Otavio Salvador
Em qua., 24 de abr. de 2024 às 11:18, Fabio Estevam
escreveu:
> Instead of using the local rv1108 devicetree copies from U-Boot,
> let's convert the rv1108 boards to OF_UPSTREAM so that the upstream kernel
> devicetrees can be used
On Wed, Apr 24, 2024 at 09:33:25AM -0500, Adam Ford wrote:
> On Tue, Apr 16, 2024 at 6:53 AM Adam Ford wrote:
> >
> > On Thu, Apr 11, 2024 at 7:05 PM Tom Rini wrote:
> > >
> > > On Wed, Apr 03, 2024 at 10:00:09PM -0500, Adam Ford wrote:
> > >
> > > > The da850-evm can remove the U-Boot device
On 4/16/24 10:44, Ondřej Jirman wrote:
From: Ondrej Jirman
According to TRM, the bit that differentiates between MIO and EMIO
clocks is bit 6. This resolves failure to set clock when using EMIO
clock for ethernet.
Not sure which TRM you are using but here
On Tue, Apr 16, 2024 at 6:53 AM Adam Ford wrote:
>
> On Thu, Apr 11, 2024 at 7:05 PM Tom Rini wrote:
> >
> > On Wed, Apr 03, 2024 at 10:00:09PM -0500, Adam Ford wrote:
> >
> > > The da850-evm can remove the U-Boot device trees if migrated
> > > to OF_UPSTREAM. This means pointing the device
Instead of using the local rv1108 devicetree copies from U-Boot,
let's convert the rv1108 boards to OF_UPSTREAM so that the upstream kernel
devicetrees can be used instead.
Tested on a rv1108-elgin-r1 board.
Signed-off-by: Fabio Estevam
---
Changes since v2:
- Also removed the
On 24/04/2024 13:13, Robert Marko wrote:
We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so
lets drop our downstream DTSI.
Signed-off-by: Robert Marko
Acked-by: Caleb Connolly
---
arch/arm/dts/qcom-ipq4019.dtsi | 202 -
1 file
On 24/04/2024 13:13, Robert Marko wrote:
Now that drivers are compatible enough with the upstream DTS, there is no
reason to not use the upstream DTS, so imply OF_UPSTREAM by default.
Signed-off-by: Robert Marko
Acked-by: Caleb Connolly
---
arch/arm/Kconfig | 1 +
1 file changed, 1
On 24/04/2024 13:13, Robert Marko wrote:
Provide basic DRAM info population from DT, cache setting and the
board_init stub.
Signed-off-by: Robert Marko
Acked-by: Caleb Connolly
---
arch/arm/mach-ipq40xx/Makefile | 7 ++
arch/arm/mach-ipq40xx/cpu.c| 44
On 4/21/24 22:27, Marek Vasut wrote:
> On 3/19/24 3:45 AM, Marek Vasut wrote:
>> This patch adds STM32 PWR regulators DT support on stm32mp131.
>> This requires TFA to clear RCC_SECCFGR, is disabled by default
>> and can only be enabled on board DT level.
>>
>> Signed-off-by: Marek Vasut
>
>
Hi Ravi,
Thank you for the patch.
On mer., avril 24, 2024 at 14:15, Marek Vasut wrote:
> On 4/24/24 9:39 AM, Ravi Gunasekaran wrote:
>> From: Aswath Govindraju
>>
>> When the device port is in a low power state [U3/L2/Not Connected],
>> accesses to usb device registers may take a long time.
Enable CONFIG_BOARD_LATE_INIT to use PHYTECs common board_late_init()
to set handy environment variables for u-boot.
Also, resync after savedefconfig.
Signed-off-by: Wadim Egorov
---
configs/phycore_am64x_a53_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git
Factor out code that we can reuse across all our K3 based SoMs.
2nd patch of this series require patch [1] to be applied first.
[1] https://lists.denx.de/pipermail/u-boot/2024-April/552021.html
Wadim Egorov (2):
board: phytec: Commonize board code for K3 based SoMs
Environment handling code can be reused across all our K3 based SoMs.
Instead of adding the same code for every new SoM, move it to a common
board.c file.
Signed-off-by: Wadim Egorov
---
board/phytec/common/Makefile | 2 +
board/phytec/common/k3/Makefile| 2 +
On 16/01/24 17:13, Roger Quadros wrote:
Hi,
On 12/01/2024 08:47, Siddharth Vadapalli wrote:
From: Kishon Vijay Abraham I
Initialize base address of ring config registers required to natively
setup ring cfg registers in the absence of Device Manager (DM) services
at R5 SPL stage.
Number of Qualcomm ARMv7 SoC-s did not use PSCI but rather used PSHOLD
(Qualcomm Power Supply Hold Reset) bit to trigger reset or poweroff.
Qualcomm IPQ40XX is one of them, so provide a simple sysreset driver based
on the upstream Linux one, it is DT compatible as well.
Signed-off-by: Robert
Let's provide get_boot_device() for AM64, similar to what we did
in commit 2f9095e2bf59 ("arm: mach-k3: am625: Provide a way to obtain boot
device for non SPLs") for AM62.
Signed-off-by: Wadim Egorov
---
arch/arm/mach-k3/Makefile | 1 +
arch/arm/mach-k3/am642_init.c | 92
On 4/24/24 9:39 AM, Ravi Gunasekaran wrote:
From: Aswath Govindraju
When the device port is in a low power state [U3/L2/Not Connected],
accesses to usb device registers may take a long time. This could lead to
potential core hang when the controller registers are accessed after the
port is
On 3/22/24 11:57, Sughosh Ganu wrote:
The following patch series adds support for version 2 of the FWU
metadata. The version 2 metadata structure is defined in the latest
revision of the FWU specification [1].
The earlier versions of these patches were migrating to a version 2
only support
Hi Kever,
I also see this issue when switching between Rockchip ATF and Upstream ATF.
Versions:
Rockchip DDR Blob - rk3399_ddr_800MHz_v1.30.bin
Rockchip Miniloader - rk3399_miniloader_v1.30.bin
Rockchip ATF - rk3399_bl31_v1.36.elf
Upstream ATF -
We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so
lets drop our downstream DTSI.
Signed-off-by: Robert Marko
---
arch/arm/dts/qcom-ipq4019.dtsi | 202 -
1 file changed, 202 deletions(-)
delete mode 100644 arch/arm/dts/qcom-ipq4019.dtsi
Now that drivers are compatible enough with the upstream DTS, there is no
reason to not use the upstream DTS, so imply OF_UPSTREAM by default.
Signed-off-by: Robert Marko
---
arch/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index
Provide basic DRAM info population from DT, cache setting and the
board_init stub.
Signed-off-by: Robert Marko
---
arch/arm/mach-ipq40xx/Makefile | 7 ++
arch/arm/mach-ipq40xx/cpu.c| 44 ++
2 files changed, 51 insertions(+)
create mode 100644
[AMD Official Use Only - General]
Hi Greg,
> -Original Message-
> From: Greg Malysa
> Sent: Friday, March 29, 2024 6:15 AM
> To: Bhumkar, Tejas Arvind
> Cc: u-boot@lists.denx.de; ja...@amarulasolutions.com; vigne...@ti.com;
> Simek, Michal ; Abbarapu, Venkatesh
> ; git (AMD-Xilinx) ;
On 24.04.24 09:43, lukas.funke-...@weidmueller.com wrote:
From: Lukas Funke
Rename spl_soc_init() to spl_dram_init() because the generic function
name does not reflect what the function actually does. Also
spl_dram_init() is commonly used for dram initialization and should be
called from
Hi Peter, Andre,
On 4/24/24 12:29, Andre Przywara wrote:
On Tue, 23 Apr 2024 12:55:55 +0200
Quentin Schulz wrote:
Hi Peter,
On 4/23/24 10:10, Peter Hoyes wrote:
From: Peter Hoyes
Polling cntpct_el0 in a tight loop for delays is inefficient.
This is particularly apparent on Arm FVPs,
On Tue, 23 Apr 2024 12:55:55 +0200
Quentin Schulz wrote:
> Hi Peter,
>
> On 4/23/24 10:10, Peter Hoyes wrote:
> > From: Peter Hoyes
> >
> > Polling cntpct_el0 in a tight loop for delays is inefficient.
> > This is particularly apparent on Arm FVPs, which do not simulate
> > real time, meaning
Hi Quentin,
On 4/23/24 11:55, Quentin Schulz wrote:
Hi Peter,
On 4/23/24 10:10, Peter Hoyes wrote:
From: Peter Hoyes
Polling cntpct_el0 in a tight loop for delays is inefficient.
This is particularly apparent on Arm FVPs, which do not simulate
real time, meaning that a 1s sleep can take a
Pinctrl drivers were moved to a dedicated directory but the entry was never
updated, so add the pinctrl-ipq4019 driver entry.
Signed-off-by: Robert Marko
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 207c8b763f..382376b8e3 100644
---
The reset handling was added to the clock drivers but the entry was never
updated, so add the clock-ipq4019 driver instead.
Signed-off-by: Robert Marko
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index fdce7c8334..207c8b763f
The separate clock and reset dt-bindings for IPQ40XX were merged into one
recently, but the entry was not updated so do it now.
Signed-off-by: Robert Marko
---
MAINTAINERS | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index
Luka Kovacic is no longer at Sartura, so remove him as one of IPQ40xx
maintainers.
Signed-off-by: Robert Marko
---
MAINTAINERS | 1 -
1 file changed, 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index d0a4a28b40..8691500d28 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -334,7 +334,6 @@
Hello Jonathan and Kevar,
> I also see this issue when switching between Rockchip ATF and Upstream ATF.
>
> Versions:
> Rockchip DDR Blob - rk3399_ddr_800MHz_v1.30.bin
> Rockchip Miniloader - rk3399_miniloader_v1.30.bin
> Rockchip ATF - rk3399_bl31_v1.36.elf
> Upstream ATF -
Hi Kever,
On 2024-04-23 13:27, Kever Yang wrote:
> Hi Jonas,
>
>
> On 2024/4/1 04:28, Jonas Karlman wrote:
>> This series adds support for new clocks used in linux v6.8 device trees,
>> enables use of FIT signature check for checksum validation and fixes
>> loading FIT from SD-card when loading
Hi Jonas,
On 4/24/24 00:40, Jonas Karlman wrote:
Hi Quentin,
On 2024-04-15 16:16, Quentin Schulz wrote:
From: Quentin Schulz
[...]
+ if (!(tmp_mem_map->attrs & PTE_BLOCK_NON_SHARE)) {
This check does not seem to work because PTE_BLOCK_NON_SHARE evaluates
to 0.
On 4/10/24 21:50, Charlie Johnston wrote:
While working on a third-party board using a ZynqMP, I was unable to use
the zynqmp command even with the proper config definitions. While that
command appears tied to the architecture, it was being included based on
the board selection instead.
This
On 4/15/24 09:55, Michal Simek wrote:
Options are moving to Kconfig by running sed and comments are staying in
that's why do clean up and remove useless comments.
Signed-off-by: Michal Simek
---
include/configs/xilinx_zynqmp.h | 6 --
1 file changed, 6 deletions(-)
diff --git
From: Lukas Funke
On ZynqMp there seems to be a dependency between the card-stable bit and
the card-detect bit. The card-stable bit is set *if and only if*
the card-detect bit was set before, indicating that the signal was
stable and reliable during card insertion.
If the card-detect bit is
From: Lukas Funke
On ZynqMp there seems to be a dependency between the card-stable bit and
the card-detect bit. The card-stable bit is set *if and only if*
the card-detect bit was set before, indicating that the signal was
stable and reliable during card insertion.
If the card-detect bit is
On 24.04.24 09:55, Philip Oberfichtner wrote:
Hi,
I'm wondering if it is currently possible to have U-Boot run in 64-bit
mode as EFI payload.
TARGET_EFI_APP64 selects X86_64 to achieve this. TARGET_EFI_PAYLOAD does
currently always switch 32-bit mode. Any hints what would have to be
done to
On 4/15/24 09:55, Michal Simek wrote:
Options are moving to Kconfig by running sed and comments are staying in
that's why do clean up and remove useless comments.
Signed-off-by: Michal Simek
---
include/configs/xilinx_zynqmp.h | 6 --
1 file changed, 6 deletions(-)
diff --git
From: Peng Fan
Convert to OF_UPSTREAM for i.MX93 11x11 EVK.
Signed-off-by: Peng Fan
---
arch/arm/dts/Makefile| 1 -
arch/arm/dts/imx93-11x11-evk-u-boot.dtsi | 118 +
arch/arm/dts/imx93-11x11-evk.dts | 322 ---
From: Peng Fan
Sync clock header with kernel 6.8
Signed-off-by: Peng Fan
---
include/dt-bindings/clock/imx93-clock.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/clock/imx93-clock.h
b/include/dt-bindings/clock/imx93-clock.h
index
From: Peng Fan
patch 1 is to avoid build break when using upstream dts
Patch 2 is moving to OF_UPSTREAM
This is a resend of V3 imx93: Conver to OF_UPSTREAM patch 5,6
Peng Fan (2):
dt-bindings: imx93: sync clock header
imx: imx93-11x11-evk: convert to OF_UPSTREAM
arch/arm/dts/Makefile
Hi,
I'm wondering if it is currently possible to have U-Boot run in 64-bit
mode as EFI payload.
TARGET_EFI_APP64 selects X86_64 to achieve this. TARGET_EFI_PAYLOAD does
currently always switch 32-bit mode. Any hints what would have to be
done to get it to run in 64-bit mode?
Thanks in advance,
From: Lukas Funke
Rename spl_soc_init() to spl_dram_init() because the generic function
name does not reflect what the function actually does. Also
spl_dram_init() is commonly used for dram initialization and should be
called from board_init_f().
Signed-off-by: Lukas Funke
---
Changes in v3:
From: Lukas Funke
Rename spl_soc_init() to spl_dram_init() because the generic function
name does not reflect what the function actually does. Also
spl_dram_init() is commonly used for dram initialization and should be
called from board_init_f().
Signed-off-by: Lukas Funke
---
(no changes
From: Lukas Funke
This patch series renames spl_soc_init() to spl_dram_init() since the
purpose of the function is to initialization the DRAM on sifive/starfive
boards. spl_dram_init() is a commonly used function for this purpose.
Changes in v3:
- Reorganize patches such that each patch can
Hi Heinrich,
On Wed, 24 Apr 2024 at 10:25, Heinrich Schuchardt wrote:
>
> On 24.04.24 07:03, Ilias Apalodimas wrote:
> > Since we support QueryVariableInfo at runtime now add the relevant
> > tests. Since we want those to be reusable at bootime, add them
> > in a separate file
> >
> > Add tests
From: Aswath Govindraju
When the device port is in a low power state [U3/L2/Not Connected],
accesses to usb device registers may take a long time. This could lead to
potential core hang when the controller registers are accessed after the
port is disabled by setting DEVDS field. Setting the fast
On 24.04.24 07:03, Ilias Apalodimas wrote:
Since we support QueryVariableInfo at runtime now add the relevant
tests. Since we want those to be reusable at bootime, add them
in a separate file
Add tests for
- Test QueryVariableInfo returns EFI_SUCCESS
- Test null pointers for the function
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