On Thu, Apr 25, 2024 at 05:16:12PM +0200, Caleb Connolly wrote:
> Hi all,
>
> On 25/04/2024 15:46, Ilias Apalodimas wrote:
> > Hi Richard,
> >
> > On Thu, 25 Apr 2024 at 15:28, Richard Hughes wrote:
> > >
> > > Hi all!
> > >
> > > > Any ODM/OEM creating a board
> > > > based on the original
Hello Tom,
On 11.04.24 08:09, Michael Nazzareno Trimarchi wrote:
Hi
On Thu, Apr 11, 2024 at 7:06 AM John Watts wrote:
UBI required MTD to build correctly, add it as a Kconfig dependency.
Signed-off-by: John Watts
---
While working with UBI on my SPI NAND patch series I found it was
On Sun, Apr 21, 2024 at 10:48:39PM +0200, Igor Opaniuk wrote:
> Add additional check for buffer size when reading out persistent
> storage value and provide back actual value size.
>
> Signed-off-by: Igor Opaniuk
> ---
>
> drivers/tee/sandbox.c | 10 +++---
> 1 file changed, 7 insertions(+),
On 4/26/24 2:14 AM, Tim Harvey wrote:
eMMC devices have hardware partitions such as user, boot0, and boot1.
Allow these names to be displayed when reading the mmc PARTITION_CONFIG
field via 'mmc partconf'. Additionally allow a name to be specified when
setting the PARTITION_CONFIG.
Before:
On 4/26/24 2:16 AM, Tim Harvey wrote:
diff --git a/drivers/crypto/fsl/Makefile b/drivers/crypto/fsl/Makefile
index 7a2543e16cc..4fbce519a0b 100644
--- a/drivers/crypto/fsl/Makefile
+++ b/drivers/crypto/fsl/Makefile
@@ -6,6 +6,6 @@ obj-y += sec.o
obj-$(CONFIG_FSL_CAAM) += jr.o fsl_hash.o
On 4/25/24 10:34 PM, Tim Harvey wrote:
On Tue, Apr 23, 2024 at 11:33 AM Marek Vasut wrote:
Rework the flash.bin image generation such that it uses the new binman
nxp_imx8mimage etype. This way, the flash.bin is assembled in correct
order using plain binman, without any workarounds or sections
Hello Fabio,
On 26.04.24 03:55, Fabio Estevam wrote:
Hi,
When enabling bootcount on the imx8mm-evk like this:
--- a/configs/imx8mm_evk_defconfig
+++ b/configs/imx8mm_evk_defconfig
@@ -120,3 +120,5 @@ CONFIG_SDP_LOADADDR=0x4040
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_SPL_USB_SDP_SUPPORT=y
Hi,
When enabling bootcount on the imx8mm-evk like this:
--- a/configs/imx8mm_evk_defconfig
+++ b/configs/imx8mm_evk_defconfig
@@ -120,3 +120,5 @@ CONFIG_SDP_LOADADDR=0x4040
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_IMX_WATCHDOG=y
+CONFIG_BOOTCOUNT_LIMIT=y
On Thu, Apr 25, 2024 at 10:35 PM Fabio Estevam wrote:
> This is a nice improvement:
>
> Reviewed-by: Fabio Estevam
There is a typo in the Subject: "partition"
Hi Tim,
On Thu, Apr 25, 2024 at 9:14 PM Tim Harvey wrote:
>
> eMMC devices have hardware partitions such as user, boot0, and boot1.
> Allow these names to be displayed when reading the mmc PARTITION_CONFIG
> field via 'mmc partconf'. Additionally allow a name to be specified when
> setting the
On Thu, Apr 25, 2024 at 4:03 PM Marek Vasut wrote:
>
> Add SPL variant of SPL_FSL_CAAM_RNG so that the SPL_FSL_CAAM_RNG can
> be disabled in SPL if necessary. This may be necessary due to e.g.
> size constraints of the SPL.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Angelo Dureghello
> Cc:
eMMC devices have hardware partitions such as user, boot0, and boot1.
Allow these names to be displayed when reading the mmc PARTITION_CONFIG
field via 'mmc partconf'. Additionally allow a name to be specified when
setting the PARTITION_CONFIG.
Before:
u-boot=> mmc partconf 2 1 1 0 && mmc
Update documentation and use nxp_imx8mcst binman etype for signing
of flash.bin instead of previous horrible shell scripting.
Signed-off-by: Marek Vasut
---
Cc: "NXP i.MX U-Boot Team"
Cc: Adam Ford
Cc: Alper Nebi Yasak
Cc: Andrejs Cainikovs
Cc: Angus Ainslie
Cc: Emanuele Ghidoli
Cc: Fabio
Add new binman etype which allows signing both the SPL and fitImage sections
of i.MX8M flash.bin using CST. There are multiple DT properties which govern
the signing process, nxp,loader-address is the only mandatory one which sets
the SPL signature start address without the imx8mimage header, this
Differentiate between "Enable Random Number Generator support" and
"Enable Random Number Generator support" in Kconfig entry, mark the
first as CAAM and the second as DCP, otherwise users cannot easily
decide which of the options is which and enable the correct one.
Signed-off-by: Marek Vasut
Add SPL variant of SPL_FSL_CAAM_RNG so that the SPL_FSL_CAAM_RNG can
be disabled in SPL if necessary. This may be necessary due to e.g.
size constraints of the SPL.
Signed-off-by: Marek Vasut
---
Cc: Angelo Dureghello
Cc: Emanuele Ghidoli
Cc: Fabio Estevam
Cc: Gaurav Jain
Cc: Heinrich
Add SPL variant of DM_RNG so that the DM_RNG can be disabled in SPL
if necessary. This may be necessary due to e.g. size constraints of
the SPL.
Signed-off-by: Marek Vasut
---
Cc: Angelo Dureghello
Cc: Emanuele Ghidoli
Cc: Fabio Estevam
Cc: Gaurav Jain
Cc: Heinrich Schuchardt
Cc: Marek
Rework the flash.bin image generation such that it uses the new binman
nxp_imx8mimage etype. This way, the flash.bin is assembled in correct
order using plain binman, without any workarounds or sections assembled
in special DT node order.
Reviewed-By: Tim Harvey
Tested-By: Tim Harvey #
Include imx8mq-u-boot.dtsi in the board -u-boot.dtsi to pull in binman
configuration instead of duplicating it in the board -u-boot.dtsi again.
Drop the duplicate binman configuration.
Signed-off-by: Marek Vasut
---
Cc: "NXP i.MX U-Boot Team"
Cc: Adam Ford
Cc: Alper Nebi Yasak
Cc: Andrejs
Add new binman etype derived from mkimage etype which generates configuration
input file for mkimage -T imx8mimage, and runs the mkimage on input data. The
mkimage -T imx8mimage is used to generate combined image with SPL and DDR PHY
blobs which is bootable on i.MX8M.
The configuration file
Fix a typo, no functional change.
Signed-off-by: Marek Vasut
---
Cc: Alper Nebi Yasak
Cc: Simon Glass
Cc: Tom Rini
Cc: u-boot@lists.denx.de
---
tools/binman/btool/mkimage.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/binman/btool/mkimage.py
J7200 has SR1.0 and SR2.0 having three variants of each GP, HS-FS and
HS-SE. Current build does not generate HS-SE SR1.0 and HS-FS SR1.0 so
add support for them.
Reported-by: Suman Anna
Reported-by: Aniket Limaye
Signed-off-by: Neha Malcom Francis
---
arch/arm/dts/k3-j7200-binman.dtsi | 95
J721E has SR1.1 and SR2.0 having three variants of each GP, HS-FS and
HS-SE. Current build does not generate HS-FS SR1.1 so add support for
them.
Reported-by: Suman Anna
Signed-off-by: Neha Malcom Francis
---
Changes since v1:
- removed redundant HS-SE SR2.0 generation
Add support for missing HS SRs in the build for J721E and J7200.
Boot logs (updated for v2):
https://gist.github.com/nehamalcom/e652752623537aced8cf31308015d7c9
Changes since v2:
- removed redundant HS-SE SR2.0 generation for J721E (Andrew)
Neha Malcom Francis (2):
arm: dts: k3-j721e-binman:
Each SoC now has a directory in mach-k3, let's move the SoC specific
files into their respective directories.
Signed-off-by: Andrew Davis
---
arch/arm/mach-k3/Makefile | 27 ++---
arch/arm/mach-k3/am62ax/Makefile| 7 ++
arch/arm/mach-k3/{ =>
On Thu, Apr 25, 2024 at 5:34 PM Tim Harvey wrote:
> Marek,
>
> Thanks - this is neat and I look forward to seeing a CST signing etype!
>
> Reviewed-By: Tim Harvey
>
> I did test this on imx8mm_venice_defconfig and it worked great:
> Tested-By: Tim Harvey # imx8mm_venice
I tested on imx8mm-evk
On Tue, Apr 23, 2024 at 11:33 AM Marek Vasut wrote:
>
> Rework the flash.bin image generation such that it uses the new binman
> nxp_imx8mimage etype. This way, the flash.bin is assembled in correct
> order using plain binman, without any workarounds or sections assembled
> in special DT node
Andrew Davis writes:
> To workaround an issue in AM642 we reset the SoC in early boot. For that
> we first probed the sysreset driver by calling uclass_get_device(). The
> ti-sci sysreset driver is now probed during the ti-sci firmware probe.
> Update this call to probe the firmware driver which
nfc: Synced from Linux commit 7ca2ef33179f ("Linux 6.6-rc1")
nand_all_pins: Synced from Linux commit be18d53c32b2 ("Linux 6.7-rc3")
Signed-off-by: Arseniy Krasnov
---
arch/arm/dts/meson-axg.dtsi | 36
1 file changed, 36 insertions(+)
diff --git
On Thu, 25 Apr 2024 at 16:16, Caleb Connolly wrote:
> I discussed an idea with Ilias to generate GUIDs dynamically based on
> the board compatible/model, which seem to essentially just an
> abstraction on this..
Yup, that works too -- on the assumption the compatible string is unique enough.
>
On Thu, 25 Apr 2024 at 14:46, Ilias Apalodimas
wrote:
> TBH those are GUIDs that are used by virtual devices. It wouldn't hurt
> if someone reused those GUIDs but we can display a warning about it?
Right, I've added some of those to the spreadsheet "never" column.
They'll work for testing
On Thu, Apr 25, 2024 at 05:13:21PM +0100, Richard Hughes wrote:
> On Thu, 25 Apr 2024 at 16:16, Caleb Connolly
> wrote:
> > I discussed an idea with Ilias to generate GUIDs dynamically based on
> > the board compatible/model, which seem to essentially just an
> > abstraction on this..
>
> Yup,
On 4/16/2024 2:50 PM, MD Danish Anwar wrote:
> The series introduces device tree and config changes and AM65x
> to enable ICSSG driver. The series also enables SPL_LOAD_FIT_APPLY_OVERLAY
> for AM65x in order to load overlay over spl.
>
> The ICSSG2 node is added in device tree overlay so that
On Thu, Apr 25, 2024 at 12:59:29PM GMT, Michal Simek wrote:
> > Well, it doesn't help that the code is almost all refering to CLK_CTRL while
> > actually accessing gem1_rclk_ctrl in the struct.
> >
> > In any case it can't detect the case when sourcing the clock from EMIO and
> > not one of the
Hi all,
On 25/04/2024 15:46, Ilias Apalodimas wrote:
Hi Richard,
On Thu, 25 Apr 2024 at 15:28, Richard Hughes wrote:
Hi all!
Any ODM/OEM creating a board
based on the original device must use his own
GUIID to avoid confusion. If not we would end up with different
devices reusing the same
Winbond W25Q256FV and W25Q256JV share the same JEDEC ID, but only
W25Q256JV fully supports 4-byte OPCODE-s.
In order to differentiate between them we can use the SFDP header version
and apply a fixup post BFPT.
Based on upstream Linux commit ("mtd: spi-nor: winbond: Fix 4-byte opcode
support for
Currently, the only way to indicate 4-byte OPCODE support is by setting
the SPI_NOR_4B_OPCODES feature flag for each JEDEC ID in spi_nor_ids[].
However, its becoming increasingly common practice for vendors to reuse
the same JEDEC ID for new revisions of current parts.
For example Winbond
Hi Richard,
On Thu, 25 Apr 2024 at 15:28, Richard Hughes wrote:
>
> Hi all!
>
> > Any ODM/OEM creating a board
> > based on the original device must use his own
> > GUIID to avoid confusion. If not we would end up with different
> > devices reusing the same GUIDs and upgrading their firmware
On 25/04/24 17:57, Roger Quadros wrote:
On 25/04/2024 15:08, Chintan Vankar wrote:
From: Kishon Vijay Abraham I
In order to support Ethernet boot on AM62x, probe AM65 CPSW NUSS
driver in board_init_f().
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Siddharth Vadapalli
Hello Caleb,
On 25.04.24 14:44, Caleb Connolly wrote:
Hi Heiko,
On 25/04/2024 06:28, Heiko Schocher wrote:
Hello Caleb,
On 23.04.24 13:43, Caleb Connolly wrote:
On Mon, 22 Apr 2024 11:33:51 +0200, Neil Armstrong wrote:
Add Support for the Qualcomm Generic Interface (GENI) I2C interface
Hi Heiko,
On 25/04/2024 06:28, Heiko Schocher wrote:
Hello Caleb,
On 23.04.24 13:43, Caleb Connolly wrote:
On Mon, 22 Apr 2024 11:33:51 +0200, Neil Armstrong wrote:
Add Support for the Qualcomm Generic Interface (GENI) I2C interface
found on newer Qualcomm SoCs.
The Generic Interface
On 25/04/24 18:01, Roger Quadros wrote:
On 25/04/2024 15:08, Chintan Vankar wrote:
Add "bootph-all" property to CPSW MAC's PHY node phy_gmii_sel.
Signed-off-by: Chintan Vankar
---
Changes from v1 to v2:
- This patch is newly added in this series to enable CPSW MAC's PHY
node
Hi all!
> Any ODM/OEM creating a board
> based on the original device must use his own
> GUIID to avoid confusion. If not we would end up with different
> devices reusing the same GUIDs and upgrading their firmware with a
> different one.
Yes and no. Of course it's never okay for vendor A to use
On 4/25/24 05:52, tkuw584...@gmail.com wrote:
> From: Takahiro Kuwano
>
> The macronix_octal_fixups should be set only when mfr and flags match.
>
> Fixes: df3d5f9e41 ("mtd: spi-nor: add support for Macronix Octal flash")
> Signed-off-by: Takahiro Kuwano
> Cc: JaimeLiao
> ---
>
On 4/25/24 05:52, tkuw584...@gmail.com wrote:
> From: Takahiro Kuwano
>
> spi_nor_post_sfdp_fixups() was called regardless of if
> spi_nor_parse_sfdp() had been called or not. late_init() should be
> instead used to initialize the parameters that are not defined in SFDP.
>
> Ideally
On 4/25/24 05:52, tkuw584...@gmail.com wrote:
> From: Takahiro Kuwano
>
> The Infineon SEMPER NOR flash family uses 2-bit ECC by default with each
> ECC block being 16 bytes. Under this scheme multi-pass programming to an
> ECC block is not allowed. Set the writesize to make sure multi-pass
>
On 4/25/24 05:52, tkuw584...@gmail.com wrote:
> From: Takahiro Kuwano
>
> default_init() is wrong, it contributes to the maze of initializing
> flash parameters. We'd like to get rid of it because the flash
> parameters that it initializes are not really used at SFDP parsing time,
> thus they
On 25/04/2024 15:08, Chintan Vankar wrote:
> Add "bootph-all" property to CPSW MAC's PHY node phy_gmii_sel.
>
> Signed-off-by: Chintan Vankar
> ---
>
> Changes from v1 to v2:
> - This patch is newly added in this series to enable CPSW MAC's PHY
> node "phy_gmii_sel". As per discussion at
On 25/04/2024 15:08, Chintan Vankar wrote:
> From: Kishon Vijay Abraham I
>
> In order to support Ethernet boot on AM62x, probe AM65 CPSW NUSS
> driver in board_init_f().
>
> Signed-off-by: Kishon Vijay Abraham I
> Signed-off-by: Siddharth Vadapalli
> Signed-off-by: Chintan Vankar
> ---
>
Move GPIO pinmux to MDIO node. Add GB Ethernet reset GPIO.
Add PIN_INPUT to Fix SPE ethernet reset gpio so that
reading the GPIO can give correct status.
Signed-off-by: Roger Quadros
---
arch/arm/dts/k3-am625-beagleplay.dts | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff
Add missing bits in -u-boot.dtsi to get CPSW Ethernet working.
Signed-off-by: Roger Quadros
---
arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi | 63
1 file changed, 63 insertions(+)
diff --git a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
Update k3-am62 DT files from Linux v6.9-rc5
Signed-off-by: Roger Quadros
---
arch/arm/dts/k3-am62-main.dtsi | 126 ++---
arch/arm/dts/k3-am62-mcu.dtsi | 4 +-
arch/arm/dts/k3-am62-phycore-som.dtsi | 5 +-
arch/arm/dts/k3-am62-thermal.dtsi
Sync AM62 device tree files with Linux v6.9-rc5 and
add in the missing bits in -u-boot.dtsi to get CPSW
Ethernet working.
The last patch is marked [not-for-merge] as it is not yet
applied to Linux device tree.
CI testing
https://github.com/u-boot/u-boot/pull/527
Signed-off-by: Roger Quadros
Add "bootph-all" property to CPSW MAC's PHY node phy_gmii_sel.
Signed-off-by: Chintan Vankar
---
Changes from v1 to v2:
- This patch is newly added in this series to enable CPSW MAC's PHY
node "phy_gmii_sel". As per discussion at here:
From: Kishon Vijay Abraham I
Enable config options needed to support Ethernet boot on AM62x SK.
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Siddharth Vadapalli
Signed-off-by: Chintan Vankar
---
Link to v1:
https://lore.kernel.org/r/20240112064759.1801600-10-s-vadapa...@ti.com/
From: Siddharth Vadapalli
Enable DM services for main_pktdma during R5 SPL stage.
Signed-off-by: Siddharth Vadapalli
Signed-off-by: Chintan Vankar
---
Link to v1:
https://lore.kernel.org/r/20240112064759.1801600-11-s-vadapa...@ti.com/
Changes from v1 to v2:
- No changes.
From: Kishon Vijay Abraham I
Add configs for enabling ETHBOOT in R5SPL.
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Andreas Dannenberg
Signed-off-by: Siddharth Vadapalli
Signed-off-by: Chintan Vankar
---
Link to v1:
From: Kishon Vijay Abraham I
In order to support Ethernet boot on AM62x, probe AM65 CPSW NUSS
driver in board_init_f().
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Siddharth Vadapalli
Signed-off-by: Chintan Vankar
---
Link to v1:
From: Vignesh Raghavendra
Expectation of k3_ringacc_ring_reset_raw() is to reset the ring to
requested size and not to 0. Fix this.
Signed-off-by: Vignesh Raghavendra
Signed-off-by: Siddharth Vadapalli
Signed-off-by: Chintan Vankar
---
Link to v1:
From: Kishon Vijay Abraham I
In absence of Device Manager (DM) services such as at R5 SPL stage,
driver will have to natively setup TCHAN/RCHAN/RFLOW cfg registers.
Existing UDMA driver performed the above mentioned configuration
for UDMA. Add similar configuration for PKTDMA here.
From: Kishon Vijay Abraham I
Initialize base address of ring config registers required to natively
setup ring cfg registers in the absence of Device Manager (DM) services
at R5 SPL stage.
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Siddharth Vadapalli
Signed-off-by: Chintan Vankar
From: Kishon Vijay Abraham I
RX_FL_CFG message should not be forwarded to TIFS and should be
handled within R5 SPL (when DM services are not available). Add
a no-op function to not handle RX_FL_CFG messages.
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Siddharth Vadapalli
This series enables Ethernet Boot on SK-AM62 device.
Link to v1:
https://lore.kernel.org/all/20240112064759.1801600-1-s-vadapa...@ti.com/
Changes from v1 to v2:
- Updated dram_init_banksize() function to be called from common section
instead of board specific function call as suggested by Tom.
Initialize DRAM size in SPL stage since networking requires DDR
to be initialized.
Signed-off-by: Chintan Vankar
---
Link to v1:
https://lore.kernel.org/r/20240112064759.1801600-2-s-vadapa...@ti.com/
Changes from v1 to v2:
- Updated dram_init_banksize() function to be called from common
On 25/04/2024 06:02, mwle...@mailtundra.com wrote:
Hi Caleb,
Thanks for this interesting feedback. I saw these patches were already merged
since you sent this but I added a few thoughts below anyway.
Ah, a shame.. It would be good to find a scalable solution to this!
On Friday, April
On 4/25/24 10:23, Ondřej Jirman wrote:
On Wed, Apr 24, 2024 at 04:34:05PM GMT, Michal Simek wrote:
On 4/16/24 10:44, Ondřej Jirman wrote:
From: Ondrej Jirman
According to TRM, the bit that differentiates between MIO and EMIO
clocks is bit 6. This resolves failure to set clock when using
From: Quentin Schulz
RK356x-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.
The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for
reading banks from ATAGS, so let's use the default
From: Quentin Schulz
RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.
The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for
reading banks from ATAGS, so let's use the default
From: Quentin Schulz
RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.
Since ft_board_setup isn't defined anymore, there's no need for
selecting CONFIG_OF_BOARD_SETUP.
Similarly, because the
From: Quentin Schulz
RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.
Since ft_board_setup isn't defined anymore, there's no need for
selecting CONFIG_OF_BOARD_SETUP.
Similarly, because the
From: Quentin Schulz
RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.
Since ft_board_setup isn't defined anymore, there's no need for
selecting CONFIG_OF_BOARD_SETUP.
Similarly, because the
From: Quentin Schulz
RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.
Since ft_board_setup isn't defined anymore, there's no need for
selecting CONFIG_OF_BOARD_SETUP.
Similarly, because the
From: Quentin Schulz
RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.
Since ft_board_setup isn't defined anymore, there's no need for
selecting CONFIG_OF_BOARD_SETUP.
Similarly, because the
From: Quentin Schulz
RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.
Since ft_board_setup isn't defined anymore, there's no need for
selecting CONFIG_OF_BOARD_SETUP.
Similarly, because the
From: Quentin Schulz
RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.
Since ft_board_setup isn't defined anymore, there's no need for
selecting CONFIG_OF_BOARD_SETUP.
Similarly, because the
From: Quentin Schulz
When Rockchip TPL blob is used, the memory areas that can be used for
DRAM is gotten from ATAGS passed through the DRAM at a specific address.
The DDR_MEM tag contains at most 10 areas, so we should default to 10 if
Rockchip TPL blob is used. Note that it is technically
From: Quentin Schulz
Allow RK3568 and RK3588 based boards to get the RAM bank configuration
from the ROCKCHIP_TPL stage instead of the current logic. This fixes
both an issue where 256MB of RAM is blocked for devices with >= 4GB
of RAM and where memory holes need to be defined for devices with
This is a new version of the patch series started by Chris Morgan here:
https://lore.kernel.org/u-boot/20240401181435.553351-1-macroalph...@gmail.com/
Thanks Chris for starting this effort and allowing me to take over the
development.
Allow RK3568 and RK3588 based boards to get the RAM bank
Hi Heinrich,
On Thu, 25 Apr 2024 at 11:32, Heinrich Schuchardt wrote:
>
> On 25.04.24 07:18, Ilias Apalodimas wrote:
> > Since commit c28d32f946f0 ("efi_loader: conditionally enable SetvariableRT")
> > we are enabling the last bits of missing runtime services.
> > Add support for
On Thu, Apr 25, 2024 at 10:23:42AM GMT, megi xff wrote:
> On Wed, Apr 24, 2024 at 04:34:05PM GMT, Michal Simek wrote:
> >
> >
> > On 4/16/24 10:44, Ondřej Jirman wrote:
> > > From: Ondrej Jirman
> > >
> > > According to TRM, the bit that differentiates between MIO and EMIO
> > > clocks is bit
Hi Quentin,
On 2024-04-24 11:11, Quentin Schulz wrote:
> Hi Jonas,
>
> On 4/24/24 00:40, Jonas Karlman wrote:
>> Hi Quentin,
>>
>> On 2024-04-15 16:16, Quentin Schulz wrote:
>>> From: Quentin Schulz
> [...]
>
>>> + if (!(tmp_mem_map->attrs & PTE_BLOCK_NON_SHARE)) {
>>
>> This
On 25.04.24 07:18, Ilias Apalodimas wrote:
Since commit c28d32f946f0 ("efi_loader: conditionally enable SetvariableRT")
we are enabling the last bits of missing runtime services.
Add support for QueryVariableInfo which we already support at boottime
and we just need to mark some fucntions
On Wed, Apr 24, 2024 at 04:34:05PM GMT, Michal Simek wrote:
>
>
> On 4/16/24 10:44, Ondřej Jirman wrote:
> > From: Ondrej Jirman
> >
> > According to TRM, the bit that differentiates between MIO and EMIO
> > clocks is bit 6. This resolves failure to set clock when using EMIO
> > clock for
Hi Heinrich,
On Thu, 25 Apr 2024 at 11:06, Heinrich Schuchardt
wrote:
>
> If the UEFI boot manager fails there is no point in installing the
> device-tree as a configuration table.
>
> Unload image if device-tree cannot be installed.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> v2:
>
If the UEFI boot manager fails there is no point in installing the
device-tree as a configuration table.
Unload image if device-tree cannot be installed.
Signed-off-by: Heinrich Schuchardt
---
v2:
Unload image if device-tree cannot be installed.
---
lib/efi_loader/efi_bootmgr.c | 14
Hi,
On Thu Apr 25, 2024 at 8:19 AM CEST, Ilias Apalodimas wrote:
> I've cc'ed all the people I could find in board specific MAINTAINER files.
> Can you respond to Richard with the proper company name & board name
> so we can bind the following GUIDs to a vendor properly?
> Richard any guidance on
Hi,
On Wed, 24 Apr 2024 13:09:11 +0530, Ravi Gunasekaran wrote:
> When the device port is in a low power state [U3/L2/Not Connected],
> accesses to usb device registers may take a long time. This could lead to
> potential core hang when the controller registers are accessed after the
> port is
Hi,
On 4/25/24 08:19, Ilias Apalodimas wrote:
Hi,
Richard maintains LVFS & fwupd, commonly used for firmware upgrades.
We recently discussed the U-Boot status and supported devices since
fwupd supports capsule updates.
In order to be able to support capsule updates via LVFS manufacturers
Hi,
Richard maintains LVFS & fwupd, commonly used for firmware upgrades.
We recently discussed the U-Boot status and supported devices since
fwupd supports capsule updates.
In order to be able to support capsule updates via LVFS manufacturers
should bind their GUIDs to their devices. Any ODM/OEM
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