Hi Sebastian, You might be using an old YAML file and tring to apply it to a new version of UHD. Take a look at the YAML file for the version of the FPGA closest to what you want. For example, here's the default X410 image in UHD 4.6:
https://github.com/EttusResearch/uhddev/blob/UHD-4.6/fpga/usrp3/top/x400/x410_200_rfnoc_image_core.yml Here's the same YAML with the DRAM commented out and a single FFT block added: https://drive.google.com/file/d/1TojBea56ZuPpXTYUIsgQRDg7F-EbVtWH/view?usp=sharing You'll probably want to tailor this to your use case. Wade On Mon, May 6, 2024 at 7:03 AM <ettus@basti.rocks> wrote: > Hello Piotr, hello everybody, > > i am working with the USRP X410 as well and want to get the FFT Block to > work in RFNoC. > > I have tried to use the yml as it is, but the Plausibility check failed, > which i could resolve by editing the line 143 “dram” -> “dram0”. I guess > this was a typo. > > After 2 h or so i had a .bit file and tried to flash it. However it > doesn’t work and i get the following Message: > > [ERROR] [MPMD::MB_IFACE] Automatic clock detection requested, but no valid > clock index given (63). Make sure FPGA bitfile is up to date! > > [ERROR] [RFNOC::GRAPH] Caught exception while initializing graph: > RuntimeError: NotImplementedError: Automatic clock detection requested, but > no valid clock index given (63). Make sure FPGA bitfile is up to date! > > Do you have any idea what the problem is or can you provide me your > working yml file? > > Please note that i have no in depth experience with FPGA development or > RFNoC and only tried to follow the available guides. > > > Best Regards, > Sebastian > > > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-le...@lists.ettus.com >
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